Supply Voltage Degradation Aware Analytical Placement

Andrew B. Kahng, Bao Liu and Qinke Wang

UCSD CSE Department{abk, bliu, qiwang}@cs.ucsd.edu

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Outline

• Introduction– Motivation– Related work– Our work– Problem formulation

• Analysis and Observations

• Voltage Degradation Aware Placement

• Experiments

• Conclusions

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Motivation

• Increasingly significant voltage degradation along power networks in nanometer VLSI designs– shrinking layout feature sizes– increasing device density

• Logic malfunction

• Performance degradation– a 10% voltage drop could be responsible for 10%

transistor performance degradation, and the effect is super-linear

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Related Work• Techniques to reduce supply voltage

degradation– wiresizing and edge augmentation– decoupling capacitor insertion – circuit de-tuning

• Placement and floorplan related techniques– local placement adjustment to allocate

whitespace for decoupling capacitor insertion– allocation of power pads: more pads close to

current drain hot spots– a floorplan objective for power network

construction and supply voltage drop

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Summary of Existing Works

• Existing voltage drop reduction techniques focus on power supply network design

• Supply voltage degradation is also a function of supply currents of the circuit

• To the best of our knowledge, no analytical placement technique for voltage drop reduction is proposed

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Our Contributions

• We propose voltage degradation aware placement : relocating current drains for voltage drop reduction– represent voltage drop at a power node as a

function of current drains and effective resistances

– propose voltage drop as placement objective and integrate into an analytical placement framework

– test our method on real designs with industry flow

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Model of Power Network

• Power network: modeled as a resistive netlist• parallel metal wires at multiple layers• metal layers connected at crossing points by vias

• Power pads on the top layer: modeled as DC voltage sources

• Active devices at the bottom layer: modeled as DC current drains – DC currents provide bounds for the actual AC

currents

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Problem Formulation

• Given – a power supply network– worst-case current drains for each cell

• Find a placement to– reduce supply voltage drop – maintain comparable placement wirelength,

area, and timing performance

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Outline

• Introduction

• Analysis and Observations– Analysis of voltage drop– Observations on voltage drop optimization– Computation of effective resistance

• Voltage Degradation Aware Placement

• Experiments

• Conclusions

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Analysis of Voltage Drop

• Voltage drop at an observation node t

– each current drain Ik has contribution to the

voltage drop– : effective resistance for a current drain

at node k to inject noise voltage at node t

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An Example Tree-Structure

R2

R1

R3

s

t

I1

I2 I3

• s : power pad

• t : observation node

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Objectives and Observations • Given a power supply network, find a

placement of current drains to minimize:– (a) voltage drop at a given observation node t– (b) average voltage drop of all nodes, or – (c) max voltage drop over all nodes

• (a) : greedy algorithm to locate largest current Ik first to have smallest resistance

• (b) : greedy algorithm to locate largest current Ik first to have smallest resistance

• (c) : NP-hard

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Effective Resistance (I)

• Direct modified nodal analysis

– G: conductance matrix – matrix inversion O(n3)– not feasible for practical power networks

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Effective Resistance (II)

• Random walk [Qian et al. DAC 2003]– resistance of the common part of two random

walk paths that respectively start from nodes k and t and end at a power pad

– a random walk path follows the corresponding current distribution probability: transition probability from node p to q on the random walk path is

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Effective Resistance (III)

• Better scalability and efficiency– contract power netlist by merging bottom-level

wires and computing parallel resistances– compute effective resistance between

observation nodes – apply bi-linear interpolation for supply voltage

drop at any node

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Outline

• Introduction

• Analysis and Observations

• Voltage Degradation Aware Placement– Introduction of analytical placement– Voltage drop aware placement objectives– Implementation

• Experiments

• Conclusions

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Introduction of APlace (I)• APlace: a general analytical placement framework• High solution quality and strong extensibility• Regard Global placement (NP-hard) as a

Constrained Nonlinear Optimization Problem:

– : density function that equals the total module area in a global cell g

– D : average module area over all global cells

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Introduction of APlace (II)• Apply smooth approximation of placement

objectives: wirelength, density function, etc.• Quadratic Penalty method

– solve a sequence of unconstrained minimization problems for a sequence of µ ↓ 0

• Conjugate Gradient solver– find an unconstrained minimum of a high-dimensional

function– memory required is only linear in the problem size,

which makes it adaptable to large-scale placement problems

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Outline

• Introduction

• Analysis and Observations

• Voltage Degradation Aware Placement– Introduction of analytical placement– Voltage drop aware placement objectives– Implementation

• Experiments

• Conclusions

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Average Voltage Drop

• N : the number of observation nodes• : effective resistance for a

current drain Iv to generate a voltage-drop at node g– function of module v's position during global

placement– effective resistance at continuous positions are

obtained using bi-linear interpolation– partial differentials are computed accordingly

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Worst Voltage Drop

• LOG-SUM-EXP function – smooth approximation of worst voltage drop– α: smoothing parameter and significance

criterion for choosing power network nodes with large voltage drop to minimize

– Vworst: strictly convex, continuously differentiable and converges to the worst voltage drop as α converges to 0

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Outline

• Introduction

• Analysis and Observations

• Voltage Degradation Aware Placement– Introduction of analytical placement– Voltage drop aware placement objectives– Implementation

• Experiments

• Conclusions

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Implementation (I)

• Integrate voltage drop objectives into the analytical placement framework

• Wv : weight of the voltage drop objective– computed according to the gradients derived

from the wirelength and voltage drop terms – scaled voltage drop gradients comparable to

wirelength gradients

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Implementation (II)

• β : voltage drop ratio– decide the ratio of voltage drop gradients to

wirelength gradients– provide a knob to trade-off between voltage

drop and wirelength objectives for the placer

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Outline

• Introduction

• Analysis and Observations

• Voltage Degradation Aware Placement

• Experiments– Experimental setup– Results

• Conclusions

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Experimental Setup

• Two industry circuits– TSMC library– six metal layers– power/ground ring at top 2 layers – 4 power pads at the center of boundaries– AES: 5 stripes at M2– PCI: 4 stripes at M6 and 5 large fixed macros

Design #Cells #Rows Tech UtilizationAES 13397 129 90nm 0.6PCI 7128 251 180nm 0.43

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Experimental Flow• Design inputs: synthesized

netlists, technology libraries, timing constraints and floorplans

• Power planning and routing, and pad placement in Cadence SoC Encounter

• Voltage drop aware and oblivious placements using our placer and wirelength-driven APlace

• Fast global and detail routing by Cadence TrialRoute

• Steady-state voltage-drop analysis by Cadence VoltageStorm

Power PlanningPower Route

Pad Place

Voltage Degradation Aware Place

Trial Route

Extract RC

Power Analysis

IR-Drop

Design

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Outline

• Introduction

• Analysis and Observations

• Voltage Degradation Aware Placement

• Experiments– Experimental setup– Results

• Conclusions

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Results (I): Worst Voltage Drop Results of worst voltage-drop aware placements with a variety of voltage drop ratios (β 's)Design Placers Vdrop

Ratio CPU

(V) (%) (V) (%) (e8) (%) (s)

AES APlace 0.00 0.233 0.00% 0.406 0.00% 9.48 0.00% 223.62

our placer 0.05 0.217 6.61% 0.354 12.74% 9.58 -1.10% 286.53

0.10 0.219 6.02% 0.356 12.41% 9.57 -0.94% 265.94

0.15 0.214 8.07% 0.331 18.49% 9.67 -1.95% 239.52

0.20 0.208 10.67% 0.318 21.59% 9.68 -2.09% 227.24

0.25 0.209 10.22% 0.314 22.65% 9.78 -3.17% 217.53

PCI APlace 0.00 0.026 0.00% 0.051 0.00% 19.95 0.00% 120.97

our placer 0.05 0.025 3.18% 0.048 5.54% 20.14 -0.93% 172

0.10 0.025 5.84% 0.046 9.75% 20.25 -1.50% 166

0.15 0.024 9.27% 0.044 13.67% 20.53 -2.92% 156

0.20 0.023 11.52% 0.042 16.65% 20.72 -3.87% 145

0.25 0.023 13.08% 0.041 19.02% 21.01 -5.33% 146

Vdrop Improvements Impact

Avg Vdrop Max Vdrop HPWL

(β)

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Design Placers Vdrop

Ratio CPU

(V) (%) (V) (%) (e8) (%) (s)

AES APlace 0.00 0.233 0.00% 0.406 0.00% 9.48 0.00% 223.62

our placer 0.05 0.219 6.13% 0.361 11.12% 9.50 -0.23% 284.27

0.10 0.210 9.79% 0.343 15.48% 10.04 -5.88% 273.32

0.15 0.209 10.19% 0.341 16.07% 10.12 -6.76% 319.44

0.20 0.201 13.68% 0.320 21.24% 10.28 -8.46% 311.6

0.25 0.192 17.64% 0.302 25.70% 10.40 -9.74% 285.58

PCI APlace 0.00 0.026 0.00% 0.051 0.00% 19.95 0.00% 120.97

our placer 0.05 0.025 4.94% 0.047 6.75% 20.22 -1.35% 160

0.10 0.024 9.14% 0.044 13.06% 21.04 -5.44% 175

0.15 0.019 26.03% 0.035 29.80% 22.83 -14.45% 206

0.20 0.018 31.02% 0.033 35.14% 23.18 -16.18% 234

0.25 0.016 39.54% 0.028 43.99% 25.16 -26.10% 285

Vdrop Improvements Impact

Avg Vdrop Max Vdrop HPWL

Results (II): Average Voltage Drop

Results of average voltage-drop aware placements with a variety of voltage drop ratios (β 's)

(β)

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Summary of Results

• Improvement– worst voltage drop: 22.7% and 19.0% – average voltage drop: 10.2% and 13.1%

• Impact on HPWL: -3.2% and -5.3%

• Worst voltage drop objective leads to better results than average voltage drop objective– large voltage drops are among the first to be

reduced– benefit the average voltage drop more than trying

to reduce all the voltage drops with same efforts

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HPWL vs. Voltage Drop

-5.00%

0.00%

5.00%

10.00%

15.00%

20.00%

25.00%

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Voltage Degradation Ratio

Imp

rove

men

t

Avg Vdrop

Max Vdrop

HPWL

HPWL, worst-case and average voltage-drop improvements as functions of voltage drop

ratio for AES

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Conclusions

• We propose analytical placement for supply voltage drop reduction

• We integrate supply voltage drop objective into an analytical placement framework

• Our experimental results show on average 20.9% improvement of worst-case voltage drop and 11.7% improvement of average voltage drop with only 4.3% wirelength increase

• Ongoing research efforts: supply voltage drop aware timing-driven placement

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Thank You !