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Supporting Information
High-Performance Sub-Micrometer Channel WSe2 Field-Effect
Transistors Prepared Using A Flood-Dike Printing Method
Fanqi Wu,1,§ Liang Chen,2,§ Anyi Zhang,1 Yi-Lun Hong,3,4 Nai-Yun Shih,1 Seong-
Yong Cho,5 Gryphon A. Drake,5 Tyler Fleetham,6 Sen Cong,2 Xuan Cao,1 Qingzhou
Liu,1 Yihang Liu,2 Chi Xu,7 Yuqiang Ma,7 Moonsub Shim,5 Mark E. Thompson,6
Wencai Ren,3 Hui-Ming Cheng,3 and Chongwu Zhou*,1,2
1Department of Chemical Engineering & Materials Science, 2Department of Electrical
Engineering, 6Department of Chemistry, 7Department of Physics & Astronomy,
University of Southern California, Los Angeles, California 90089, United States
3Shenyang National Laboratory for Materials Science, Institute of Metal Research,
Chinese Academy of Sciences, Shenyang 110016, P. R. China
4School of Materials Science and Engineering, University of Science and Technology
of China, 72 Wenhua Road, Shenyang 110016, P. R. China
5Department of Materials Science and Engineering and Materials Research Laboratory,
University of Illinois, Urbana, Illinois 61801, United States
§ These authors contributed equally.
*Address correspondence to: [email protected]
2
1. XPS studies of CVD monolayer WSe2
XPS measurements were carried out to examine the CVD-grown monolayer WSe2
before and after air annealing under 220 °C for 2 h, which were needed to sinter the
gold ink. Figure S1a shows the XPS spectrum of a W 4f core level of as-grown WSe2
on Si/SiO2, with a 4f7/2 and 4f5/2 doublet of WSe2 at 32.3 and 34.4 eV. After air annealing,
the XPS spectrum (Figure S1b) shows stronger doublet peaks of WSe2 at 32.3 and 34.4
eV, and weaker doublet peaks at 35.7 and 37.7 eV which correspond to 4f7/2 and 4f5/2
lines of tungsten oxide (WOx, x≤3). The XPS data (Figure S1) indicates slight oxidation
of WSe2 after air annealing, which is qualitatively consistent with previous studies.1, 2
Figure S1. XPS studies of CVD monolayer WSe2. (a) XPS spectrum of a W 4f core
level of CVD monolayer WSe2 on Si/SiO2 before air annealing. The blue solid line
represents the experimental data. The orange dashed lines are Lorentzian fits for the
peaks of WSe2. (b) XPS spectrum of a W 4f core level of CVD monolayer WSe2 on
Si/SiO2 after annealing in air at 220 °C for 2h. The black solid line represents the
experimental data. The dashed lines in orange and green represent Lorentzian fits for
the peaks of WSe2 and WOx, respectively.
40 38 36 34 32 30
4f5/2
Inte
nsity (
a.u
.)
Binding Energy (eV)
As-grown
WSe2
4f7/2
40 38 36 34 32 30
WOx
4f5/2
4f7/2
Inte
nsity (
a.u
.)
Binding Energy (eV)
4f7/2
4f5/2
WSe2
220 °C a b
3
2. Selective formation of SAM layer on the Au surface
The selective formation of the SAM layer on the surface of the first gold electrode was
evidenced by energy dispersive X-ray (EDX) mapping of Au and S on the SAM-treated
gold electrode and SiO2 (Figure S2), which clearly shows the existence of S on the Au
surface, while the amount of S on the SiO2 surface was negligible.
Figure S2. EDX mapping of Au and S on the surface of the printed gold electrode and
SiO2 substrate after SAM treatment. The mapping area is shown in (a).
In addition, we further studied the hydrophobicity of the Au surface, WSe2 surface and
SiO2 surface before and after SAM treatment, as shown in Figure S3, by placing a
sessile DI water drop on each surface. The water contact angle on the Au surface
increased significantly from ~74.7° before SAM treatment to ~ 116.7° after SAM
treatment (Figure S3a and S3b), indicating the formation of the hydrophobic SAM layer.
In contrast, the water contact angle on the WSe2 surface shows negligible change, from
~96.1° before SAM treatment to ~95.8° after SAM treatment (Figure S3c and S3d),
indicating the SAM does not deposit on the WSe2 surface. Similarly, the water contact
angle on the SiO2 surface shows negligible change, from ~29.2° before SAM treatment
to ~29.0° after SAM treatment (Figure S3e and S3f), indicating the SAM does not
deposit on the SiO2 surface.
Au SSAM-Au
2 μm
a b c
4
Figure S3. Representative optical images of water drops on (a) Au surface, (b) SAM-
treated Au surface, (c) WSe2 surface, (d) WSe2 surface after SAM treatment, (e) SiO2
surface, and (f) SiO2 surface after SAM treatment.
116.7°74.7°DI water on Au DI water on SAM-Au
DI water on WSe2 DI water on WSe2
after SAM treatment96.1° 95.8°
DI water on SiO2DI water on SiO2
after SAM treatment29.2° 29.0°
a b
c d
e f
5
3. Study of wetting property of Au ink on WSe2, SiO2, Au and SAM-Au
We have carried out contact angle measurements by placing a sessile Au ink drop on
WSe2 surface, SiO2 surface, fresh Au surface and SAM-treated Au surface, respectively.
The contact angle of the Au ink drop on the WSe2 surface is ~ 4.8°, indicating good
wetting between the Au ink and the WSe2 surface (Figure S4a). The Au ink also shows
good wettability on the SiO2 surface, with a contact angle of ~ 12.4° (Figure S4b). In
addition, before the SAM treatment, the contact angle of Au ink on the fresh Au surface
is ~ 3.9° (Figure S4c). In contrast, after the SAM treatment, the contact angle of Au ink
on the SAM-treated Au surface increased dramatically to ~ 70.60° (Figure S4d).
Figure S4. Representative optical images of gold ink drops on (a) WSe2 surface, (b)
SiO2 surface, (c) fresh Au surface, and (d) SAM-treated Au surface.
Furthermore, we measured the contact angle of xylene, used as the solvent for the Au
ink, on the WSe2 surface, showing a contact angle of ~ 6.6° (Figure S5).
Figure S5. Representative optical image of a xylene drop on the WSe2 surface.
Au ink on WSe2
Au ink on SAM-Au
Au ink on SiO212.4 °
Au ink on Au
a b
c d 70.60°3.9 °
4.8 °
6.6°Xylene on WSe2
6
4. Additional images of printed sub-micron WSe2 FETs
Figure S6 shows the optical microscope images of three representative WSe2 FETs with
sub-micron channel lengths formed by this printing method. The 1st electrode usually
shows a slightly convex shape, due to the spreading of the gold ink on the WSe2 surface.
In contrast, the edge of the 2nd electrode conforms to the edge of the 1st electrode.
Figure S6. Optical microscope images showing three typical printed WSe2 FETs with
sub-micron channel lengths, fabricated using the “flood-dike” printing method.
Figure S7 shows a representative scanning electron microscopy (SEM) image of a
printed sub-micron WSe2 FET. From this image, a clear gap can be seen between the
two printed electrodes.
Figure S7. SEM image showing a typical sub-micron channel formed by “flood-dike”
printing method.
1st AuElectrode
2nd AuElectrode
20 μm 20 μm
1st AuElectrode
2nd AuElectrode
20 μm
1st AuElectrode
2nd AuElectrode
a b c
50 um
2nd Au Electrode
1st Au Electrode
7
Figure S8 shows a representative low-magnification optical microscope image of two
sub-micron WSe2 FETs printed on the same WSe2 flake using this self-aligned printing
method.
Figure S8. Representative zoomed-out optical microscope image showing two printed
sub-micron channel FETs on a single WSe2 flake.
1st Au Electrode
2nd Au Electrode
2nd Au Electrode
channel channel
100 μm
8
5. Hysteresis study of the printed WSe2 FET
Figure S9a and S9b show the double-sweep transfer characteristics of the representative
WSe2 FET shown in Figure 3, plotted in both logarithm scale (Figure S9a) and linear
scale (Figure S9b), measured under varying integration time of 0.64 ms, 20 ms and 100
ms, from which the hysteresis can be clearly observed. We believe the hysteresis
originates from the absorption of moisture on the WSe2 surface or the charge trapping
at the WSe2/SiO2 interface.3-5 By decreasing the integration time, less hysteresis was
observed (Figure S9a, S9b, and S9e), because shorter integration time reduces the
measuring time and thus reduces the VG stress. The hysteresis can be further reduced
using pulse I-V measurement method, as shown in Figure S9c-e, because the trapped
charges caused by VG stress when VG pulse was on can be detrapped when VG pulse was
off, which resulted in less charge traps (Figure S9f) and less hysteresis. At constant VG
pulse width (ton) of 1 ms, by increasing the pulse period (tperiod), the off time when VG =
VBase = 0 V can be increased, so the trapped charges can have longer time to be
detrapped, which reduces the hysteresis of the WSe2 FET (Figure S9c-f).
9
Figure S9. (a) Logarithm and (b) linear scale of the ID-VG characteristics of a
representative WSe2 FET measured using DC method under VDS = -2 V and different
integration time of 0.64 ms, 20 ms and 100 ms. (c) Logarithm and (d) linear scale of
the ID-VG characteristics of the same WSe2 FET measured by pulse I-V method, with
different pulse period (tperiod) varying from 10-2 s to 1 s under a constant pulse width
(ton) of 10-3 s. The base of VG was set to be 0 V and VDS was -2 V. (e) Comparison of
hysteresis (ΔV) between the forward and backward sweeps for the transfer
characteristics of the WSe2 FET, measured by the conditions in (a-d). The hysteresis
was extracted based on the pink dashed line in (a) and (c), where -ID = 1 nA. (f) Trap
density (ntrap) of the device under different measurement conditions, estimated using
𝑛𝑡𝑟𝑎𝑝 = 𝐶𝑜𝑥 × ∆𝑉/𝑒, where Cox = 1.21x10-8 F/cm2 for 285 nm SiO2.
-100 -50 0 50 1001E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
Backward
-ID (
A)
VG (V)
0.64 ms
20 ms
100 ms
Integration time
Forward
VDS
= -2 V
DC
-100 -50 0 50 100
0
10
20
30
40
Backward
-ID (A
)
VG (V)
0.64 ms
20 ms
100 ms
Integration time
Forward
VDS
= -2 V
DC
-100 -50 0 50 1001E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
backward
-ID (
A)
VG (V)
10-2
10-1
1
Pulse VG
Vbase
= 0 V
VDS
= -2 V
tperiod (s)
ton = 10-3 s
forward
-100 -50 0 50 100-5
0
5
10
15
20
25
30
35
40
45
backward
-ID (A
)
VG (V)
10-2
10-1
1
Pulse VG
Vbase
= 0 V
VDS
= -2 V
tperiod (s)
ton = 10-3 sforward
10
20
30
40
50
60
70
80
90
100
Pulse
period
1 s
Pulse
period
100 ms
Pulse
period
10ms
Short
0.64 msMedium
20 ms
Hyste
resis
(V
)
Long
100 ms
1x1012
2x1012
3x1012
4x1012
5x1012
6x1012
7x1012
8x1012
Pulse
period
1 s
Pulse
period
100 ms
Pulse
period
10ms
Short
0.64 msMedium
20 ms
Long
100 ms
ntr
ap (
cm
-2)
a b
c d
e f
10
6. Comparison of the FET performances for printed 2D TMDC FETs.6-9
Table S1 shows detailed comparison of the FET performances between this work and
previously reported printed FETs based on 2D TMDC materials.6-9
Table S1. Comparison of the device performances for printed 2D TMDC FETs
Reference Channel Contacts Dielectric L
(μm)
VDS
(V)
VG
(V)
Ion/W
(μA/μm)
Ion/Ioff μeff
(cm2/Vs)
Year
This work CVD
WSe2
Printed Au SiO2
(285 nm)
0.75 -2 -
100
0.64 300000 1.00 2017
Kelly et
al.,
Science
MoS2
ink
Fabricated
Au
Ionic
liquid
120 1 2 0.22 100 0.15 2017
Kelly et
al.,
Science
WS2
ink
Fabricated
Au
Ionic
liquid
120 1 -2 0.19 600 0.22 2017
Kelly et
al.,
Science
WSe2
ink
Fabricated
Au
Ionic
liquid
120 1 -2.5 0.09 100 0.08-0.22 2017
Kelly et
al.,
Science
WSe2
ink
Printed
graphene
networks
BN/ionic
liquid
200 1 -2.5 0.003 22 0.08-0.22 2017
Kim et al.,
ACS Nano
CVD
MoS2
Printed Ag SiO2
(270 nm)
100 2 20 0.02 >
10000
1.8 2016
Kim et al.,
ACS Nano
CVD
MoS2
Printed
PEDOT:PSS
Printed
PVP
100 1 80 0.0005 1000 0.27 2017
Li et al.,
Advanced
Functional
Materials
MoS2
ink
Printed Ag SiO2
(300 nm)
13 1 -30 0.0000006 3 - 2014
11
7. Transfer characteristics of the WSe2 FET used for LED control.
Figure S10 shows the transfer characteristics of the WSe2 FET which was used for the
demonstration of LED control as shown in Figure 5. This FET has a channel length of
~680 nm and a channel width of ~142 μm. The transfer characteristics of this device
were measured under different VDS from -0.5 V to -2.0 V in a step of -0.5 V. This device
shows a high on-state current density of ~ 1.11 μA/μm at VDS = -2.0 V, a good on/off
current ratio of ~4.8x105, and an extracted field-effect mobility of 1.40 cm2/Vs.
Figure S10. Transfer characteristics of the LED-driving WSe2 FET, measured under
different VDS, from -0.5 V to -2.0 V in -0.5 V steps.
-100 -50 0 50 100
-160
-120
-80
-40
0
I D (
A)
VG (V)
-0.5 V
-1.0 V
-1.5 V
-2.0 V
VDS
12
8. Structure and electrical properties of QDLED, inorganic LED, and OLED
The external QDLED used for the demonstration of LED control is a double-
heterojunction nanorod (DHNR) LED. Figure S11a shows the energy band diagram of
the DHNR LED, with a schematic diagram showing a DHNR. Figure S11b illustrates
the structure of the DHNR LED. The experimental details about the fabrication process
of DHNR LED can be found in Methods of the manuscript. Figure S11c plots the
current-voltage characteristics of the DHNR LED, showing a low turn-on voltage of
~1.7 V.
Figure S11. (a) Energy band diagram of DHNR LED and a schematic of a DHNR. (b)
Schematic diagram showing the structure of the DHNR-LED. (c) Current-voltage
characteristics of the DHNR-LED.
The external inorganic LED used for LED control experiment was a 3-mm red LED
purchased from radioshack. Figure S12 plots the current-voltage characteristics of the
LED, showing a turn-on voltage of ~1.5 V.
Figure S12. Current-voltage characteristics of the inorganic LED.
-6 -4 -2 0 2 4 6
0.000
0.002
0.004
0.006
0.008
0.010
Curr
ent
(A)
Voltage (V)
a b
HIL
ETL
ITOAl
2
3
4
5
6
7
8
Ene
rgy
(eV
)
+
-
DHNR
HTL
c
0.0 0.5 1.0 1.5 2.0 2.5
0.00
0.02
0.04
0.06
0.08
Curr
ent (A
)
Voltage (V)
13
Figure S13a shows the structure of the external OLED, which is ITO/NPD
(50nm)/Alq3 (50nm)/LiF (1nm)/Al (100nm). Figure S13b shows the current-voltage
characteristics of the OLED with a turn-on voltage of ~ 3.5 V.
Figure S13. (a) Schematic diagrams showing the cross-section view of the OLED
structure. The OLED used in this study is a 4,4'-bis[N-(1-naphthyl)-N-
phenylamino]biphenyl (NPD)/tris(8-hydroxyquinoline)aluminum (Alq3) green light
OLED with aluminum (Al) as the cathode and indium tin oxide (ITO) as the anode. (b)
Current-voltage characteristics of the OLED.
a b
0 2 4 6 8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Curr
ent (m
A)
Voltage (V)
Al1 nm LiF
50 nm Alq3
50 nm NPD
ITO
14
9. “Flood-dike” printing for CVD WSe2 synthesized directly on Si/SiO2
It is worth mentioning that the “flood-dike” self-aligned printing strategy is not limited
to the specific type of CVD WSe2 used in this work. Indeed, it can serve as a general
printing strategy to produce high-performance ultra-short channel TMDC devices. This
printing method is highly compatible with various CVD-grown TMDC flakes, liquid-
exfoliated TMDC inks, continuous TMDC film, etc. We have applied this printing
approach to monolayer WSe2 flakes directly synthesized on Si/SiO2 substrates using a
“traditional” CVD method10-12 (as compared to the ultrafast CVD method13).
a. CVD system setup and materials characterization
In this study, we used WSe2 powder and Se powder as precursors instead of a
combination of WO3 and Se powders. We found that this PVD-like approach gave us a
better uniformity and controllability than the common CVD methods using metal
oxides and selenium. We have successfully achieved two kinds of WSe2 samples with
either triangular shape or hexagram shape by using two different sets of CVD setups as
schematically illustrated in Figure 14a. Specifically, we added a specially designed
inner tube for the hexagram-shape WSe2 growth, where the inner tube has two openings
with the small one facing the upstream and the large one facing the downstream. We
discovered that an inner tube with such a structure can greatly facilitate the hexagram-
shaped growth. Figure S14b and S14c are two representative optical microscopic
images of the as-grown triangle-shaped and hexagram-shaped WSe2 flakes. The lateral
size of an individual flake is around 10 µm for triangle-shaped samples and 20 µm for
hexagram-shaped samples, respectively. According to previous studies, a possible
reason for the hexagram-shaped growth may be due to the unique local environment
created by the special inner tube with a reduced reactant concentrations and a quasi-
static reactant distribution. First, the small front window facing the upstream will
significantly reduce the amount of reactants that were introduced into the inner tube,
therefore reducing the density of nucleation sites. This is clearly evidenced in Figure
S14b and Figure S14c. Then, the reduced nucleation sites would result in less active
growth edges compare to the normal triangle-shaped growth with massive growth edges.
At last, the reduced number of growth edges along with the quasi-static environment
15
ensure a continuous and sufficient reactant supply to all growth edges, resulting in a
uniform growth rate on all directions.14 Similar work has been reported in CVD
graphene growth where six-lobe graphene flowers were synthesized using a gas trap
setup.15 AFM inspection was performed on the hexagram-shaped WSe2 flakes as shown
in Figure S14d. The cross-section height profile along the white dashed line presents a
clear step with a height of ~0.8 nm which is close to the thickness of a monolayer WSe2.
Raman and photoluminescence spectra were further conducted to verify the properties
of the CVD-grown WSe2. Figure S14e is a Raman spectrum taken under a 561 nm
incident laser, where both in-plane 𝐸2𝑔1 and out-plane 𝐴1𝑔 characteristic peaks can be
clearly observed. Meanwhile, no Raman peak for 𝐵2𝑔1 mode was found, indicating the
monolayer status of the CVD-grown WSe2 samples. In addition, the monolayer feature
was further confirmed by PL measurements where a sharp PL emission peak appeared
at ~770 nm, corresponding to the direct bandgap transition of monolayer WSe2 (Figure
S14f).
Figure S14. (a) Schematic diagrams of CVD setups for triangle-shaped WSe2 growth
and hexagram-shaped WSe2 growth. For hexagram-shaped growth, the substrate is
enclosed in a special inner tube with a small opening facing the upstream supplies. (b)(c)
optical microscope images showing the as-grown WSe2 flakes with triangular shapes
(b) and hexagram shapes (c). The lateral size of an individual WSe2 flake is ~10 µm for
triangular-shaped samples and ~20 µm for hexagram-shaped samples. (d) AFM image
10 μm
0.8 nm
200 250 300 350 400 450
Ram
an Inte
nsity (
a.u
.)
Raman Shift (cm-1)
A1g
E1
2g
B1
2g
680 720 760 800 840
PL Inte
nsity (
a.u
.)
Wavelength (nm)
5 μm
e f
20 μm
Triangular WSe2 synthesis
Hexagram WSe2 synthesis
WSe2Se
Se WSe2
a b c
d
16
of a hexagram-shaped WSe2 flake along with the cross-section height profile of the
white dash line. The height of the sample is measured to be ~0.8 nm corresponding to
a monolayer TMDC. (e) Raman spectrum of the as-grown CVD WSe2 showing the two
characteristic peaks of 𝐸2𝑔1 mode and 𝐴1𝑔 mode. (f) PL spectrum of the CVD WSe2
sample showing a strong PL peak at ~770 nm, confirmed the monolayer status.
b. Methods for CVD synthesis of monolayer WSe2 on Si/SiO2
A low-pressure CVD setup was used to synthesize monolayer WSe2 samples.
Specifically, a ceramic boat with 2 mg WSe2 powders (Alfar Aesar, 99.8%) was firstly
placed in the middle of a one-inch quartz tube with another ceramic boat containing 10
mg Se powders (Sigma Aldrich, 99%) sitting at the upstream. The Si/SiO2 substrate
was placed at the downstream about 15 cm away from the WSe2 powder. Then the
furnace will be pumped down to ~900 mTorr with 80 sccm Ar flow mixed with 10 sccm
H2 flow. Once the pressure read-out was stable, the system was ramped up to 1000 °C
in 20 minutes and kept for 15 minutes for growth. After completion, the furnace was
cooled down naturally under the atmosphere of Ar gas. For the hexagram-shaped WSe2
growth, a small inner tube was used to first encapsulate the Si/SiO2 substrate. The rest
were similar to normal CVD growth.
c. Electrical characterization of the printed sub-micron WSe2 FETs
Figure S15 presents the electrical properties of the printed ultra-short channel FETs
based on the monolayer WSe2 synthesized using the “traditional” CVD method (as
compared to the ultrafast CVD growth). The measurements were conducted under
ambient condition with a back-gated structure. Figure S15a shows the transfer
characteristics of a typical printed device on monolayer WSe2 with a channel length of
~0.75 µm and a channel width of ~8 µm. The device was measured at a negative VDS
of -2 V (Figure S15a). A strong unipolar p-type behavior was observed. The inset of
Figure S15a shows the optical microscope image of this device (images of more devices
shown in Figure S16). Figure S15b shows the transfer curve plotted in logarithmic scale
with an Ion/Ioff ratio of 105. The inset of Figure S15b shows the SEM image of this
device. The field-effect mobility (µeff) was also calculated with a value of 0.85 cm2/V·s
which is comparable to the reported value for CVD monolayer WSe2.12 Figure S15c
17
shows a family of output curves (ID-VDS) at various VG from -100 V to -50 V. The non-
linear behavior indicates the existence of Schottky barriers. Figure S15d is the output
curve in the low VDS bias region.
Figure S15. (a) ID-VG transfer curve of a representative printed sub-micron WSe2 FET,
measured at a negative VDS of -2V. The inset shows the optical image of the device. (b)
The transfer curve plotted in a logarithmic scale showing an Ion/Ioff ratio of 105. The
inset shows the SEM image of the device. (c) A family of ID-VDS output curves of the
printed devices showing the existence of Schottky barrier. (d) ID-VDS output curves in
the low-bias region.
Figure S16. Optical microscope images of additional sub-micron channel devices
prepared using “flood-dike” printing method. These devices were printed on monolayer
WSe2 flakes directly synthesized on Si/SiO2.
-100 -50 0 50 100-3
-2
-1
0
I D (
A)
VG (V)
VDS
= -2 V
-100 -50 0 50 10010
-5
10-4
10-3
10-2
10-1
100
101
-ID (
A)
VG (V)
VDS = -2 V
-10 -5 0 5 10
-20
-15
-10
-5
0
5
10
15
I D(
A)
VDS
(V)
VG
-100 V -90 V
-80 V -70 V
-60 V -50 V
-2 -1 0 1 2
-4
-2
0
2
4
VG
-100 V -90 V
-80 V -70 V
-60 V -50 V
I D(
A)
VDS
(V)
a b
c d
10 um
5 um
a b c
20 μm 20 μm 20 μm
18
A systematic statistic study was performed on 14 printed monolayer WSe2 devices to
verify the reliability and reproducibility of the three-step printing process. All the
devices achieved through this SAM-assisted printing technique possess an ultra-short
channel of less than one micrometer while still sustain a high Ion/Ioff ratio of ~ 1.6 x 105
(average) as shown in Figure S17b. The distribution of the on-state current densities
over these 14 devices is shown in Figure S17a, with an average on-state current density
of 0.27 μA/μm. Figure S17c presents the distribution of µeff with an average mobility
of 1.53 cm2/Vs, which is within the range of reported values of as-grown CVD
monolayer TMDCs with a back-gated structure.7, 12
Figure S17. Statistic studies of the performance of printed ultra-short channel devices
on CVD monolayer WSe2 flakes synthesized on Si/SiO2. (a) Ion/W distribution of 14
printed sub-micron monolayer WSe2 FETs, measured under VG = -100 V and VDS = -2
V. (b) Ion/Ioff ratio distribution of the devices printed on monolayer WSe2. (c) Field-
effect mobility distribution of the printed devices on monolayer WSe2, extracted under
VDS = -2 V.
0.00 0.25 0.50 0.75 1.00 1.250
2
4
6
8
10
Co
unts
Ion/W (A/m)
Average Ion/W
~ 0.27 A/m
a b c
2 3 4 5 6 70
1
2
3
4
5
6
7
8
Counts
Log10(Ion/Ioff)
Average Ion/Ioff ratio
~1.6 x 105
0 1 2 3 4 5 6 70
2
4
6
8
10
Co
unts
Mobility (cm2/Vs)
Average mobility
~1.53 cm2/Vs
19
d. Printed sub-micron channel FETs based on few-layer WSe2
The results of the printed ultra-short channel FETs on few-layer WSe2 are presented in
Figure S18 with a higher on-sate current density of 3.70 μA/μm, a reduced Ion/Ioff ratio
of 103 and an increased µeff of 10.4 cm2/Vs, compared to printed monolayer WSe2 FETs.
Figure S18. Printed ultra-short channel devices based on few-layer CVD WSe2. (a) ID-
VG transfer curve measured at a VDS of -2 V. (b) ID-VG transfer curve at a negative VDS
of -2 V in a logarithmic scale. A clear p-type behavior can be observed for few-layer
WSe2 samples. Compared to monolayer WSe2 devices, few-layer WSe2 devices show
higher on-current but lower Ion/Ioff ratio. (c)(d) A family of ID-VDS output curves
measured at different VG. A clear Schottky behavior can be observed from the output
curves.
-100 -50 0 50 100
-30
-20
-10
0
I D (
A)
VG (V)
VDS
= -2 V
-3 -2 -1 0 1 2 3
-50
0
50
I D
(A
)
VDS
(V)
VG
-100 V
-90 V
-80 V
-70 V
-60 V
-50 V
-40 V
-10 -5 0 5 10
-50
0
50
100
I D(
A)
VDS
(V)
VG
-100 V
-90 V
-80 V
-70 V
-60 V
-50 V
-40 V
20 μm
a b
c d-100 -50 0 50 100
1E-7
1E-6
1E-5
-ID (A
)
VG (V)
VDS
= -2 V
20
e. Printed sub-micron monolayer WSe2 FET for inorganic LED and OLED
control. (Using WSe2 synthesized by “traditional” CVD method)
A representative printed sub-micron WSe2 FET was connected with an external
inorganic LED to demonstrate its controllability over inorganic LED (Figure S19a-c).
Figure S19a plots the current through the LED as a function of VG measured under VDD
of 5 V. Figure S19b shows the current through the LED as a function of VDD under VG
from -40 V to -100 V in -10 V steps. Figure S19c shows a series of photographs of the
LED taken under different VG when VDD was fixed at 5 V, illustrating the light intensity
modulation. Similarly, this device was connected with an external OLED to
demonstrate its controllability over OLED (Figure S19d-f). Figure S19d plots the
current through the OLED as a function of VG measured under different VDD from 0 V
to 10 V in 1 V steps. Figure S19e plots the current through the OLED as a function of
VDD under different VG from 0 V to -100 V in -20 V steps. Figure S19f shows a series
of photographs of the OLED taken under different VG at a fixed VDD of 8 V to
demonstrate the light intensity modulation.
21
Figure S19. Printed back-gated sub-micron WSe2 FET for inorganic LED and OLED
control. (a, b) Electrical characteristics of printed WSe2 FET connected to an external
inorganic LED with the circuit diagram shown in the inset. (a) ILED-VG curve measured
under VDD of 5 V. (b) ILED-VDD family curves measured under VG from -40 V to -100 V
in a step of -10 V. (c) Optical images demonstrating the light intensity modulation of
LED by tuning VG at VDD = 5 V. (d, e) Electrical characteristics of printed WSe2 FET
connected to an external OLED. (d) IOLED-VG family curves measured under VDD from
0 V to 10 V in a step of 2 V. (e) IOLED-VDD family curves measured under VG from 0 V
to -100 V in a step of -20 V. (f) Optical images showing the light intensity modulation
of OLED by tuning VG at VDD = 8 V.
VG
VDD
VG = -100V VG = -80V VG = -60V VG = -40V VG = -20V VG = 0V VG = 20V
VG
VDD=5V
VG = -100V VG = -80V VG = -60V VG = -40V VG = -20VVG
VDD = 8 V
a b
c
d e
f
VG
VDD
VG
22
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