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SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
An Industry Perspective on University Research Relations
Marie BurnhamExternal Research
Motorola, SPS
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
STUDENTS
RESEARCH
NETWORKING RELATIONSHIPS
University/Industry Value: University/Industry Value:
I. SIA driven university research organizations:
SRC/MARCO
II. Motorola Intern Program
III. IP and us
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
U.S. Semiconductor IndustryConsortia Partners
Research & Education
SRC FCRP1982 1997
SEMATECH1987
Development & Infrastructure
SIA1977
Tax, Trade &Technology Policy
Agilent TechnologiesAnalog DevicesCypress SemiconductorXilinx
Advanced Micro DevicesAgere SystemsConexant SystemsIBM CorporationIntel CorporationMotorola Texas Instruments
SIA
Micron
LSI LogicNational
Intersil
***DARPA
*NovellusLSI LogicNational
*Axcelis *Cadence *Mentor Graphics *Shipley *Synopsys *Ultratech Stepper **Numerical Technologies
**Coventor**ISE**Mission Research**PDF Solutions**SILVACO **Tessera, Inc**Testchip Technologies
Advanced Micro DevicesAgere SystemsConexant SystemsIBM CorporationIntel CorporationMotorola Texas Instruments
Eastman KodakUMCCharter
**Torrex **Ziptronix ***NIST ***NSF ****ISMT ****SEMI ****SIA * ****SISA *****MITRE Corporation******Compaq SRC
* SRC Science Area Members ** SRC Affiliate Member *** SRC US Gov't Participant **** SRC Strategic Industry Partners ***** SRC Associate Member****** SRC Adjunct Member
Hewlett-Packard
SISA87 Others *Novellus
*Axcelis *Cadence *Mentor Graphics *Shipley *Synopsys *Ultratech Stepper **Numerical Technologies
SIA/SRC/iSEMATECH/SISA/FCRP Membership
Last Update: 10/5/2001
Hyundai Infineon Technologies
Phillips
STMicroelectronics
TSMC
ISMT
Micron
Advanced Micro DevicesAgere SystemsConexant SystemsIBM CorporationIntel CorporationMotorola Texas Instruments
Hewlett-Packard
***DARPA
Agilent TechnologiesAnalog DevicesCypress SemiconductorXilinx
*Novellus
FCRP
Micron
Advanced Micro DevicesAgere SystemsConexant SystemsIBM CorporationIntel CorporationMotorola Texas Instruments
LSI LogicNational
Air ProductsApplied MaterialsKLA-TencorSCP Global Tech.SpeedFam/IPECTeradyneVeriflo
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
• MISSION: Helps solve North American semiconductor industry’s technical challenges with long-range (3-8yr) university research.
• CHARTER: Manage the research done by graduate students for a consortia of 12 full and 23 partial membership companies and government agencies.
• STRATEGY: Provide a framework to make decisions by the SRC management, and full-member company management (BoD, SACCs and TABs), and being responsive to the ITRS formed by the SIA.
The
a tax-free and not-for-profit arm of the SIA
• SIA : Semiconductor Industry Association• ITRS: International Technology Roadmap for
Semiconductors• BoD: Board of Directors• ETAB: Executive Technical Advisory Board• SACC: Science Area Coordinating Committee• TAB: Technical Advisory Board• FCRP: Focus Center Research Program (for
longer term research > 8yrs)• MARCO Microelectronics Advanced Research
COrporation started 2 FCRPs in 1998: Interconnects and Design and Test
• ISMT International Sematech
Lexicon • The SRC funded > $30M of fellowships, grants,
contracts, and projects in 2001
• Motorola has hired almost 160 SRC advanced degree engineers/scientists from ‘89-present.
• The Motorola SRC team is > 90 technologists.
• 850 students supervised by 230 profs on 300 research tasks at 72 univ’s in US, Taiwan, Ca, and Germany
The Numbers ( most are approximate )
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Motorola SRC Science Area OrganizationBoD: Sherry GillespieETAB: Marie Burnham, Cotton Hance
Computer-Aided Design and Test Sciences (CADTS)
Bill Read
Synthesis and VerificationCarl Pixley
Test and Testability
Magdy Abadir
Logic and PhysicalDesign
Pat McGuinnessPradipto Mukherjee
Integrated Circuit Systems Sciences (ICSS)
Chris Chun, Dave Cave
Circuit DesignAndrew Martin
Systems DesignGordon McGregor
Modeling and Simulation
Interconnect Systems
PatterningLloyd Litt, Scott Hector
Front EndProcesses (FEP)
Clarence Tracy, Hsing Tseng
Environment, Safetyand Health (ESH)
Victor Vartanian, H-A Hwang
Back EndProcesses (BEP)
Brad Melnick, Peter Ventzek
Material and Process Sciences (MPS)
Clarence Tracy
Advanced Devicesand Technologies (ADT)
Bruce White, Rainer Thoma
Packaging andInterconnect Systems
Darrel Frear, Andrew Mawer
Factory SystemsShekar Krishnaswami
Nanostructures and Integration Sciences (NIS)
Gari Harris
Cross-disciplinary Semiconductor Research (CSR)
Increased Competitiveness for Industry
SRC’s Role
SRC Concurrently Managed Phases
Initiation Phase
Performance & Evaluation Phase
Tech Transfer Phase
Research Organizations
Universities
National Labs
Research Institutions
Relevantly Educated Scientific Workforce
Advanced Enabling Technologies
Planning PhaseSRC
Participants
Industry
Govt. Agencies
OtherConsortia
Research Selection andFunding Process
Member-driven creation of needs document Request and submission of white papers Member review and selection of proposals to
seek Request for proposals Member review and selection of proposals to
fund Internal SRC Research Management
Committee review Only Excellent Proposals are funded
Three-year contract start (Typical) Annual member reviews of progress Submission of reports and “deliverables” by
researchers
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
2001 SRC University Survey Results to date.
70 of 75 university researchers said SRC was sponsor of choice
SRC is responsive (+) Detailed involvement of industry (+) Attention to the students (-) Funding amounts are too small (-) Administrative overhead is too larger (-) Want more liaison involvement
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
New Research Areas (prioritized):– Optoelectronics: chip-to-chip, integration with electronics.
– Embedded Software: must be research.
– Ultra low power heterogeneous system integration.
– Low cost, high throughput, maskless patterning for VLSI.
Summary Results of SRC ETAB Summer Study (june, 2001)
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Exploratory Research
Semiconductor Research Timeline
N N+1 N+2 N+3 N+4
Incr
easi
ng
Co
st
of
Re
se
arc
h
Industry• Largely company
specific• Product emphasis
SRC• Company specified
research• Student emphasis• Emphasize
technology transfer• Company funded
SEMATECH & SUPPLIERS
• Largely tool specific• Industry
manufacturing standards
• manufacturing path to commercialization
Product Generation
Development
Applied Research
98 01 04 07 10 13
• Bell Labs• IBM Research• GE Research
INDUSTRIAL LABS
DoD R&D Programs
$175,000,000 • Focus Centers ($40-60M)• Nanoelectronics($85M of $.5B)• Litho ($40M)• Moletronics($10M)
$Reduced funding
and
less publically available
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
The Interconnect Focus Center is based at the Georgia Institute of Technology. Professor James Meindl has been the director since the center was established two years ago. The center’s research teams examine six major tasks: system architecture and circuit innovation, physical design tools, novel communications mechanisms, integrated input/output interconnects, materials and processing, predictive modeling and metrology.
Recently, the Massachusetts Institute of Technology was designated as the lead university for a new Materials, Structures and Devices Focus Center. Professor Dimitri Antoniadis is the director. This center will research sub-10-nanometer silicon-based FETS, silicon-based quantum-effect devices, molecular and organic semiconductor electronics, nanotube electronics and modeling & simulation.
A new Circuits, Systems and Software Focus Center was also recently created, with Carnegie Mellon University as the lead university. Professor Rob Rutenbar is the director. The center’s research will focus on the analysis and synthesis of analog and analog/mixed signal circuits, explore novel system level technologies and search for software solutions and work-arounds for the deep submicron CMOS process limitations.
Two years ago, the University of California at Berkeley became the lead university for the Design and Test Focus Center (Gigascale Silicon Research Center). Professor Richard Newton is the center’s director. The Design and Test Center’s research agenda addresses concepts such as component/ communication-based design, constructive fabrics, fully programmable systems, calibration of achievable design, validation, power and energy.
DUSD(S&T)
Design and Test Focus Center
Interconnect Focus Center
Materials Structures & Devices Focus Center
Circuits, Systems & Software Focus Center
UC-Berkeley
CMU MITPenn StatePrincetonPurdueStanfordUniv. of Wisconsin
Focus Center Research Program
Agere IntelAgilent LSI LogicAMD MicronAnalog Devices MotorolaConexant NationalCypress TIIBM Xilinx
UCLAUC – San DiegoUC – Santa BarbaraUC – Santa CruzUniv. of MichiganUT Austin
Air Products SCP GlobalApplied Materials SpeedfamKLA-Tencor TeradyneNovellus Veriflo
DARPA
Prof. Richard Newton
Prof. James Meindl
Prof. Dimitri Antoniadis
Prof. Rob Rutenbar
Georgia Tech
MITStanfordRPIUCLAUniv. of Albany
MIT
CornellPrincetonPurdueStanfordUCLA
UC-BerkeleyUniv. of Albany UT-AustinUVA
CMU
ColumbiaCornellMITPrincetonUniv. of Washington
3
RPIStanfordUC–BerkeleyUIUC
Sponsors:
Deputy Undersecretary of Defense for Science & Technology
Research Teams:
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Motorola’s Intern/Co-op ProgramMotorola’s Intern/Co-op Program
The Motorola Intern/Co-op Program is a strategic college-recruiting tool.
The goal of the program is to identify and attract critical talent for regular
full-time employment.
Tera Martinez
Regional University Relations Manager
(817) 245-2976
Pager: 1800SKYTEL2 PIN# 1332302
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Motorola’s Intern/Co-op ProgramMotorola’s Intern/Co-op Program
Give students real experience
Internships and Co-ops are intended to give the student a way to gain experience in
his/her field of study. It is also a tremendous opportunity for the student to work with
cutting edge technology and to gain “real” work experience. Students can also see what
classes and experiences will be needed to be successful in the industry they choose.
Pre-evaluation
The business has the opportunity to see how well the student works in a particular work
environment. A manager will also be able to see how the student adapts to change and
how quickly they pick up the new technology.
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Motorola’s Intern/Co-op ProgramMotorola’s Intern/Co-op Program
Bring in fresh perspectives
Technology and innovation are dependent upon fresh ideas and creative minds. Some
of these creative minds are currently on the campuses of the colleges and universities.
The Intern/Co-op Program is a way to bring these creative minds into Motorola and
benefit from their innovative thinking.
Promote Motorola on campusStudents that have a positive work experience promote Motorola’s image and products
on campus.
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Benefits of the Intern/ Co-op ProgramBenefits of the Intern/ Co-op Program
To Company
Early exposure to women and underrepresented groups
Special projects for interns often have unexpected positive return
Has available students who might return for expanded assignments
Has opportunity to develop the intern for possible future employment
Has intern as an Mbassador to share experience with other students
Engineering Rotation Program
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Benefits of the Intern/ Co-op ProgramBenefits of the Intern/ Co-op Program
To Intern/Co-ops
Gains meaningful experience which enhances education development
Enhances ability to obtain future employment
Obtains experience and knowledge
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Benchmarking DataBenchmarking Data
Conclusions.
Job Content remains the essential element among effective internshipfactors. Of those who have accept or will accept employment, the topthree reasons they will join the company where they intern are:Job content; Cultural “fit”; and the Quality of management and staff.The corresponding reason students have or decline are: Job content,Cultural “fit”; and Compensation.
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Intern / Coop Program Timeline
Early February Deadline for extension of summer intern/coop offers.April-June Summer interns/coops startLate June Extension of fall intern/coop offersAugust through September Processing of returning intern/coop and returning full-
time new graduate offers Early November Deadline for extension of spring intern/coop offers
Panel Session on IPISPD 2001
3/2/2001
Jeff Parkhurst
Intel Corporation
Direct Industry/University Relationships that require different Intellectual Property Rights (IPR) Agreements: agreements take months
•Centers or Large Collaborative Efforts
•Endowed Chairs
•Government/Industry ERCs
•Sponsored Research Agreements
•Industrial Consortia Memberships
•Bilateral Research Agreements
•Grants
•Consulting Contracts
•Student Internships
Level of DifficultyIndustry
Researcher
...
...
3
4
2
2
1
1
0
Industry LEGAL arm
4
2-3
3
3
2
2
2
1
1
ISPD IPR Panel 3April, 2001
• Objective of university research for industrial researcher:1) research 2) students 3) relationship with professor(s).
• Role of IPR to industrial researcher: protect the company.
• Role of IPR to semiconductor companies: historically defensive, commercialize product not make money from IPR.
• Semiconductor companies understand IPR relationships and how to do business with each other.
• IPR relationship with universities is changing, infinite variety:–IPR policy and objectives changes with each university, each professor at each university, sometimes with students, technical topic, and research contract type. –Legal overhead becoming unmanageable.–Contamination of industrial IPR hampering relationships, research.
IPR, the Semiconductor Industry, and Universities
ISPD IPR Panel 3April, 2001
Successful Negotiation: an Industry Point-of-View
• The industrial and university researchers know how future IPR might be related to the research and what university background IPR might be relevant to the research - absolutely necessary for negotiation.
• Industry notifies professor (and vice versa) when last proposal from industry is sent to university Technology Transfer. Professor checks on proposal 1-2 weeks later.
• Industry researcher has easy access to industry contracts person or lawyer to assist with the process.
• University researcher is interested in contractual issues, especially if the University is.
• If professor, student, or university want the future IPR, then the professor must understand how to protect both the IPR and the industrial collaborator over time.
ISPD IPR Panel 3April, 2001
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Backup
Specification
Implementation
Refinement
Ver
ific
atio
n
Abstract Representation
Compilation/Synthesis/Configuration
Domains
ArchitecturalPlatforms
ImplementationPlatforms
Embedded System(HW/SW)
Source: Ted VucurevichChief Architect
Cadence Design Systems
Source: Ted VucurevichChief Architect
Cadence Design Systems
* Small aspects within GSRC
Embedded System Design: Proposal
Adapted from B. Leheny – 6/01
VLSI Today , Gigahertz Clocking (2000)
Limits to CMOS, ~100Gahertz Clocking (2015?), Gigahertz Clocking (2000)
Transition to Molecular & Quantum Devices, Densities to 1011 cm2, Clocking @ ??
Entry of SRC and MARCO
DARPA University Optoelectronics Centers
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
MathDown 20%
PhysicsDown20%
EngineeringDown40%
The Federal Government Must Balance Its Basic Research Portfolio to Support the ‘Hard Science-based’ Information Technology Engine That Produces the Annual Productivity Increases to Drive the U.S. Economy and Whose Performance, Cost and Size Drive Defense Capabilities.
Academic R&D Sources By Discipline
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Year of Production: 1999 2002 2005 2008 2011 2014
DRAM Half-Pitch [nm]: 180 130 100 70 50 35
Overlay Accuracy [nm]: 65 45 35 25 20 15
MPU Gate Length [nm]: 140 85-90 65 45 30-32 20-22
CD Control [nm]: 14 9 6 4 3 2
TOX (equivalent) [nm]: 1.9-2.5 1.5-1.9 1.0-1.5 0.8-1.2 0.6-0.8 0.5-0.6
Junction Depth [nm]: 42-70 25-43 20-33 16-26 11-19 8-13
Metal Cladding [nm]: 17 13 10 0 0 0
Inter-Metal Dielectric 3.5-4.0 2.7-3.5 1.6-2.2 1.5 <1.5 <1.5
Approaching a “Red Brick Wall”Challenges/Opportunities for Semiconductor R&D
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
From Ralph Cavin, SRC
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Architecture
Non-classical
CMOS
Memory
Logic
Time
Emerging Technology Sequence
Strained Si
Vertical TR FinFET Planar dbl
gate
Phase Change
Nano FG SET Mem Molecular
Magnetic RAM
SETRSFQ QCA Molecular
RTD-FET
Quantum computing
CNNDefect Tolerant
QCA
3D Integration
FD SOI
molecular
Tech Vectors
From Ralph Cavin, SRC
SWEEDA WORKSHOP Sedona, AZExternal Research Group, Marie Burnham 16Nov01
Emerging Research Memory Devices
Baseline 2002Technologies Magnetic RAM
PhaseChangeMemory
Nano FloatingGate Memory
Single/FewElectron
MemoriesMolecular Memory
StorageMechanism
ChargedCapacitor
Device Types DRAMNORFlash
Pseudo-Spin-Valve
MagneticTunnel
JunctionOUM
-EngineeredBarrier-Nanocrystal
SET-Bistable switch-Molecular NEMS-Spin based moleculardevices
Availability 2002 ~2004 ~2004 ~2004 >2005 >2007 >2010Initial F Value 130 nm 150 nm 350 nm 130 nm 100 nm 80 nm 65 nm 45 nm
Cell size8F2
0.14 m2
1T
10F2
0.19 m2
1T
~40F2
4.9 m2
2T
20 to 40F2
0.68 m2
1T
~6F2
0.06 m2
1T
4 to 10F2
0.04 m24 to 9F2
~0.04 m2~2F2
~0.004 m2
Access time <20 ns ~80 ns <25 ns <10 ns <100 ns <10 ns <10 ns ~10 nsStore time <20 ns ~1 ms <25 ns <10 ns <100 ns <10 ns <100 ns ~10 nsRetention 64 ms >10 yrs >10 yrs >10 yrs >10 yrs > 10 yrs Sec to minutes DaysE/W cycles >1E5 >1E15 >1E13 >1E13 >1E6 >1E9 >1E15Maturity production development development demonstrated demonstrated demonstrated
GeneralAdvantages
DensityEconomy
NonvolatileNonvolatile, High
endurance, Fast read &write, Rad Hard, NDRO
Nonvolatile,Low Power,
NDRORad Hard
Nonvolatile,Fast read &
write
DensityPower
Density, PowerIdentical switcheslarge 1/0 difference
Opportunities for 3DEasier to interconnect
Defect tolerant circuitry
Challenges Scaling Scaling
Integration issues,Material Quality, Controlmagnetic properties for
write operations
Newmaterials &integration
MaterialQuality
Dimensioncontrol (Room
temp operation),Background
charge
VolatileThermal stability
From Ralph Cavin, SRC