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Texas Instruments – 2016/17 Power Supply Design Seminar
Louis DianaRobert Sheehan
Switch-mode power converter compensation made easy
Texas Instruments – 2016/17 Power Supply Design Seminar
Agenda
• Compensation design and objectives• Explanation of poles and zeros• Power stage characteristics• Error amplifier and transconductance amplifier• Isolated feedback with optocoupler• Compensation examples• Circuit limitations and other issues
3-2
Texas Instruments – 2016/17 Power Supply Design Seminar
Compensation design and objectives
• Feedback is needed to regulate the output voltage
• The bandwidth of the control loop determines the response time
Why do we need feedback and why do we need compensation?
3-3
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop response
• Response is under-damped causing oscillatory behavior
• Response is well damped with good settling behavior
• Maximize crossover frequency for fastest transient response
• Adjust compensation for best settling behavior
Good transient responseObjectivePoor transient response
VOUT
IOUT
VOUT
IOUT
3-4
Texas Instruments – 2016/17 Power Supply Design Seminar
Phase margin and gain margin
• Sufficient phase margin is needed to prevent oscillation (45º min.)
• Gain margin goal 10 dB min.• Slope of –20 dB/decade when passing
through 0 dB• Bandwidth rule of thumb is 1/5 to 1/10
of switching frequency
Phase margin and stability
-90
-45
0
45
90
135
-40
-20
0
20
40
60
100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
Control loop – frequency response
Phase margin
Gain margin
3-5
Texas Instruments – 2016/17 Power Supply Design Seminar
Poles and zerosZeroPole
P
ssH
1
1)(
1
1)( Z
s
sH
-135
-90
-45
0
45
-60
-40
-20
0
20
10 100 1,000 10,000 100,000 1,000,000PH
ASE
(°)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
-45
0
45
90
135
-20
0
20
40
60
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)FREQUENCY (Hz)
3-6
Texas Instruments – 2016/17 Power Supply Design Seminar
Inverted and right-half-plane zerosRight-half-plane zeroInverted zero
1
1)( ssH
Z
1
1)( Z
s
sH
-135
-90
-45
0
45
-20
0
20
40
60
10 100 1,000 10,000 100,000 1,000,000PH
ASE
(°)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
-135
-90
-45
0
45
-20
0
20
40
60
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)FREQUENCY (Hz)
3-7
Texas Instruments – 2016/17 Power Supply Design Seminar
Complex conjugate pole and ESR zeroWith ESR zeroComplex conjugate pole
2
2
1
1)(
OOO
sQs
sH
2
2
1
1)(
OOO
Z
sQs
s
sH
-180
-135
-90
-45
0
45
-80
-60
-40
-20
0
20
10 100 1,000 10,000 100,000 1,000,000PH
ASE
(°)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
-180
-135
-90
-45
0
45
-80
-60
-40
-20
0
20
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)FREQUENCY (Hz)
Gain
Phase
Q = 2Q = 1Q = 0.5Q = 0.25
3-8
Texas Instruments – 2016/17 Power Supply Design Seminar
Control methods and operating modes
• Voltage-mode control
• Current-mode control
Switching frequency and period
Control methods
Operating modes
SWfT 1
• Fixed frequency
• Continuous conduction-mode (CCM)
• Switching frequency – fSW
• Switching period – T
3-9
Texas Instruments – 2016/17 Power Supply Design Seminar
Buck, boost and buck-boost derived topologies• Forward• Two switch forward • Active clamp forward• Half bridge
P
SINOUT N
NDVV
• Push-pull• Full bridge• Phase-shifted full
bridge DVV INOUT
P
SINOUT N
NDVV 2
Buck-boost, SEPIC, flyback
Buck, forward,
push-pull, bridge
DVV INOUT
1
• Boost topology
DDVV INOUT
• Buck-boost derived topologies
• SEPIC• Cuk
Boost
• Flyback
P
SINOUT N
NDDVV
On-time duty cycle:D
Off-time duty cycle:D′ = 1 - D
3-10
Texas Instruments – 2016/17 Power Supply Design Seminar
Voltage-mode buck power stage
OUTO CL
1
OUTESRZ CR
1
2
2
1
1
ˆˆ
OOO
ZVC
C
OUT
sQs
s
Avv
OUT
OUTO
CLRQ
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
VCA
2O
2Z
RAMP
INVC V
VA
3-11
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode buck power stage
OUTESRZ CR
1
OUTOUTP RC
1LRK im
L
SLOPE
INm V
VK i
OUTVC R
RA
LP
ZVC
C
OUT
ss
s
Avv
11
1
ˆˆ
VIN
COUT
RESR
ROUT
LVOUT
+ +
VC+- VSLOPEPWM
A
LogicRS
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
VCA
2P
2Z
2L
at D = 0.5
Si RAR
3-12
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode boost power stage
OUTESRZ CR
1
OUTOUTP RC
2
LRK im
L
SLOPE
OUTm V
VK
i
OUTVC R
DRA
2
LP
ZRVC
C
OUT
ss
ss
Avv
11
11
ˆˆ
LDROUT
R
2
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
VCA
2P
2R
2L
2Z
at D = 0.5
Si RAR
3-13
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode buck-boost power stage
OUTESRZ CR
1
OUTOUTP RC
D
1
LRK im
L
SLOPE
OUTINm V
VVK
i
OUTVC RD
DRA
1
LP
ZRVC
C
OUT
ss
ss
Avv
11
11
ˆˆ
DLDROUT
R
2
at D = 0.5
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
VCA
2P
2R
2L
2Z
Si RAR
3-14
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode forward power stage
OUTESRZ CR
1
OUTOUTP RC
12
P
SimL N
NLRK
SLOPE
INm V
VK S
P
i
OUTVC N
NRRA
LP
ZVC
C
OUT
ss
s
Avv
11
1
ˆˆ
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
VCA
2P
2Z
2L
at D = 0.5
Si RAR
3-15
CIN
Q1
D1VIN
VSLOPE
+
+-
PWM
VC
Logic
T1NP : NS
D2
L
RS
A
COUT
RESR
ROUT
VOUT
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode flyback power stage
OUTESRZ CR
1
OUTOUTP RC
D
1
P
imL L
RK
SLOPE
S
POUTIN
m VNNVV
K
S
P
i
OUTVC N
NRDDRA
1
LP
ZRVC
C
OUT
ss
ss
Avv
11
11
ˆˆ
22
S
P
P
OUTR N
NDLDR
at D = 0.5
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
VCA
2P
2R
2L
2Z
Si RAR
3-16
+
Texas Instruments – 2016/17 Power Supply Design Seminar
Type I error amplifier
COMPFBTEA CR
1
svv EA
OUT
C
ˆˆ
-90
-45
0
45
90
135
-40
-20
0
20
40
60
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
2EA
3-17
Texas Instruments – 2016/17 Power Supply Design Seminar
Type II error amplifier
COMPCOMPZEA CR
1
HFCOMP CC HFCOMP
HF CR
1
FBT
COMPVM R
RA -45
0
45
90
135
180
-20
0
20
40
60
80
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
2ZEA
VMA
2HF
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
HF
ZEAZEAVM
s
s
sA
1
1
Assumption:
3-18
Texas Instruments – 2016/17 Power Supply Design Seminar
Type II transconductance amplifier
COMPCOMPZEA CR
1
COMPEAHFCOMP RRCC &
COMPmFBVM RgKA
HFCOMPHF CR
1
FBTFBB
FBBFB RR
RK
EAmOL RgA
HF
ZEAZEAVM
s
s
sA
1
1
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
Assumptions:
-45
0
45
90
135
180
-20
0
20
40
60
80
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
2ZEA
VMA
2HF
3-19
Texas Instruments – 2016/17 Power Supply Design Seminar
Type III error amplifier
COMPCOMPZEA CR
1
FFFBTFZ CR
1
FFFFFP CR
1HFCOMP
HF CR
1
FBT
COMPVM R
RA
HFFP
FZ
ZEA
VMOUT
C
ss
ss
Avv
11
11
ˆˆ
FFFBTHFCOMP RRCC &
0
45
90
135
180
225
270
-40
-20
0
20
40
60
80
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
2ZEA
VMA 2HF
2FZ
2FP
HFFP
FZZEAZEAVM
ss
ss
sA
11
11
Assumptions:
3-20
Texas Instruments – 2016/17 Power Supply Design Seminar
Isolated feedback with optocoupler
-45
0
45
90
135
180
-20
0
20
40
60
80
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
2ZEA
VMA
2HF
D
PVM R
RCTRA
COMPFBTZEA CR
1
PPHF CR
1
F
C
IICTR
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
HF
ZEAZEAVM
s
s
sA
1
1
3-21
Texas Instruments – 2016/17 Power Supply Design Seminar
Voltage-mode buck
Output filter
Error amplifier
Modulator
IN
OUT
VVD
IN
OUTIN
VVVD
3-22
Texas Instruments – 2016/17 Power Supply Design Seminar
Voltage-mode buck compensation strategy• Choose a value for RFBT based on bias current and power
dissipation• Pick target bandwidth, typically fSW/10:
ωC = 2·π·fC• Find the mid-band gain AVM to achieve target bandwidth• Set ωZEA and ωFZ equal to the output filter complex conjugate
pole ωO:ωZEA = ωFZ = ωO
• Set ωFP equal to the output filter zero ωZ:ωFP = ωZ
• Set ωHF equal to half the switching frequency: ωHF = 2·π·fSW/2
FBTFZFF RC
1
FFFPFF CR
1
OVC
CVM ωA
ωA
FBTVMCOMP RAR
COMPZEACOMP RC
1
COMPHFHF RC
1
3-23
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop
Error amplifier
Power stage
Voltage-mode buck compensation results
OUT
C
C
OUT
OUT
OUT
vv
vv
vv
ˆˆ
ˆˆ
ˆˆ
HFFP
FZ
ZEA
VMOUT
C
ss
ss
Avv
11
11
ˆˆ
2
2
1
1
ˆˆ
OOO
ZVC
C
OUT
sQs
s
Avv
-180-135-90-45045
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
VCA
2O
2Z
4590135180225270
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
2&
2FZZEA
VMA
2HF
2FP
-90-4504590135
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
2C
3-24
Texas Instruments – 2016/17 Power Supply Design Seminar
Output filter
Error amplifier
Modulator
Isolated current-mode flyback
OUTP
SIN
OUT
VNNV
VD
S
POUTIN
IN
NNVV
VD
+3-25
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode flyback compensation strategy
(mod)m
OUTCVM G
CA
S
P
im N
NRDG
(mod)
22
S
P
P
OUTR N
NDLDR
• Choose a value for RFBT based on bias current and power dissipation
• Find the modulator transconductance in A/V• Find the RHPZ frequency at minimum input voltage and
maximum load current• Set the target bandwidth to 1/4 of the RHPZ frequency:
ωC = 2·π·fC = ωR/4• Find the mid-band gain AVM to achieve target bandwidth
Adjust RD, RP and COUT as required• Set ωZEA equal to 1/10 the target crossover frequency:
ωZEA = ωC/10• Set ωHF equal to the lower of the RHP or ESR zero
frequency:ωHF = ωR or ωZ
VMAP
DRCTRR
ZEAFBTCOMP RC
1
HFPP RC
1
3-26
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop
Error amplifier
Power stage
Current-mode flyback compensation results
LP
ZRVC
C
OUT
ss
ss
Avv
11
11
ˆˆ
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
OUT
C
C
OUT
OUT
OUT
vv
vv
vv
ˆˆ
ˆˆ
ˆˆ
-180-135-90-45045
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
4590135180225270
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
-90-4504590135
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
VCA
2C
2P
2Z
2ZEA
VMA
2HF
2R
2L
3-27
Texas Instruments – 2016/17 Power Supply Design Seminar
Bandwidth vs. transient responseCurrent-mode transient responseCurrent-mode bandwidth
-90-4504590135
-40-20
0204060
100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (Hz)
vPtP
∆I
With no ESR, slew rate or duty cycle limiting:
Current-mode single pole approximation:
Current-mode critically damped:
Voltage-mode:
fC
CP ft
41 s
kHztP 25
1041
OUTCP Cf
IV
8
OUTCP Cf
IV
2
OUTCP Cfe
IV
mV
FkHzeAVP 130
440105
mVFkHz
AVP 180440102
5
mVFkHz
AVP 140440108
5
shown above
3-28
Texas Instruments – 2016/17 Power Supply Design Seminar
Switching regulator with poor compensation
4590135180225270
-40-20
0204060
0.1 1 10 100 1000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (kHz)
Error amplifier
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
0.1 1 10 100 1000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (kHz)
Power stage
-90
-45
0
45
90
135
-40
-20
0
20
40
60
0.1 1 10 100 1000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (kHz)
Control loop
• Power stage: phase at –180°indicates high internal slope compensation
• Error amplifier: zero appears high and mid-band gain is 3 dB
• Control loop: fC is 95 kHz with only 20° phase margin
VOUT
IOUT
Transient response
U1
VIN
GND
EN
SS/TR RT/CLK
BOOTPH
VSENSE
COMP
VIN
0.1 μF
10 nF 100 kΩ
3.3 μH
31.6 kΩ
10 kΩ
5 kΩ
1 nF
47 μF
VOUT
15 μF
22 μF effective
capacitance
TPS54620
3-29
Texas Instruments – 2016/17 Power Supply Design Seminar
Switching regulator with revised compensation
4590135180225270
-40-20
0204060
0.1 1 10 100 1000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (kHz)
Error amplifier
-180
-135
-90
-45
0
45
-60
-40
-20
0
20
40
0.1 1 10 100 1000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (kHz)
Power stage
-90
-45
0
45
90
135
-40
-20
0
20
40
60
0.1 1 10 100 1000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
FREQUENCY (kHz)
Control loop
• Power stage: cannot change slope compensation
• Error amplifier: decrease RCOMP and rescale CCOMP
• Control loop: now fC is 30 kHz with 67° phase margin
VOUT
IOUT
Transient response
U1
VIN
GND
EN
SS/TR RT/CLK
BOOTPH
VSENSE
COMP
VIN
0.1 μF
10 nF 100 kΩ
3.3 μH
31.6 kΩ
10 kΩ
1 kΩ
10 nF
47 μF
VOUT
15 μF
22 μF effective
capacitance
TPS54620
3-30
Texas Instruments – 2016/17 Power Supply Design Seminar
Practical limitations
• Error amp BW can limit maximum fC
• Wider BW op amp needed for voltage-mode due to Type III compensation
• Resistance seen by output transistor forms a pole in kHz range
• More of an issue for forward topologies at higher fC
• Maximum fC is a fraction of fSW
• Rule of thumb is 1/5 to 1/10 of fSW
3-31
Texas Instruments – 2016/17 Power Supply Design Seminar
DCM vs. CCM characteristics
• Discontinuous conduction-mode (DCM) occurs when the inductor current dwells at zero before the end of the switching cycle
• This causes a reduction in the bandwidth• Generally, if the loop is stable in CCM, it will be stable in DCM
• Buck
• Boost
• Buck-boost
DCM duty cycle
IN
OUTOUTSW
VVIfL
D
2
IN
INOUTOUTSW
VVVIfL
D
2
OUTININ
OUTOUTSW
VVVVIfLD
2
3-32
Texas Instruments – 2016/17 Power Supply Design Seminar
Filter considerations
• Capacitors: make COUT1 smaller than COUT2• Inductors: make L2 smaller than L1• Resonance: make second stage filter
resonance 3 times fC• Damping: make second stage filter damped
to a Q of 1
• Characteristic impedance• Damping factor
Second stage filtersInput filter stability
For stability: Filter ZOUT << Converter ZIN
IN
INS C
LZ
IN
S
S
CL
ZZ
ZRR
21
3-33
Texas Instruments – 2016/17 Power Supply Design Seminar
Summary
• Identify poles and zeros of the power stage• Cancel with zeros and poles in the error amp• Adjust the gain for best performance
3-34
Texas Instruments – 2016/17 Power Supply Design Seminar
Resources and references• “Closing the Feedback Loop” by Lloyd Dixon, SEM300
• “Current-Mode Control of Switching Power Supplies” by Lloyd Dixon, SEM400
• “The Right-Half-Plane Zero -- A Simplified Explanation” by Lloyd Dixon, SEM500
• “Isolating the Control Loop” by Robert Mammano, SEM700
• “Control Loop Design” by Lloyd Dixon, SEM800
• “Control Loop Cookbook” by Lloyd Dixon, SEM1100
• “A More Accurate Current-Mode Control Model” by Ray Ridley, SEM1300
• “Designing Stable Control Loops” by Dan Mitchell and Bob Mammano, SEM1400
• “Current-Mode Modeling – Reference Guide” by Robert Sheehan, SNVA542
• “Understanding and Applying Current-Mode Control Theory” by Robert Sheehan, SNVA555
• “Frequency Compensation and Power Stage Design for Buck Converters to Meet Load Transient Specifications” by S. Bag, R. Sheehan, et al., APEC 2014
3-35
Texas Instruments – 2016/17 Power Supply Design Seminar
Appendix
• Current-mode buck compensation• Current-mode boost compensation• Current-mode buck-boost compensation• Isolated compensation techniques• Isolated forward converter compensation
3-36
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode buck
Output filter
Error amplifier
Modulator
IN
OUT
VVD
IN
OUTIN
VVVD
3-37
Texas Instruments – 2016/17 Power Supply Design Seminar
FBTVMCOMP RAR
Current-mode buck compensation strategy
FBm
VMCOMP Kg
AR
COMPHFHF RωC
1
COMPZEACOMP RωC
1
(mod)m
OUTCVM G
CA
im RG 1(mod) • Choose a value for RFBT based on bias current and power
dissipation• Find the modulator transconductance in A/V• Pick target bandwidth, typically fSW/10:
ωC = 2·π·fC• Find the mid-band gain AVM to achieve target bandwidth• Set ωZEA equal to 1/10 the target crossover frequency:
ωZEA = ωC/10• Set ωHF equal to the ESR zero frequency:
ωHF = ωZ
(op amp)
(gm amp)
3-38
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop
Error amplifier
Power stage
Current-mode buck compensation results
LP
ZVC
C
OUT
ss
s
Avv
11
1
ˆˆ
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
OUT
C
C
OUT
OUT
OUT
vv
vv
vv
ˆˆ
ˆˆ
ˆˆ
-90-4504590
-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
4590135180225
-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
-90-4504590135
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
VCA
2C
2P
2Z
2ZEA
VMA 2HF
2L
3-39
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode boost
Output filter
Error amplifier
Modulator
OUT
INOUT
VVVD
OUT
IN
VVD
VIN
CIN
RCOMP
CCOMP
COUT
RESRROUT
L
RFBT
RFBB
VOUT
VREF
+ +
VFBVC
Logic VSLOPE
Peak current-mode boostOptimal VSLOPE = (VOUT - VIN)·Ri·T/L
CHF
gm+-
PWM+-
Ri
3-40
Texas Instruments – 2016/17 Power Supply Design Seminar
FBTVMCOMP RAR
Current-mode boost compensation strategy
FBm
VMCOMP Kg
AR
COMPHFHF RωC
1COMPZEA
COMP RωC
1
(mod)m
OUTCVM G
CA
im R
DG
(mod)• Choose a value for RFBT based on bias current and power dissipation
• Find the modulator transconductance in A/V
• Find the RHPZ frequency at minimum input voltage and maximum load current
• Set the target bandwidth to 1/4 of the RHPZ frequency:ωC = 2·π·fC = ωR/4
• Find the mid-band gain AVM to achieve target bandwidth
• Set ωZEA equal to 1/10 the target crossover frequency:ωZEA = ωC/10
• Set ωHF equal to the lower of the RHP or ESR zero frequency:ωHF = ωR or ωZ
LDROUT
R
2
(op amp)
(gm amp)
3-41
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop
Error amplifier
Power stage
Current-mode boost compensation results
LP
ZRVC
C
OUT
ss
ss
Avv
11
11
ˆˆ
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
OUT
C
C
OUT
OUT
OUT
vv
vv
vv
ˆˆ
ˆˆ
ˆˆ
-180-135-90-45045
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
4590135180225270
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
-90-4504590135
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
VCA
2C
2P
2Z
2ZEA
VMA
2HF
2R
2L
3-42
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode buck-boost
Output filter
Error amplifier
Modulator
OUTIN
OUT
VVVD
OUTIN
IN
VVVD
3-43
Texas Instruments – 2016/17 Power Supply Design Seminar
FBTVMCOMP RAR
Current-mode buck-boost compensation strategy
FBm
VMCOMP Kg
AR
COMPHFHF RωC
1COMPZEA
COMP RωC
1
(mod)m
OUTCVM G
CA
im R
DG
(mod)• Choose a value for RFBT based on bias current and power dissipation
• Find the modulator transconductance in A/V
• Find the RHPZ frequency at minimum input voltage and maximum load current
• Set the target bandwidth to 1/4 of the RHPZ frequency:ωC = 2·π·fC = ωR/4
• Find the mid-band gain AVM to achieve target bandwidth
• Set ωZEA equal to 1/10 the target crossover frequency:ωZEA = ωC/10
• Set ωHF equal to the lower of the RHP or ESR zero frequency:ωHF = ωR or ωZ
DLDROUT
R
2
(op amp)
(gm amp)
3-44
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop
Error amplifier
Power stage
Current-mode buck-boost compensation results
LP
ZRVC
C
OUT
ss
ss
Avv
11
11
ˆˆ
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
OUT
C
C
OUT
OUT
OUT
vv
vv
vv
ˆˆ
ˆˆ
ˆˆ
-180-135-90-45045
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
4590135180225270
-60-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
-90-4504590135
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
VCA
2C
2P
2Z
2ZEA
VMA
2HF
2R
2L
3-45
Texas Instruments – 2016/17 Power Supply Design Seminar
Isolated compensation techniquesSimplest method: Optocoupler with shunt regulator
• CTR – Current transfer ratio
• CP – Includes optoparasitic capacitance. This creates a pole with gain setting resistor RP
• RD – Connected to VOUTcreates a feedback path even when CCOMP rolls off the gain
• TL431 – Cathode cannot pull lower than the reference voltage
PP
FBTCOMP
D
P
OUT
C
RCsRCs
RRCTR
vv
1
11
ˆˆ
3-46
Texas Instruments – 2016/17 Power Supply Design Seminar
Primary side compensation
-+
VCC
VREF
VC
RE
RI
RF
• Uses primary side inverting amplifier to implement frequency compensation
• Opto emitter is at virtual ground of VREF• This minimizes pole due to opto
parasitic capacitance
Primary side compensation High bandwidth configuration
3-47
Texas Instruments – 2016/17 Power Supply Design Seminar
Secondary side compensation
• An RC pole to the opto can be used to cancel the output capacitor ESR zero
• Feed-forward across RD adds phase boost for increased bandwidth
• Zener bias for RD eliminates the high frequency feedback path for secondary-side compensation
Zener biasPhase boostESR zero compensation
TL431
CFF
CCOMP
RFF
RFBT
RFBB
RD
V′OUT
TL431
ZS
CCOMP
CHF
RCOMP
RFBT
RFBB
V′OUTRSRD
CCOMP
TL431
CS
RFBT
RFBB
V′OUTRSRD
3-48
Texas Instruments – 2016/17 Power Supply Design Seminar
+
Isolated current-mode forward
Output filter
Error amplifier
Modulator
S
P
IN
OUT
NN
VVD
IN
S
POUTIN
VNNVV
D
3-49
Texas Instruments – 2016/17 Power Supply Design Seminar
Current-mode forward compensation strategy
(mod)m
OUTCVM G
CA
S
P
im N
NR
G 1(mod)
• Choose a value for RFBT based on bias current and power dissipation
• Find the modulator transconductance in A/V• Pick target bandwidth, typically fSW/10:
ωC = 2·π·fC• Find the mid-band gain AVM to achieve target bandwidth
Adjust RD, RP and COUT as required• Set ωZEA equal to 1/10 the target crossover frequency:
ωZEA = ωC/10• Set ωHF equal to the ESR zero frequency:
ωHF = ωZ
VMAP
DRCTRR
ZEAFBTCOMP RC
1
HFSS RC
1
3-50
Texas Instruments – 2016/17 Power Supply Design Seminar
Control loop
Error amplifier
Power stage
Current-mode forward compensation results
LP
ZVC
C
OUT
ss
s
Avv
11
1
ˆˆ
HF
ZEA
VMOUT
C
ssA
vv
1
1
ˆˆ
OUT
C
C
OUT
OUT
OUT
vv
vv
vv
ˆˆ
ˆˆ
ˆˆ
-90-4504590
-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
4590135180225
-40-20
02040
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
-90-4504590135
-40-20
0204060
10 100 1,000 10,000 100,000 1,000,000
PHA
SE (°
)
MA
GN
ITU
DE
(dB
)
VCA
2C
2P
2Z
2ZEA
VMA 2HF
2L
3-51
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