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ECE 322 Digital Design with VHDL
Lecture 17
Synchronous SequentialCircuits
California State University
Textbook References
n Synchronous Sequential Circuits Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd or 3rd Edition–Chapter 8, Synchronous Sequential Circuits– Sections 8.7 Design of a Counter Using the Sequential CircuitApproach
California State University
Design of a Counter Using the Sequential Approach
California State University
Example: Modulo-8 Counter
Design of a Modulo-8 Counter Using the Sequential Approach w 0=
w 1=
w 0=
w 1=
w 0=
w 1=
w 0=
w 1=
w 0=
w 1=
w 0=
w 1=
w 0=
w 1=
w 0=
w 1=
A/0 B/1 C/2 D/3
E/4F/5G/6H/7
State diagram for the counter
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Example: Modulo-8 Counter
State table for the Moore-type sequential circuit
State table for the counter
Present Next state Outputstate w = 0 w = 1
A A B 0 B B C 1 C C D 2 D D E 3 E E F 4 F F G 5 G G H 6 H H A 7
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Example: Modulo-8 Counter
State Assignment: Three state variables are needed to represent the eight states.
State-assigned table for the counter
Present Next state
state w = 0 w = 1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 Y 2 Y 1 Y 0
z 2 z 1 z 0
A 000 000 001 000 B 001 001 010 001 C 010 010 011 010 D 011 011 100 011 E 100 100 101 100 F 101 101 110 101 G 110 110 111 110 H 111 111 000 111
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Example: Modulo-8 Counter
Implementation using D-type flip-flops
00 01 11 10
00
01
1
0 1
1
1
0
0
0
0
1 0
0
0
1
1
1 11
10
y 1 y 0 wy2
00 01 11 10
00
01
0
0 0
1
1
1
1
0
1
0 1
0
0
1
1
0 11
10
y 1 y 0 wy2
00 01 11 10
00
01
0
1 1
0
1
0
1
0
1
0 0
0
1
1
0
1 11
10
y 1 y 0 wy2
Y 2 wy2 y 0 y 2 y 1 y 2 w + + + y 0 y 1 y 2 =
Y 0 wy0 wy0 + = Y 1 wy1 y 1 y 0 wy0 y 1 + + =
Karnaugh maps for D flip-flops for the counter
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Example: Modulo-8 Counter
Implementation using D-type flip-flops
D Q
Q
D Q
Q
Clock
y 0
w
y 1
y 2
Y 0
Y 1
Y 2
Resetn
D Q
Q
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Example: Modulo-8 Counter
Implementation using JK-type flip-flops
§ If a FF in state 0 is to remain in state 0 J = 0 and K = d (i.e. K can be either 0 or 1)
§ If a FF in state 0 is to change to state 1 J = 1 and K = d
§ If a FF in state 1 is to remain in state 1 J = d and K = 0
§ If a FF in state 1 is to change to state 0 J = d and K = 1
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Example: Modulo-8 Counter
Implementation using JK-type flip-flops
Present Flip-flop inputs
state w = 0 w = 1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0
z 2 z 1 z 0
A 000 000 0d 0d 0d 001 0d 0d 1d 000 B 001 001 0d 0d d0 010 0d 1d d1 001 C 010 010 0d d0 0d 011 0d d0 1d 010 D 011 011 0d d0 d0 100 1d d1 d1 011 E 100 100 d0 0d 0d 101 d0 0d 1d 100 F 101 101 d0 0d d0 110 d0 1d d1 101 G 110 110 d0 d0 0d 111 d0 d0 1d 110 H 111 111 d0 d0 d0 000 d1 d1 d1 111
Excitation table for the counter with JK flip-flops
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Example: Modulo-8 Counter
Implementation using JK-type flip-flops
00 01 11 10
00
01
d
0 d
d
d
0
0
0
d
1 d
d
d
1
1
111
10
y1y0wy2 00 01 11 10
00
01
0
d 0
0
0
d
d
d
1
d 1
1
1
d
d
d11
10
y1y0wy2
J 0 w= K0 w=
00 01 11 10
00
01
0
0 0
d
d
d
d
0
1
0 1
d
d
d
d
011
10
y1y0wy2
J 1 wy0=
00 01 11 10
00
01
d
d d
0
0
0
0
d
d
d d
1
1
0
0
d11
10
y1 y0wy2
K1 wy0=
00 01 11 10
00
01
0
d d
0
d
0
d
0
d
0 0
d
1
d
0
d11
10
y1y0wy2 00 01 11 10
00
01
d
0 0
d
0
d
0
d
0
d d
1
d
0
d
011
10
y1y0wy2
J 2 wy0y1= K2 wy0y1=
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Example: Modulo-8 Counter
Implementation using JK-type flip-flops
Clock Resetn
w J Q
Q K
y 0
y 1
y 2
J Q
Q K
J Q
Q K
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Example: Modulo-8 Counter
Factored-form implementation of the counter using JK-type flip-flops
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Reverse of synthesis process Outputs of the FFs
•represent the present state variables •Inputs of FFs represent the next state variables •Construct a state-assigned table •This leads to the state table and state diagram
Analysis of Synchronous Sequential Circuits
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Example:
D Q
Q
D Q
Q
Clock
Resetn
y 2
y 1
Y 2
Y 1
w
z
𝑌1 = 𝑤𝑦&1 + 𝑤𝑦2 𝑌2 = 𝑤𝑦1 + 𝑤𝑦2
𝑧 = 𝑦1𝑦2
Analysis of Synchronous Sequential Circuits
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• From these tables it can be seen that the out z is one, only when the FSM is at state D=’11’ when input is ‘1’.
• Therefore, the circuit is a sequence detectors that detect a three consecutive one.
Present Next State
state w = 0 w = 1
Outputy 2 y 1
Y 2 Y 1 Y 2 Y 1 z
0 0 0 0 01 0 0 1 0 0 10 0 1 0 0 0 11 0 1 1 0 0 11 1
(a) State-assigned table
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A D 0 D A D 1
(b) State table
Analysis of Synchronous Sequential Circuits
