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SYNCHRO/RESOLVERCONVERSIONHANDBOOK
105 Wilbur Place, Bohemia, New York 11716-2426
For Technical Support - 1-800-DDC-5757 ext. 7771
Headquarters - Tel: (631) 567-5600, Fax: (631) 567-7358
United Kingdom - Tel: +44-(0) 1635-811140, Fax: +44-(0) 1635-32264
France - Tel: +33-(0) 1-41-16-3424, Fax: +33-(0) 1-41-16-3425
Germany - Tel: +49-(0) 8141-349-087, Fax: +49-(0) 8141-349-089
Japan - Tel: +81-(0) 3-3814-7688, Fax: +81-(0) 3-3814-7689
World Wide Web - http://www.ddc-web.com
FOURTH EDITION
UPDATED 03/2009
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The Synchro/Resolver Conversion Handbook is designed as a practical reference source. It discusses thetheory of operation of data converter products (synchro, resolver, and linear variable differential transformer[LVDT]), performance parameters, and design factors for typical applications. The subject matter and appli-cations are chosen to be those of greatest interest and concern for the designers, systems engineers, andsystems operators with whom DDC has worked over the years. The text treats both DDC’s own approach toshaft encoding and other generally accepted techniques. Because various points of view are presented, theHandbook has served well as a teaching aid over the years.
Our first Synchro Conversion Handbook was conceived in 1973 during a series of technical seminars con-ducted at DDC. It was the first integrated reference source on synchro/resolver data converters.
Now after 30 plus years, this hardcopy book is released as an electronic file.
Since 1968 DDC has been the leader in new product development in the field of synchro/resolver convert-ers. DDC’s introduction, in 1968, of the first modular synchro converters (in a 0.8 x 2.6 x 3.1 inch package)instantly made the existing rack, box, and card-set converters obsolete. Indeed, the biggest sales problemwas convincing engineers that they were able to design complete synchro/resolver systems using only a fewsmall DDC hybrids. Shortly thereafter, hybrid technology matured and we were able to once again make adramatic size reduction - down to single DIP packages. Now, with the advent of custom monolithic technolo-gy, we are making major advances in functionality and cost (size is more and more being determined by pincount requirements). Today, as in 1968, DDC is still committed to being the leader in synchro conversionand related test equipment. We intend to do this by offering superior products that meet the needs of theengineering community and supporting those products with the best application support world-wide in thisfield.
PREFACE
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TABLE OF CONTENTS
SECTION I - FundamentalsAngle-Sensing Transducers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Reliability and Functional Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Attainable Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Static and Dynamic Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Environmental Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Angle-Data Conversion Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Fundamental Mathematical Relationships in Synchro/Resolver Equipment . . . . . . . . . . . . . . . . . . . . . .4
Synchro Control Transmitter (Figure 1.10a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Synchro Control Transformer (Figure 1.10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Control Differential Transmitter (Figure 1.10c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Resolver (Figure 1.10d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Transolver (Figure 1.10e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6The Scott-T Transformer (Figure 1.10f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Torque Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Typical Synchro/Resolver System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Single-Speed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Multispeed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stick-off Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Digital Data Conversion Techniques for Synchro/Resolver Systems . . . . . . . . . . . . . . . . . . . . . . . . . .15
Single-RD Phase-Shift Synchro-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Double-RD Phase-Shift Synchro-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Real-Time Trigonometric Function - Generator Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Demodulation, A/D, and µP Approach to Synchro/Resolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
SECTION II - Theory of Operation of Modern Synchro-to-Digital Converters . . . . . . . . . . . . . . . . . . .19The Tracking Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Use of a "Synthesized" Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Sampling A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Successive-Approximation Sampling Synchro-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . .27The Sampling Harmonic Oscillator Synchro-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . .29Multiplexing Synchro-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Synchro- or Resolver-To-Digital Converters for Two-Speed Systems . . . . . . . . . . . . . . . . . . . . . . . . . .33Testing S/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Single Channel S/D or R/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Multiplexed S/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Dynamic Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
SECTION III - Theory of Operation of Synchro-to-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Theory of Operation of Synchro- or Resolver-to-Linear DC Converters . . . . . . . . . . . . . . . . . . . . . . . .39Synchro/Resolver-to-Nonvariant DC Sine/Cosine Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
SECTION IV - Theory of Operation of Modern RVDT/LVDT-to-Digital Converters . . . . . . . . . . . . . . . .45RVDT/LVDT Rotary and Linear Variable Differential Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . .45RVDT/LVDT-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
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Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SECTION V - Theory of Operation of Modern Digital-to-Synchro Converters . . . . . . . . . . . . . . . . . . .49The Programmed-Function Generator Digital-to-Synchro Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .49Types of Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50The Stored-Table-Lookup Digital-to-Synchro Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52Output Circuits for D/S and D/R Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Power Surge at Turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Torque Load Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Pulsating Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Passive Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Pulsating Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Active Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57Feedback Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Tuning the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58Computing Value of Capacitor for Tuning Synchro Stator Windings . . . . . . . . . . . . . . . . . . . . . . . .58
Testing D/S Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59How to Calculate Power Requirements for D/S Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Control Transformers and Torque Receiver Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62Digital-to-Synchro/Resolver Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
SECTION VI - Other Functions and Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63Solid-State Control Transformer (SSCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63Electronic Control Differential Transmitter (ECDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Isolation and Format-Conversion Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65Signal Booster Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65Driving Torque Receiver Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67Reference Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67Power-Output Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
SECTION VII - Measuring and Computing Performance Parameters of Synchro/Digital andSynchro/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Worst-Case Error Analysis of Typical S/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69Velocity and Acceleration Errors in Type I and Type II Servos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Type I Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71Type II Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
The Relationship between Bandwidth, Tracking Rate and Settling Time for Synchro/Resolver-to-DigitalConversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
RDC-19220 Series Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72RDC-19220 Series Maximum Tracking Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Determining Acceleration Lag and Large Step Response Settling Time . . . . . . . . . . . . . . . . . . . . . . . .74Speed-Voltage Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76Resolution, Linearity, Monotonicity, and Absolute Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
TABLE OF CONTENTS - (CONTINUED)
Static errors and Instabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79Maximum Tracking Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80“Skew” in Sampled Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Quantization Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Jitter Due to Hunting in Tracking Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81LOS Circuit to Detect Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81BIT Logic to Detect Malfunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Harmonic Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82Quadrature Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82Amplitude Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
SECTION VIII - Measuring and Computing Performance Parameters of Digital-to-Synchro Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Worst-Case Error Analysis of Typical D/S Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85External Influences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85Interface Influences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85Internal Influences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Static Accuracy (Network) Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85Effects of Settling Time and Maximum Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86Loading Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87Amplifier Mismatch Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88Static Errors and Instabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
SECTION IX - Typical Applications and Interface Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . .89Parametric Tradeoffs vs. Price . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89Typical Interface Circuits (Input and Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89Trimming and System Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94Synchro Zeroing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
SECTION X - PC-Based Synchro/Resolver Test Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95PC-Based Test Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
SECTION XI - Application Tips and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97Example #1: Coordinate Transformation (Polar to Rectangular) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97Example #2: Using an S/D in the CT Mode in a Servo System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97Example #3: Using the Velocity (VEL) Output to Stabilize a Position Loop . . . . . . . . . . . . . . . . . . . . . .98Example #4: Interfacing an S/D or R/D with an IBM PC/AT/XT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98Example #5: Using BIT to Speed Up Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Example #6: Using Major Carry (MC) and Direction (U) in Multiturn Applications . . . . . . . . . . . . . . .102Example #7: An On-Line Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102Example #8: Boosting the Output of D/S and D/R Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103Example #9: Synchronizing Two Rotating Shafts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104Example #10: Using and S/D with an Inductosyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105Example #11: A 7VA Power Amplifier for Driving Synchros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106Example #12: A Solid-State Scott-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106Example #13: Replacing and Incremental Encoder with a Synchro or Resolver . . . . . . . . . . . . . . . .109
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TABLE OF CONTENTS - (CONTINUED)
viii
Example #14: A Binary Two-Speed Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109Example #15: Single Axis Servo Interfacing to a Motorola 6809 µP . . . . . . . . . . . . . . . . . . . . . . . . . .110Example #16: Interfacing a Motorola 6809 µP to a Multiturn Positioning Servo . . . . . . . . . . . . . . . . .113
TABLE OF CONTENTS - (CONTINUED)
1
FUNDAMENTALS
SECTION I
Angle-Sensing Transducers
The measurement of shaft angle is one of the mostprevalent requirements in the modern control, instru-mentation, and computing technologies. Almostevery machine, process, and monitoring system hasa rotating shaft somewhere in its mechanism...or canbe so equipped. Mechanisms for converting shaftrotation to translation (linear motion) further extendthe usefulness of shaft-angle sensing.
Shaft angle is used in the measurement and controlof position, velocity, and acceleration, in one, two, orthree spatial dimensions; and, in many systems,many different sets of these parameters must besensed and/or controlled. Thus, shaft-angle trans-ducers are extremely important elements in modernengineering.
Over the years, many different forms of shaft-angletransducers have been developed. Among them, thefollowing are worth consideration:
Potentiometers (single or multiturn - see Figure 1.1)
Brush encoders (see Figure 1.2)
Optical encoders (see Figure 1.3)
Synchros (see Figure 1.4)
Resolvers (see Figure 1.5)
Rotary Variable Differential Transformers (RVDTs)/Linear Variable Differential Transformers (LVDTs) (see Figure 1.6)
Let us now compare these types of transducers withrespect to the most important design parameters.
Reliability and Functional Stability
The probability of catastrophic failure, and the prob-ability of failure to meet specifications are related
SHAFT
B0
B1
B2
B3
PIERCED CODED DISC
PHOTODETECTORLIGHT SOURCE
"N"LIGHTSOURCES
"N"PHOTODETECTOR
Figure 1.1. Potentiometers.
Figure 1.2. Brush Encoder.B0, B1, B2, B3, show brush positions.
Figure 1.3. Optical Shaft Encoder.In this type of encoder, the disk is pierced with a
pattern analogous to the disk shown in Figure 1.2.
FUNDAMENTALS
parameters. In most applications, either kind of fail-ure is intolerable. In both respects, synchro, resolverand RVDT/LVDT sensors are unchallenged. They donot depend on moving electrical contacts for signalintegrity (e.g., brushes)*; they do not exhibit appre-ciable aging or wear. They do not drift with time, andeven extreme temperature changes have negligibleeffect on their performance. Next in order of reliabil-ity, but significantly less dependable are opticalencoders, which exhibit significant temperaturedependence, and appreciable vulnerability to elec-tromagnetic and electrostatic fields. Following them,in decreasing order of reliability, are the moving-con-tact devices: potentiometers and brush transducers.
Cost
In comparing costs, it is necessary to include theassociated electronics required to produce data inthe form acceptable for modern control and monitor-ing systems - digital data. Thus potentiometers,which are analog components, must be excited by awell-regulated reference voltage, and their outputsignals must be digitized. Similar circuit implemen-tation must be provided for all of the types of trans-ducers under consideration, with the brush encodertype requiring the least. The costs can only bemeaningfully compared at a given level of resolution(e.g., at 0.01% of 360° full scale), but assuming rela-tively high precision, the order of decreasing cost is:optical encoder; synchro/resolver; RVDT/LVDT;potentiometer; and brush encoder.
Attainable Performance
The resolution capability, absolute accuracy, long-term reliability, temperature stability, and dynamicresponse characteristics of these devices vary fromtype to type. It is generally accepted that both thesynchro/resolver and optical types are capable ofequal state-of-the-art performance (10-50 PPM totaluncertainty), under optimum conditions. Though thebrush encoder can theoretically attain equivalentperformance, its useful operating life, at very highresolutions, is severely limited by noise and position-
2
Figure 1.6. RVDT/LVDT.
Figure 1.5. Resolver.
SINEOUTPUT
COSINEOUTPUT
TWO WINDINGSON ROTOR
REF. INPUT
STATOR
ROTORANGLE
ROTORANGLE
SINEOUTPUT
COSINEOUTPUT
COIL
CORE
LVDT
RVDT
*Synchro and Resolver brushes ride on slip rings, not segmented surfaces; furthermore, contact resistance changes do not introducesignificant data errors.
Figure 1.4. Synchro.
STATOR
ROTOR
FUNDAMENTALS
al uncertainty, due to brush wear, and dimensionaluncertainty under normal vibration stress.Potentiometers (including the so-called “infinite reso-lution” film types) are even more severely limited bywear and other mechanical and electrical noiseuncertainties. RVDTs and LVDTs, because of theirunique properties, occupy a niche all to themselvesand do not really compete with the other transducers.Many LVDTs have virtually no friction, excellent nullstability and operate in both extremes of the temper-ature spectrum.
Static and Dynamic Mechanical Loading
All shaft angle transducers, except the LVDT, presentsome small amount of static and dynamic friction tothe shaft measured. In the case of the RVDT, syn-chro/resolver, and optical-sensor types, the friction isusually negligible - particularly since high-qualitybearings are used. Another dynamic loading ele-ment to consider is the moment of inertia added tothe shaft. In this respect, miniature synchro/resolverand RVDT/LVDT designs are ideal. They are superi-or to the large diameter encoders required for highresolution. The static and dynamic loading present-ed by both potentiometers and brush sensors aresignificantly higher than those presented by eithersynchro/resolvers, RVDT/LVDTs or optical encoders.
Environmental Sensitivity
Environmental considerations include: temperature,humidity, vibration, shock, and power supply varia-tions. Under extreme environmental conditions thesynchro/resolver or RVDT/LVDT with solid-stateelectronics is the most dependable and stable of allshaft-angle instrumentation configurations. Theother types perform in the descending order of merit:optical-sensor; potentiometer; brush-sensor. TheRVDT/LVDTs in particular have excellent null stabili-ty and can be constructed to operate in very extremeenvironments.
Angle-Data Conversion Devices
All of the transducers considered above require exci-tation by AC or DC analog reference signals. Thedisc encoders produce parallel digital outputs at alltimes (although monotonicity1 tends to be poor atmajor-carry transitions from quadrant to quadrant),but require signal conditioning electronics: filtering,common-mode rejection2 to preserve accuracydespite ground-loops and induced low-frequencynoise, and buffer amplification. Synchronous clock-ing and parallel-serial conversion may also berequired. Figure 1.7 shows typical interface electron-ics between a disc encoder and a computer data link.
3
Figure 1.7. Typical Interface (simplified) between Disk Encoder and Computer.
FILTER
FILTER
FILTER
DELAY
LATCH
SAMPLINGLOGIC
STROBE
REGISTER
RESET
CLOCK
COMPUTERI/O BUS
COMMON
Bn1
B1
B0 BUFFER
BUFFER
BUFFER
1. See Section VII for definitions and discussions of these error factors.2. See Section IX for definitions and discussions of these error factors.
FUNDAMENTALS
4
The analog-output devices - potentiometers, syn-chros, and resolvers - require reference excitation(always AC for the synchros, resolvers, andRVDT/LVDTs), and analog-to-digital conversion.Potentiometers also require the same amount of sig-nal conditioning electronics as do the disc encoders.In rare instances, synchros and resolvers do notrequire signal conditioning, because they are lowimpedance devices, self-isolated from ground-loopinduced noise, and capable of driving the S/D or R/Dconverter directly, as shown in Figure 1.8.RVDT/LVDTs, although similar to a resolver, requirea few additional parts to match the transducer outputto the converter. An example is shown in Figure 1.9.
When considering performance, reliability, cost andapplication convenience, the synchro/resolver con-verter combination of Figure 1.8 is the logical choicefor angle-data measurement.
The remainder of this handbook is devoted to the elec-tronic circuits used to convert and process shaft-angledata developed by synchros and resolvers. There is aseparate chapter describing RVDT/LVDTs and theirconverters as a specialized version of an R/D. Thedevices considered will include both synchro/resolver-to-digital and digital-to-synchro/resolver types.
Fundamental Mathematical Relationships inSynchro/Resolver Equipment
Before proceeding to study converter design, it willbe necessary to review the nature of the signals pro-duced by, or accepted by, synchro and resolver com-ponents. First, let us list the most common types ofsynchro and resolver components, each of which isillustrated in Figure 1.10.
• Synchro Control Transmitter (Figure 1.10a)Accepts AC reference excitation at rotor terminals(R1 and R2), and develops, at its stator terminals(S1, S2, and S3), a 3-wire AC output at the refer-ence (or “carrier”) frequency. The amplitude ratiosof the line-to-line voltages of this 3-wire output rep-resent an explicit mathematical relationship to theangular position of the shaft (θ degrees), withrespect to some reference shaft position, called
Figure 1.8. Synchros and Resolvers generally donot require signal conditioning.
Figure 1.9. RVDT/LVDT Interconnect to Converter.
Figure 1.10a. Symbol for Control Transmitters andReceivers.
COMPUTERI/O BUS
S/DCONVERTER
DTC-193000
PHASECOMP
FULLSCALE
R2
C2
R510k
10kR1
SJ
TO V(PIN 25)
SO
SG
S
R
V
RO
RIC1
OSC
RF1
RF2
FREQR4
29
35
34
33
32
25
31
36
19
21
22
20
24e
23A
18BIT
RMAMPL
R3TO V(PIN 25)
LVDT
+
DATA
S1
S2
S3
V1-2
V2-3V1-3
SHAFT INPUT θ
ROTOR IS PRIMARY
R1
R2
FUNDAMENTALS
5
zero degrees of rotation. In synchro language, acontrol transmitter is called a “CX.”
• Synchro Control Transformer (Figure 1.10b)Accepts, at its 3-wire stator terminals (S1, S2, andS3), a set of carrier-frequency signals of the typeproduced by a synchro control transmitter (or CX),corresponding electrically to some shaft angle θ. Itproduces, at its rotor terminals (R1 and R2), a carrier-frequency signal proportional to the sineof the angular difference between the electricalinput angle, θ, and the mechanical angular posi-tion of its shaft, φ ... in other words, the voltageinduced into the rotor is proportional to sin (θ - φ),where φ is measured from some reference shaft position, called zero degrees of rotation.The synchro shorthand for this component is “CT.”
• Control Differential Transmitter (Figure 1.10c)Accepts, at its 3-wire stator terminals, a set of carrier-frequency signals of the type produced bya CX, the line-to-line amplitude ratios of which(S1, S2, and S3) correspond to some (remote)shaft angle θ. Produces, at its 3 rotor terminals(R1, R2, and R3), a 3-wire set of carrier-frequen-cy signals whose line-to-line amplitude ratios represent the difference between the input angle θ and the mechanical angular position of itsshaft ... in other words, the line-to-line voltageratios induced into the rotor represent the angle (θ- φ), where φ is measured from some referenceshaft position, called zero degrees rotation. Insynchro language, the symbol for this componentis “CDX.”
• Resolver (Figure 1.10d)Accepts at its 2-wire rotor terminals (R1 and R2),an AC reference excitation and produces, ata pair of 2-wire output terminals (connected to iso-lated stator windings, a pair of voltages that are atthe carrier frequency, and with amplitudes that areproportional, respectively, to the sine (S1 and S3)and cosine (S2 and S4) of the angular position ofthe shaft ... in other words, the voltages inducedinto the stator winding will be K sinθ sinω(t) and Kcosθ sinω(t), where K is the transformation ratio,θ is the shaft rotation from some reference zero-
Figure 1.10b. Symbol for Control Transformer.
Figure 1.10d. Symbol for Resolver.
Figure 1.10c. Symbol for Differential Transmittersand Differential Receivers.
S1
S2
S3
SHAFT INPUT φ
STATOR IS PRIMARY
R1
R2θ SIN (θ − φ)
SHAFT INPUT φ
STATOR IS PRIMARY
R1
R2
R3
S1
S2
S3
θ
SHAFT INPUT θ
EITHER ROTOR OR STATORMAY BE THE PRIMARY S2
S1
S3
S4
R1
R2
Cos θ
Sin θ
FUNDAMENTALS
6
degree position, and ω = 2πf carrier frequency.The symbol for this component is “RS.”
• Transolver (Figure 1.10e)A bidirectional device (i.e., either rotor or statormay be used as input) in which the rotor windingsare in 3-wire synchro format (R1, R2, R3) butwhose stator windings are in 4-wire resolver for-mat (S1, S2, S3, S4). It can convert signals fromsynchro to resolver format, can be used as a CT(ignoring one stator winding) or as a CX (ignoringthe other stator winding). By rotating the shaft, thedevice can rotate the reference axis (i.e., add to orsubtract from) of the angle that is being convertedfrom synchro to resolver (or resolver to synchro)format. The symbol for this component is “TY.”
• The Scott-T Transformer (Figure 1.10f)Although this is not a rotary device, but merely twointerconnected static transformers, it is included inthis list of synchro/resolver components because itperforms the same function as a transolver set atzero shaft position. It will transform signals fromsynchro to resolver format, or vice versa. A solidstate equivalent of the Scott-T transformer can beimplemented as shown in Figure 1.10g. It is com-monly used in hybrid synchro converters as eitherthe input or output stage.
Torque Components
Although torque elements are not, strictly speaking,transducers, they are used in some control systemsto move indicators, position other synchros (e.g.,
Transmitters
Transolvers
Resolvers
Torque Receiver Transmitters
Torque Differential Receivers
Control Transformers
Torque Receivers
Differential Transmitters
UNIT FUNCTION
TX
—
—
TRX
TDR
—
TR
TDX
TORQUE
CX
TY
RS
—
—
CT
—
CDX
CONTROL
Table 1.1Torque and Control Components
SHAFT INPUT θ
EITHER ROTOR OR STATOR MAY BE THE PRIMARY
S4
S1
S2
S3
R1
R2
R3
Figure 1.10e. Symbol for Transolver.
SYNCHRO RESOLVER
1:1
S4
S1
S3
S3
S2
SIN θ
COS θ
S1 S2
Figure 1.10f. Scott-T Transformer.
S1
S3
S2
_
+ SIN
+ COS
+
+
_
WHERE: SIN ~ S3 - S1
COS ~ S2 - ( ) S1 + S32
23
Figure 1.10g. Solid-State Scott-T Transformer.
FUNDAMENTALS
7
where the constants K1, K2, K3 are ideally equal, butdiffer slightly in practice, and represent the rotor-sta-tor transfer functions;
α1, α2, and α3, are ideally zero (or small and equal),but are appreciable in practice, and represent therotor-stator time-phase shift at the carrier frequency;
and ω = 2πf, where f is the carrier (or reference) fre-quency used to excite the system.
With these variables accounted for the basic synchrosignal relationship is a shown in Figure 1.11a.
Similarly, a 4-wire set of resolver signals (see Figure1.10d) measured at terminals S1 and S3 (Vx), S2and S4 (Vy), and corresponding to the spacial phaseangle θ, would be represented mathematically by:
where Kx and Ky are ideally equal transfer-functionconstants like K1, K2, and K3;
αx and αy are ideally zero time-phase shifts, like α1,α2, and α3;
and ω = 2πf where f is the same as in the synchroequations.
V = K sinθ sin (ωt + α )
V = K sin (θ + 120°) sin (ωt + α )
1
2
1
23-2
3-1
30 90 150 210 270 330
360
θ (DEGREES) CCW
0
S4-S2 = V COS(θ) MAX
S3-S1 = V SIN(θ) MAX
- V MAX
+ V MAX
In Phase with RH-RL
Out of Phase with RH-RL
Figure 1.11b. Resolver Signal Relationships.
“repeaters”), or perform other low-energy mechani-cal work. Table 1-1 relates torque components to theanalogous control components described above.
The most important fact about all synchro andresolver signals is that they present informationabout the angular position of a shaft in the form ofrelative amplitudes of a carrier wave. All signals, rotorand stator, input and output, are at the same fre-quency, and (except for imperfections in the compo-nents) in perfect time-phase synchronization.Although it is common to speak of the “phase angle”of the shaft, and of the winding as a “3-phase” (syn-chro) or “2-phase” (resolver), all carrier signals aresine waves, in phase with all others in the system...except for the imperfections and undesired side-effects to be discussed later. To differentiatebetween time-phase angle and shaft-position angles(or their electrical equivalents), we refer to the latteras “spatial-phase” angles.
A 3-wire set of synchro signals (see Figure 1.10a),measured between pairs of terminals, S1, S2 andS3, corresponding to the spacial phase angle, wouldbe represented mathematically as:
V = K sinθ sin (ωt + α )
V = K sin (θ + 120°) sin (ωt + α )
V = K sin (θ - 120°) sin (ωt + α )
1
2
3
1
2
3
3-2
3-1
1-2
30 90 150 210 270 330
360
θ (DEGREES) CCW
0
S3-S1 = V SIN(θ) MAX
S3-S2 = V SIN(θ + 120°) MAX
S1-S2 = V SIN(θ + 240°) MAX
- V MAX
+ V MAX
Out of Phase with RH-RL
In Phase with RH-RL
Figure 1.11a. Synchro Signal Relationships.
Standard Synchro Control Transmitter (CX) Outputs as a Function ofCCW Rotation From Electrical Zero (EZ).
Standard Resolver Control Transmitter (RX) Outputs as a Function ofCCW Rotation From Electrical Zero (EZ).
FUNDAMENTALS
8
That is, regardless of dθ/dt, the rotational velocity ofthe shaft, or even of d2θ/dt2, the angular acceleration,the value of θ is always given by:
However, there is an undesired effect in synchros andresolvers called “speed voltage,” which can causeappreciable deviations from the ideal relationship stat-ed above. Speed voltage is discussed in Section VII.
Speed voltage is only one of several undesirableeffects that cause synchro and resolver behavior todepart from the ideal relationships discussed above.Among the others are: harmonic distortion; quadra-ture components (of output voltage); loading (of or bythe synchro or resolver); time-phase shift in the syn-chro or resolver (the parameter α, mentioned above);and nonlinearities in the synchro or resolver - i.e.,departures, due to mechanical imperfections in themagnetic or windings that cause departure from theideal transfer functions described above. All of theseare discussed in some detail in Section VII.
As a final item in our discussion of useful mathematicalrelationships, let us examine the nature of digital sig-nals. A digital signal consists of a set of voltage levels(or current or resistance levels), at a set of terminals,each of which has been reassigned a certain “weight”(i.e., a certain relative importance), in accordance witha certain “code”. The most common code is the socalled “natural binary” code, in which the weight ofeach successive voltage-level terminal, from the small-est to the largest, is given by the simple relationship:
where n is the number of terminals, which variesfrom 1 to N (the maximum number of terminals). Ina digital signal, the voltage level at each terminalmay have either one of only two values, nominally:
The ONE state (for example, +4 Volts)
The ZERO state (for example, 0 Volts)
weight = 2n-1
θ = tan VxVy
-1
With these variables accounted for the basic resolversignal relationship is a shown in Figure 1.11b.
Thus, for any static spatial angle θ, the outputs of a syn-chro or a resolver are constant-amplitude sine waves atthe carrier frequency. In resolver format, ignoringimperfections, the ratio of the amplitudes would be:
This ratio is independent of the frequency andamplitude of the reference excitation (carrier fre-quency and amplitude).
Similarly, for the same static spatial angle θ, theratios of the amplitudes of the synchro-format sig-nals, ignoring imperfections, would be:
These ratios are independent of the frequencyand amplitude of the reference excitations, as inthe resolver-format case, above.
As we shall see, all data-conversion techniques incurrent use operate on resolver-format (sin/cos) sig-nals, for convenience. This is done by convertingfrom synchro to resolver-format before digitizing oroperating on the signals.
So far, we have spoken only of static shaft angles. Inpractical systems, of course, θ changes, sometimesrapidly, sometimes slowly and sometimes intermit-tently. At all times, however, the instantaneous valueof θ corresponds to the instantaneous ratios of Vx/Vy.
V sin (θ)
V sin (θ + 120°) 3-2
3-1 =
V sin (θ + 120°)
V sin (θ - 120°) 1-2
3-2 =
V sin (θ - 120°)
V sin (θ) 3-1
1-2 =
Note that this set of ratios is a single position, θ,and is the same information as is
contained in Vx/Vyabove.
V sin θ x
V cos θ y= = tan θ
FUNDAMENTALS
9
The examples given are completely arbitrary, theONE and ZERO states may be any two easily distin-guished values. All that matters is that they be dif-ferent enough so that noise, drift, and other circuit orsignal imperfections are not able to create any doubtas to which state exists at a particular terminal.
Each terminal in a set is said to present a “bit” ofinformation, while the entire set, in the pre-assignedsequence, is called a “word.” The 10-bit digital word:
1101000101
would represent voltage values of +4, +4, 0, +4, 0, 0,0, +4, 0, +4 Volts and the conventional way of writingthe word would indicate that the extreme-right-handbit (a one, in this example), would be the least-signif-icant bit (or LSB) - i.e., its weight would be:
with respect to the extreme-left-hand bit (also a ONE in thisexample), which is, by convention, the most-significant-bit(or MSB), the weight of which (relative to the LSB) is:
In other words, a ONE level in the MSB position (i.e.,a +4 V ONE state on the MSB terminal) has 512times as much weight as a ONE in the LSB position.
The actual value of the digital word 1101000101 isfound by adding the ONE bits, in proper weight, andto count the ZERO bits as zero:
(MSB) 1 = 2 = 5129
1 = 2 = 2568
0 = 0 = 000
0 = 0 = 000
1 = 2 = 0646
0 = 0 = 000
0 = 0 = 000
0 = 0 = 000
1 = 2 = 0042
(LSB) 1 = 2 = 0010
837
MSB = 2 = 2 = 512n-1 9
LSB = 2 = 10
Note that the maximum value that can be represent-ed by a 10-bit word is (when all bits are in the ONEstate) is (210 -1) =1,023, or one less than 210. Theresolution to which the digital word can be variedthen is ±LSB, which is:
But the digital word need not be interpreted in termsof an LSB=1. In the case of angle data, for example,we might set the maximum value of an N-bit wordequal to 360°, so that
but this would, for most values of N, give us ratherinconvenient values for each bit. A more appropriatescheme is to set the MSB=180°. Then the bits wouldhave values in descending order, of:
In this scheme, then, a 10-bit digital word in naturalbinary code would have a resolution of:
Note also that the first two bits of any natural-binary-coded digital word scaled in the manner describedabove determine the quadrant in which the angle lies(see pages 49 and 50 for a detailed explanation).
± 1LSB = ≅ 0.35˚ 360˚1024
(MSB) 2 = 180˚N - 1
2 = 90˚N - 2
2 = 45˚N - 3
(LSB) 2 = ( )˚0 180˚N - 12
...
n = N
n = 1Σ = (2 + 1) = 360˚N - 1
Resolution = 1
2n
FUNDAMENTALS
10
Typical Synchro/Resolver System Architecture
Synchro and resolver components can be intercon-nected and combined (mechanically and electrically)with other devices and circuits in hundreds - perhapsthousands - of useful configurations. A number ofthese combinations are shown in Section IX of thishandbook, but, before considering them it would bebest to review a “pre-digital” use of synchros in theall-analog configurations in which these componentswere originally used.
Single-Speed System
Figure 1.12a shows what might be called the “clas-sic” combination of synchro components into anelectro-mechanical follow-up mechanism. The inputangle (θ1) is established by the position command -a setting of the shaft position of the control transmit-ter, CX, by hand or by some director mechanism -and the position of the mechanical load (e.g., a valve,a turntable, a tool-bit feed screw) is made to conformto this command, rapidly and accurately. Thesequence of events is as follows:
(1) The CX puts out a 3-wire representation of θ1,the position command.
(2) The CT transforms θ2 into a 2-wire signal pro-portional to the sine of (θ1 - θ2).
(3) The output of the CT is amplified and used todrive the servo motor.
(4) The servo motor positions the load, through thegear train, which simultaneously drives the shaft ofthe CT.
(5) When the load has reached the correct (com-manded) position, θ1 = θ2, the output of the CT isthen zero, and the motor stops.
The above will be recognized as a vastly oversimpli-fied description, but it should serve to identify thefunction of each element in the follow-up servo.
With the advent of digital electronics, it became pos-sible to replace one or more of the synchro (orresolver) components in such a system by an accu-rate, small, reliable, and economical electronic cir-cuit. In the system of Figure 1.12a, for example, thecontrol transmitter could be replaced by a digital-to-synchro converter, as shown in Figure 1.12b, whichwould accept digital commands, from a programmingdevice - such as a computer, or a punched papertape, or a “Read-Only Memory” (ROM) - and producethe input to the CT. Such a combination is called a“hybrid” synchro system, because it combineselectromechanical and electronic devices for angulardata conversion.
In all the systems shown so far, only one or twoangles are involved in the data manipulation andcontrol. In many applications, as we shall see, manyangles may be measured, monitored, or controlled;therefore, the systems shown are relatively simple(although very important) examples.
CONTROLTRANSFORMER
CT
CONTROLTRANSMITTER
CX SERVOMOTOR
M
θ1 θ 2
MECH LOAD
GEAR TRAIN
VR
Figure 1.12a. Typical Electromechanical Follow-upServo.
SOLID-STATECONTROL
TRANSMITTER CONTROLTRANSFORMER
CT AMPLSERVOMOTOR
M
θ1
DIGITALθIN
MECH LOAD
θ 2
D/S
Figure 1.12b. Follow-up Servo with D/S converterreplacing CX of Figure 1.12a.
FUNDAMENTALS
11
In all of the synchro systems shown and discussedso far, the relationship between θ (the shaft angle tobe monitored, measured, or controlled) and theangular setting of the synchro or resolver transducerhas been a constant ... usually shown as unity (directcoupling), but possibly geared up or down. In allsuch “single-speed” systems, the product of dynam-ic fidelity and resolution is the figure of merit - i.e.,how fast one may track, measure, convert, and reactto, variations in θ, to an accuracy consistent with howmany bits of resolution.
See Figures 1.13 through 1.16 for examples of othertypes of synchro systems.
Multispeed System
There is a type of synchro/resolver system (shown inFigure 1.17) in which much higher accuracies andresolution may be achieved. This is called a multi-speed system.
A multispeed synchro system consists of two or moresynchros or resolvers geared together, usually with agear ratio of some whole number. The most commonare two-speed systems with ratios of 1:8, 1:16, 1:32,1:36 but other ratios can also be found. To under-stand how these systems achieve high accuracy letus examine a typical two-speed system.
In the single-speed case (see Figure 1.12a) the sys-tem will, essentially, have an accuracy dependentupon the accuracy of the CT (we will assume a per-fect transducer) and the positional resolution of theservo loop. Assume we can position the CT with acertain accuracy, say within ±0.1°. If we now gear thisCT to another with a gear ratio of 1:n (called a“coarse” CT) where the CT we are positioning rotatesn turns for each single turn of the other, then 0.1° ofrotation of the fast CT (called the “fine” CT) will turnthe slow CT (called the “coarse” CT) 0.1÷n, so that aninaccuracy in the fine CT position is effectively divid-ed by the gear ratio (often called the speed ratio).
CX (ANGLE SENSOR)
S1
S2S3
RH
RL
12
DIGITAL DIGITALDISPLAY
183.9˚
θIN
SOLID-STATESYNCHRO/DIGITAL
CONVERTER
M(θOUT)
CONTROLDIFFERENTIALTRANSMITTER
CDX β CT
α θ2
M
MECH LOAD
D/SDIGITALθ
SERVO MOTOR
β = θ − αθ2 = β AT NULL
Figure 1.13. Angle Position Readout.
Figure 1.15. Hybrid Follow-up Servo System withD/S Converter and CDX used to produce output
equal to difference between two angular inputs, onedigital and one analog
MSB
LSB
D/SDIGITALINPUT θ1
ECDX
SOLID-STATEELECTRONIC
CDX
CT
θ3
M
MECH LOAD
DIGITALINPUT θ2
θ3 = θ1 − θ2 AT NULL
Figure 1.14. Hybrid Follow-up Servo System withECDX to add two angular inputs in digital format.
MECHANICALLOAD
M
CXREFERENCEEXCITATION
INPUT
SOLID-STATECONTROL
TRANSFORMER(SSCT)
DIGITALCOMPUTER
θ
θ
Figure 1.16. Hybrid Follow-up Servo System Usedto Interface Computer with Motor-Driven Load.
FUNDAMENTALS
12
we use it to drive a servo to position we can theoret-ically increase our positioning resolution by a factorof n.
Let us examine why. If we have a servo loop whichcan position θ to a point where the null is less thansome value, say 2mV, this will represent some posi-tional resolution, say 0.2° (this figure is determinedby the loop gain of the system). Assume now thatour servo system input is the 1xCT error voltage andwe have driven to a 2 mV null. This means θ and φare still 0.2° apart. If we now switch the servo inputfrom the 1xCT output to the nxCT output, the servowill see a 2n mV voltage and position θ so that thenxCT output is a 2 mV null and:
To implement such a system it is apparent that wemust have a means of determining when to switchfrom the coarse (1x) output to the fine (nx) output.
φ = θ within 0.2˚ ÷ n
Perhaps the easiest way to explain their operation isto examine a basic system as shown in Figure 1.18.Assume θ = φ; that is, assume the control transform-ers (CT) are at the same angle as the transmitters(CX). For convenience let θ = φ = 0 so all synchrosare at 0°. Under these conditions the output of bothCT’s will beat null, there will be no error signal fromeither the one speed (1x) or n speed (nx) CT.
Now assume we change the input shaft position bysome small amount, say 2°, so θ is not equal to φ.The output of the 1xCT is now some value, E1xCTand since the nxCT is geared to it by 1:n the nxCToutput will be n times E1xCT. Since φ still equals 0°the output of the 1xCT can be expressed as:
where A=F.S., and the nxCT output can beexpressed as:
Note: 1x signifies that the coarse CX is connecteddirectly to the shaft being monitored. It has a 1:1relationship with it.
It can be seen then that as an additional bonus theerror gradient at null out of the n speed CT is n timesthe one speed CT gradient (see Figure 1.19) and if
E = A sin (θ - φ ) = A sin (2n˚ - 0˚)1xct
E = A sin 2n˚1xct
nn
E = A sin (θ - φ) = A sin (2˚ - 0˚)1xct
E = A sin 2˚1xct
"COARSE"SYNCHRO
"FINE"SYNCHRO
ANY ARBITRARYRATIO*
SHAFTCOUPLING
TRANSDUCERSTO INPUT
DATA
SPEED RATIO=GEAR RATIO=S(FOR IDENTICAL NUMBER OF POLE PAIRS
ON THE TWO SYNCHROS)
Sθθ
*USUALLY 1:1
Figure 1.17. Two-Speed Synchro TransducerConfiguration.
TRANSDUCER
1XCX
nXCX
1XCT
nXCT
θI N I N
ref: 1X OUTPUT
nX OUTPUT
θ
for changing θ
error
error
00 1800 3600
let n = 5
θ
θ
Figure 1.18. Two-Speed Servo Loop.
Figure 1.19. Relative RMS Magnitudes of Coarseand Fine Outputs.
FUNDAMENTALS
This can be accomplished with a sensor to monitorthe coarse output level and control which error signalis used. The crossover level is set within 90° or lessof the fine speed null (approximately 3° in a 1:32 sys-tem) to prevent hang ups at false nulls on the fineoutput. Since the fine CT turns n times for one turnof the coarse CT there will be n points where its out-put will be at null, therefore, the fine error signal isonly used when it is within 90° of the true null. Ormore correctly when the coarse null is within (90°/n).
Stick-off Voltage
If Figure 1.20 is examined it can be seen that for botheven and odd ratios a fine and coarse stable nullexists together only at 0° (or 360°). A stable null isdefined as the point where the error signals passthrough zero in the positive direction. If a servo is setup to drive towards 0° misalignment it will drive awayfrom 180° because the phase of the error signal for adisplacement will be opposite than that at 0°. Anunstable null will exist at 180° but the slightest dis-turbance will cause it to drive to the correct null.
If the coarse/fine ratio is even, the unstable coarsenull at 180° will be accompanied by a stable fine null.
If the coarse/fine ratio is odd, the coarse and fine sig-nals each have unstable nulls at 180°, and there isno danger of the system accidentally remainingaligned at 180°, but if an even ratio system happened
to be at 180° from the true stable null (as can happenat power turn on or some forms of switched systems)then the servo would sense the coarse null (eventhough an unstable one) and switch to the fine errorsignal. Since the fine error signal is at a stable nullthe system would “lock in” at 180° from where itshould.
To enable even-ratio systems to function without thepossibility of nulling at 180°, a stick-off voltage isadded to the coarse control signal.
Figure 1.21 shows a simplified circuit for this pur-pose. When a fixed AC voltage of the correct phaseis added to the coarse signal, and the stator of thecoarse control transformer (or transmitter) is suitablyrepositioned, the coarse system can be made to nullat 180° of fine rotation, which is unstable fine null.The null at 0° is unaffected.
In detail, the coarse control transformer signal/mis-alignment curve is shifted obliquely so that it stillpasses throughout the same null at 0° but a differentnull at 180°. The stick-off voltage shifts the coarsenull horizontally by 90° of fine rotation, and thecoarse synchro offset shifts the error signal by a fur-ther 90° of fine rotation. At 0° the two 90° changescancel; at 180° they add up to prevent a fine stablenull at 180°.
“Stick-off” voltage can be added to any even-ratio,two-speed system, regardless of the method ofadding the coarse and fine signals. The voltage musthave the same phase as the normal coarse signal toavoid introducing quadrature components at null. Atwo-speed S/D converter is described in detail onpages 33 through 36. Three-speed, four-speed, andeven more highly articulated synchros are practical,although they are rarely used. In all multispeed ser-vos, the accuracy of the gearing must be highenough to support the added resolution provided bythe fine synchro.
Where mechanical gearing size and/or errors cannotbe tolerated, electrical two-speed synchros can beused. Electrical two-speed synchros are deviceswith two rotor/stator winding sets. The two-speed
13
EVEN RATIO n = 8
ODD RATIO n = 5
360˚/0˚
360˚/0˚
360˚/0˚
360˚/0˚
180˚
180˚
1x (coarse)
nX (fine) n=EVEN
1x (coarse)
nX (fine) n=ODD
Figure 1.20. CT Voltage/Misalignment Curves forEven and Odd Ratios.
FUNDAMENTALS
14
COARSE CT
ACSTICKOFFVOLTAGE
In
LEV
EL
SE
NS
OR
CROSS OVERSWITCH
SWITCHED ERRORVOLTAGE, Es
FINE CT
ES WITHOUT STICKOFF
ES WITH STICKOFF & OFFSET COARSE CT
FALSE STABLE NULL
STABLE NULL UNSTABLENULL
STABLENULL
OFFSET DUE TOCOARSE CTOFFSET
180
180
360/0
360/0 360/0
360/0
OFFSET DUE TOSTICKOFF VOLTAGE
Figure 1.21. Unstable False Null Shifted by Adding ‘Stick-Off’ Voltage to Coarse Signal and DisplacingCoarse Control Transformer Output.
FUNDAMENTALS
15
ratio (N:1) is achieved by having Nx as many in the“fine” rotor/stator set than there are in the “coarse”rotor/stator set. Since the individual rotor/stator setson an electrical two-speed synchro are brought outseparately to appropriate sets of terminal, they maybe treated (i.e., connected) in the same manner asseparate mechanical two-speed transducers.
The advantages of electrical two-speed synchros(resolvers are also available in this configuration)are: no inaccuracies due to gear train wear or back-lash, increased reliability due to fewer moving parts,lower driving torque required, and smaller size. Withall these things considered, the cost differentialbetween a mechanical two-speed arrangement (twosynchros and a gear train) and a single electricaltwo-speed unit is marginal. Electrical two-speed syn-
chros are generally available in binary ratios, i.e., 8,16, and 32 to 1. Electrically there is no differencebetween electrical and mechanical units.
Digital Data Conversion Techniques forSynchro/Resolver Systems
This handbook does not attempt to study every cir-cuit technique ever used for synchro/resolver datamanipulation. It does not even attempt to present anencyclopedic survey of every kind of circuit in currentuse; instead, it reflects a selective concentration onwhat authors deem to be the most important andeffective modern techniques. To justify our selec-tions, we offer the following brief review of older con-version techniques.
VX
VA
INPUT
VYINPUT
R
C
Vref
Vref
A
GATE ON
GATE OFFZEROCROSSINGDETECTORS
CLOCKPULSE IN DIGITAL VALUE OF θ
COUNTER
RESOLVER(OR SYNCHROPLUS SCOTT "T")
VX
VY
Vref
θ
VA
VA
VA
VB
VB
VX
INPUT
VY
INPUT
A B
2θ
Figure 1.22. Single-RC Phase-Shift Synchro-Digital Converter.
Figure 1.23. Two-RC Phase-Shift S/D Converter (uses same zero-crossing detectors, gate, counter, andclock-pulses as that of Figure 1.22).
FUNDAMENTALS
16
1.Single-RC phase-shift approaches (Figure 1.22).
2.Double-RC phase-shift approaches (Figure 1.23).
3.Real-time-function-generator approaches(Figure 1.24).
4.Ratio-bounded harmonic oscillator approaches(Figure 1.25).
5.Demodulation of sine and cosine with µP andA/Ds (Figure 1.26).
Let us briefly consider each of them in turn, recog-nizing that the examples of each type given here aresubject to wide variation.
The single-RC phase-shift synchro-to-digitalconverter shown in Figure 1.22 operates by com-paring the zero-crossing times of the reference waveand the phase-shifted sine-to-cosine (resolver-for-mat) wave, VA at point A in the diagram. It can beshown that, if ωRC=1 (where ω = 2π times the refer-ence carrier frequency) the phase shift between thevoltage from point A to ground and the reference
FUNCTIONGENERATOR
PROGRAMMINGCIRCUITRY
ANALOGCOMPUTINGCIRCUITRY
FUNCTIONGENERATOR
FUNCTIONGENERATOR
Vx
Vy
A/DCONVERTER
DIGITAL SIGNALS (θ - φ)
ANALOG VOLTAGEPROPORTIONAL TO (θ - φ)
DIGITALOUTPUT= θWHEN(θ - φ) ISAT NULL
Vy f (φ)
Vx f (φ)
θin
φ
SIN DC SIN
COS DC COS
DEMODULATOR
DEMODULATOR
A/D
A/D
DIGITALANGLEOUTPUT
DIG SIN
DIG COS
SCOTTT
S1
S2
S3
REF
REF
µP
VxBOUND
INTEGRATOR NO.1 INTEGRATOR NO.2
A
VyBOUND
UNITY GAININVERTER
B
Figure 1.24. Real-Time Trigonometric — Function-Generator S/D Converter.
Figure 1.25. Harmonic Oscillator S/D Converter.
Figure 1.26. Demodulation, A/D, and µP approach to S/D.
FUNDAMENTALS
wave is exactly equal to (θ−α). If α, the time-phaseerror caused by rotor-to-stator phase lead, is smallcompared to θ, the time interval (tθ) between the zerocrossings of VA and Vref is a measure of θ. In Figure1.22, a counter totals the number digital clock pulseduring the time interval tθ, and the clock frequency isscaled appropriately, to make the count read directlyin digitally coded angle.
It is readily apparent that the only advantage of thesingle-RC S/D or R/D converter is its simplicity. Thedisadvantages of this approach are:
• The difficulty of maintaining ωRC=1 due to instabil-ity in the capacitor with time and temperature.
• The difficulty of maintaining ωRC=1 due to varia-tions in the carrier frequency. (These may beeliminated, at considerable expense, by generat-ing the carrier in the converter, preferably by divid-ing down from the clock frequency.)
• The difficulty of maintaining negligible time-phaseerror (α) in the reference wave. (Some relief isobtained by compensating the reference input byusing a lag network, but α varies with temperature,θ, excitation, and from synchro to synchro.)
• Significant error due to noise, quadrature compo-nents in Vx and Vy, and harmonics in Vx and Vy,particularly around the zero (θ = 0°) and full scale(θ = 360°).
• Staleness error, due to the fact that only one con-version is made per cycle.
• The circuit will only work at one specific carrier fre-quency.
The above list confines the single-RC phase-shiftconverter to relatively low accuracy applications.
The double-RC phase-shift synchro-to-digitalconverter shown in Figure 1.23 eliminates at leasttwo of the error sources that limit the performance ofthe single-RC converter. In this approach, VA and VBhave equal but opposite phase shifts with respect to
Vref. By measuring the time interval (t2θ) betweenthe zero crossing of VA and VB, and using it to gatea clock pulse into the counter, the count may bescaled to read directly in degrees of θ (i.e., at one-half the clock-pulse frequency used in the single-RCdesign). The disadvantages of this approach are thesame as those listed for the single-RC approach,with the following exceptions:
• The time-phase error (α) in the Vref is no longer anerror factor.
• The reference carrier frequency need not be quiteas stable as before, but it is still a major error fac-tor, and must still be internally generated, for evenmoderate accuracy.
• There is a partial improvement in effective RC sta-bility, due to the tendency of the capacitors to trackeach other with temperature.
• There is an added difficulty in the double-RCapproach - a 180° anomaly that causes the samereading at θ and θ ±180°. This requires special cir-cuitry to prevent false readings.
All other error factors remain the same; nevertheless,at considerable expense, the double-RC phase-shiftS/D or R/D converter can be made to perform atmoderate accuracies ... of the order of a worst-caselimit of error of 10 minutes.
The real-time trigonometric function-generator approach of Figure 1.24 takes many forms - one ofwhich, and perhaps the most advanced, is analyzedin great detail in Section V. In this generalized dis-cussion, however, we shall categorize it as follows:the resolver-format signals Vx and Vy are applied totrigonometric function generators (tangent bridges orsine/cosine non-linear multipliers) and, by manipulat-ing the resultant generator outputs in accordancewith trigonometric identities, an analog voltage pro-portional to the difference between θ and the func-tion-generator setting φ is developed. If the integralof this voltage is digitized, and the digital value fedback, as φ, to program the bridge so as to drive (θ -φ) to null zero, the digital value of φ will equal the
17
FUNDAMENTALS
shaft angle θ. This scheme has the following advan-tages over the two preceding approaches:
• It is a real-time, continuous measurement of θ;hence, there is no staleness error.
• It is inherently a ratio technique (Vy/Vx) - alwaysan advantage in maintaining accuracy.
• It is independent of the carrier frequency - indeedit is broadband, and will work over severaldecades of frequency, without special designs.
• It makes it possible to reject quadrature compo-nents.
• It makes it possible to reject most noise compo-nents.
• It rejects most harmonic distortion, being responsiveonly to differential harmonics between Vx and Vy.
• It is relatively independent of reference time-phaseerror, α.
• There is no 180° anomaly.
Implementation of the real-time function-generatorapproach was more expensive than either of theforegoing schemes, but mass-production techniquesand integrated circuits have erased the cost differ-ences. The real-time function-generator approachcan achieve state-of-the-art performance - accura-cies better than ±2 seconds.
Now, let us consider an approach that has some ofthe advantages of Figure 1.24 but also a few disad-vantages. In the past it offered a good price perfor-mance compromise but with the recent introductionof monolithic R/Ds it is no longer a viable approach
for new designs. It is discussed here only for histor-ical purposes. This approach is called the ratio-bounded harmonic oscillator circuit and is shownin Figure 1.25. (This approach is analyzed in greatdetail on pages 29 to 30.) In this technique, a pair ofintegrators are cascaded with a unity-gain inverter,into a closed loop with positive feedback, so that theywill oscillate a frequency determined by their RCtime constants. (Note that the oscillation frequencyneed have no special relationship to the referencecarrier frequency, except that it is usually high, forconversion speed.) First, the integrators are “bound”(i.e., presented with initial conditions) by presettingtheir output voltages in the ratio Vx/Vy. These volt-ages are obtained by simultaneous sampling of Vxand Vy. Then, the loop is allowed to oscillate, andthe ratio of the time interval between the zero cross-ing of the signal at B in the positive going direction tothe total natural period of oscillation is exactly pro-portional to θ. This ratio is digitized by counting clockpulses, as in earlier schemes. Indeed, the circuit ofFigure 1.25 has some significant disadvantages: It isnot a real-time measurement, but is, instead, a peri-odic technique, like the phase-shift converters, andtherefore suffers from staleness error and is costly toproduce compared to modern tracking S/D or R/Ddesigns.
The Demodulation, A/D, and µP approach to syn-chro/resolver conversion has been used from timeto time but is now seldom used for new designsbecause it burdens the µP, has significant stalenesserrors, is susceptible to noise and cannot respondadequately in a dynamic environment.
In this approach, shown in Figure 1.26, the sine andcosine analog data is demodulated with the referenceto obtain DC sine and DC cosine. These are thenmultiplexed into an A/D converter. The two data wordsare then fed to the µP which determines the angle.
18
19
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
SECTION II
Figure 2.1. Block Diagram - Synchro-to-Digital Converter
The Tracking Converter
Figure 2.1 is a functional block diagram of a 16-bitsynchro-to-digital tracking converter. Three-wiresynchro angle data are presented to a solid-stateScott-T (see page 6) which translates them into twosignals, the amplitude of one being proportional tothe sine of θ (the angle to be digitized), and theamplitude of the other being proportional to thecosine of θ. (The amplitudes referred to are, ofcourse, the carrier amplitudes at the reference fre-quency - i.e., the cosine wave is actually cosθ cosωt,but the carrier term cosωt will be ignored in this dis-cussion, because it will be removed in the demodu-lator and, in theory, contains no data.)
A quadrant selector circuit contained in the controltransformer enables selection of the quadrant in
which θ lies, and automatically sets the polarities ofthe sinθ and cosθ signals appropriately, for computa-tional significance. The sinθ, cosθ outputs of thequadrant selector are then fed to the sine and cosinemultipliers, also contained in the control transformer.
These multipliers are digitally programmed resistivenetworks. The transfer function of each of these net-works is determined by a digital input (which switch-es in proportioned resistors), so that the instanta-neous value of the output is the product of the instan-taneous value of the analog input and the sine (orcosine) of the digitally encoded angle φ. If the instan-taneous value of the analog input to the sine multi-plier is cosθ, and digitally encoded "word" presentedto the sine multiplier is φ, then the output is cosθ sinφ.
CONTROLTRANSFORMER
DATALATCH
GAIN DEMODULATOR
16-BITUP/DOWNCOUNTER
HYSTERESIS
+REF -REF BIT
R 1
VCO&
TIMING
INH EM DATA EL CB
INTEGRATOR
VELINPUT OPTION
S1S2S3S4
C 1
E
LOS
e D
Thus the two outputs of the multipliers are:
from the sine multiplier, cosθ sinφ
from the cosine multiplier sinθ cosφ
These outputs are fed to an operational subtractor, atthe differencing junction shown, so that the input fedto the demodulator is:
sinθ cosφ – cosθ sinφ=sin(θ-φ)
The right-hand side of this trigonometric identity indi-cates that the differencing-junction output representsa carrier-frequency sine wave with an amplitude pro-portional to the sine of the difference between θ (theangle to be digitized) and φ (the angle stored in digi-tal form in the up-down counter). This point is ACerror and is sometimes brought out of the converteras "e."
The demodulator is also presented with the refer-ence voltage, which has been isolated from the ref-erence source and appropriately scaled by the refer-ence isolation transformer or buffer. The output ofthe demodulator is, then, an analog DC level, pro-portional to: sin (θ – φ). In other words, the output ofthe demodulator is the sine of the "error" betweenthe actual angular position of the synchro or resolver,and the digitally encoded angle, θ, which is the out-put of the counter. This point, the DC error, is alsosometimes brought out as "D" while the addition of athreshold detector will give a Built-In-Test (BIT) flag.Note that, for small errors, sin (error) ≅ (error). Thisanalog error signal is then fed to the circuit blocklabeled "error processor and VCO." This circuit con-sists essentially of an analog integrator whose output(the time-integral of the error) controls the frequencyof a voltage-controlled oscillator (VCO). The VCOproduces "clock" pulses that are counted by the up-down counter. The "sense" of the error (φ too high orφ too low) is determined by the polarity of φ, and isused to generate a counter control signal "U," whichdetermines whether the counter increments upwardor downward, with each successive clock pulse fedto it. (For reasons discussed below, it is also conve-nient to put a small "hysteresis" into the reaction of
this error processor.) This direction line, (U), can beused to tell the system which direction the synchro orresolver is moving. The "clock" or "toggle" line isbrought out as the converter busy (CB) signal. Thecarry signal of the last stage of the counter can beused as a major carry (MC) in multiturn applications.
Note that the two most significant bits of the angle φ,stored in the up-down counter, are used to controlquadrant selection (as explained on pages 9 and47), and the remaining 14 bits are fed (in parallel) tothe digital inputs of both multipliers. (It is also inter-esting to note that the fact that the first two bits of φhave been "stripped off," for quadrant selection doesnot invalidate the explanations given above sincetheir data merely represent four sets of data fromzero in 90° increments added to the sine/cosine cal-culations of the function generators, which are strict-ly one-quadrant full-scale devices).
Finally, note that the up-down counter, like anycounter, is functionally an integrator - an incrementalintegrator, but nevertheless an integrator. Therefore,the tracking converter constitutes in itself a closed-loop servomechanism (continuously attempting tonull the error to zero) with two lags ... two integratorsin series. This is called a "Type II" servo loop, whichhas very decided advantages over Type I or Type 0loops, as we shall see.
To appreciate the value of the Type II servo behaviorof this tracking converter, consider first that the shaftof the synchro or resolver is not moving. Ignoringinaccuracies, drifts, and the inevitable quantizingerror (e.g., ±1/2 LSB), the error should be zero (θ = φ), and the digital output represents the trueshaft angle of the synchro or resolver.
Now, start the synchro or resolver shaft moving, andallow it to accelerate uniformly, from dθ/dt = 0 todθ/dt = V. During the acceleration, an error willdevelop, because the converter cannot instanta-neously respond to the change of angular velocity.However, since the VCO is controlled by an integra-tor, the output of which is the integral of the error, thegreater the lag (between θ and φ), the faster will thecounter be called upon to "catch up." So when the
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
20
velocity becomes constant at V, the VCO will havesettled to a ratio of counting that exactly correspondsto the rate of change in θ per unit time and instanta-neously θ = φ.This means that dφ/dt will always equal("track") dφ/dt without a velocity or position error. Theonly errors, therefore, will be momentary (transient)errors, during acceleration or deceleration.Furthermore, the information produced by the track-ing converter is always "fresh," being continuallyupdated, and always available, at the output of thecounter. Since dθ/dt tracks the input velocity it canbe brought out as a velocity (VEL) or tracking ratesignal which is of sufficient linearity in modern con-verters to eliminate the need for a tachometer (tach-o-generator) in many systems. Suitably scaled it canbe used as the velocity feedback signal to stabilizethe servo system or motor. A further discussion ofdynamic errors can be found in Section VII.
In older designs, use of the inhibit (INH) commandwould lock the converter counter while data was trans-ferred. This could introduce errors if the INH wasapplied too long. If the counter was frozen for morethan a few updates the catch up or reacquisition timecould be significant. Modern designs now use latchedand buffered output configurations which eliminatethis problem and greatly simplify the interface.
Two additional features of this converter should bementioned before concluding this description. Oneconcerns the fact that the velocity range over whichthe device will track perfectly (i.e., over which thevelocity error will be zero) is determined primarily by
the upper frequency limit of the VCO/counter combi-nation. A typical high-performance 14-bit, 400 Hzconverter will track at 12 RPS (by no means the limitof current technology), which corresponds to 12 x 214
counts/sec, or 196,608 counts/sec.
The other feature is indirectly related to tracking ratealso. To optimize recovery from velocity changes(i.e., to minimize acceleration errors) the gain of theerror-processor integrator, and the sensitivity of theVCO it drives, should both be high. This encourages"hunting" or "jitter" around the null (zero-error) point,due primarily to quantizing "noise." It is for this rea-son that a small (one bit) hysteresis threshold is builtinto the error processor. This threshold is muchsmaller than the rated angular error.
Several other functions generally incorporated intomodern S/D or R/D converters to make them moreversatile are loss of signal (LOS) and enable (EL andEM). LOS is used for system safety and as a diag-nostic testing point. It is generated by monitoring theinput signals. Loss of both the sine and cosine sig-nals at the same time will trigger the LOS flag. Theenable (EL and EM) line(s) enable the output buffers,usually in two 8-bit bytes for use with either 8- or 16-bit buses.
Because the tracking converter configuration ofFigure 2.1 is the most advanced and versatile deviceof its kind in use today, we shall examine and analyzeits static and dynamic performance in more detail ...principally in Section VII.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
21
RESOLUTIONInput FrequencyTracking RateBandwidthKaA1A2ABacc-1 LSB lagSettling Time
PARAMETER
BITSHertz
RPS min.Hertz
1/sec2 nominal1/sec nominal1/sec nominal1/sec nominal1/sec nominal
deg/sec2 nominalms max.
UNITS
10 12 14 16360 - 1000
160 40 10 2.5220 220 54 54
81.2k 81.2k 12.5k 12.5k2.0 2.0 0.31 0.3140k 40k 40k 40k285 285 112 11252 52 52 52
28.4k 7.1k 275 69160 160 300 800
400 HZ
10 12 14 1647 - 1000
40 10 2.5 0.6140 40 14 143k 3k 780 780
0.29 0.29 0.078 0.07810k 10k 10k 10k55 55 28 2813 13 13 131k 264 17.2 4.3
350 550 1400 3400
60 HZBANDWIDTH
Table 2.1. Dynamic Characteristics
22
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
Briefly though, the dynamic performance of thedynamic performance of the Type II tracking con-verter can be determined from its transfer functionblock diagram (shown in Figure 2.2) and open- andclosed-loop Bode plots (shown in Figures 2.3 and2.4).
Table 2.1 lists the parameters and dynamic charac-teristics relating to one of DDC's leadership convert-ers, the SDC-14560 series. The values of the vari-ables in the transfer function equation are given onthe applicable data sheet. All DDC's tracking syn-chro-to-digital or resolver-to-digital converters arecritically damped and have a typical small signal step response (100 LSB step) as shown in Figure2.5. Large signal step response is governed by the
ERROR PROCESSOR
RESOLVERINPUT
CONVERTER TRANSFER FUNCTION G =WHERE:
2 A = A A 1 2
VELOCITYOUT
DIGITALPOSITION
OUT(φ)
VCOCT SA + 1 1 B
S S + 1 10B
H = 1
2 SA + 1 B
2 SS + 1 10B
+
-
e A 2 S
2A 2 2 A ω (rad/sec)
CLOSED LOOP BW (Hz) = 2 Aπ
-12 db/oct
4
B A
2A
-6 db/oct
10Bω (rad/sec)
Figure 2.2. Transfer Function Block Diagram.
Figure 2.3.Open-Loop Bode Plot. Figure 2.4. Closed-Loop Bode Plot.
maximum tracking rate of the converter and the smallsignal settling time. A typical response is shown inFigure 2.6. In the newer designs, such as the RDC-19220 series, bandwidth can be selected to suit theparticular application. A good rule to follow is to keepthe carrier frequency four times the bandwidth. Asthe bandwidth becomes a larger percentage of thecarrier it will become progressively more jittery untilat the extreme it will attempt to follow the carrierrather than the carrier envelope.
Use of a "Synthesized" Reference
As the error analysis (see Sections VII and VIII) ofthe synchro-to-digital converter of Figure 2.1 willshow, one potentially significant source of error is
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
23
0
100
10 20 30 40 50
Out
put (
LSB
s)
Time (ms)
LOW BANDWIDTH - 10-BIT MODE
0
100
10 20 30 40 50
Out
put (
LSB
s)
Time (ms)
LOW BANDWIDTH - 12-BIT MODE
0
100
10 20 30 40 50
Out
put (
LSB
s)
Time (ms)
LOW BANDWIDTH - 14-BIT MODE
0
100
10 20 30 40 50
Out
put (
LSB
s)
Time (ms)
LOW BANDWIDTH - 16-BIT MODE
Figure 2.5. Small Signal Step Response (100 LSB Step).
0
100
2 4 6 8 10
Out
put (
LSB
s)
Time (ms)
HIGH BANDWIDTH - 10-BIT MODE
0
100
4 8 12 16 20
Out
put (
LSB
s)
Time (ms)
HIGH BANDWIDTH - 12-BIT MODE
0
100
2 4 6 8 10
Out
put (
LSB
s)
Time (ms)
HIGH BANDWIDTH - 14-BIT MODE
0
100
20 40 60 80 100
Out
put (
LSB
s)
Time (ms)
HIGH BANDWIDTH - 16-BIT MODE
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
24
0
60
120
180
10 20 30 40 50
Out
put A
ngle
(de
gree
s)
Time (ms)
LOW BANDWIDTH - 10-BIT MODE
0
60
120
180
10 20 30 40 50
Out
put A
ngle
(de
gree
s)
Time (ms)
LOW BANDWIDTH - 12-BIT MODE
0
60
120
180
20 40 60 80 100
Out
put A
ngle
(de
gree
s)
Time (ms)
LOW BANDWIDTH - 14-BIT MODE
0
60
120
180
20 40 60 80 100
Out
put A
ngle
(de
gree
s)
Time (ms)
LOW BANDWIDTH - 16-BIT MODE
0
60
120
180
1 2 3 4 5
Out
put A
ngle
(de
gree
s)
Time (ms)
HIGH BANDWIDTH - 10-BIT MODE
0
60
120
180
2 4 6 8 10
Out
put A
ngle
(de
gree
s)
Time (ms)
HIGH BANDWIDTH - 12-BIT MODE
0
60
120
180
10 20 30 40 50
Out
put A
ngle
(de
gree
s)
Time (ms)
HIGH BANDWIDTH - 14-BIT MODE
0
60
120
180
20 40 60 80 100
Out
put A
ngle
(de
gree
s)
Time (ms)
HIGH BANDWIDTH - 16-BIT MODE
Figure 2.6. Large Signal Step Response (179° Step).
time phase shift (typically, a phase lead between therotor excitation reference signal and the voltagesinduced in the stator windings of the synchro orresolver). This can cause errors due to the fact thatthe voltage applied to the rotor is also used as thereference input to the phase-sensitive demodulator.Any appreciable lag or lead between this referencevoltage and the modulated carrier will greatly reducethe ability of the demodulator to reject quadrature ofthe synchro-input signals. (The sources of quadra-ture components are discussed Section VIII, but pri-marily they comprise speed voltages induced into thesynchro or the resolver stator and differential staticphase shift from the rotor to each stator output.)
Although a first order correction can be made forrotor/stator reference phase shift by introducing aphase-advancing network (Figure 2.7) between thereference input and the demodulator, this phase cor-rection can only be approximate, since the nominalphase lead of a particular synchro or resolver designis not a tightly controlled parameter, and varies fromsynchro to synchro, and also with temperature, load-ing, etc. Trimming the phase-correction network for aparticular synchro is practical, if somewhat inconve-nient. A much better solution to the problem of ref-erence phase errors is the use of "synthesized refer-
ence." A synthesized reference is a reference volt-age that is derived directly from the stator-generatedsignals (or from their Scott-T-transformed resolver-format resultants). This technique is illustrated inFigure 2.8.
Before proceeding to a description of the referencesynthesizer it should be said that it is necessary togenerate a precise reference only in conversion sys-tems and instruments that require better than 1minute accuracy ... or in conversion systems orinstruments that must operate in several modes hav-ing different phase shifts.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
25
SCOTT TTRANSFORMER
SYNCHROINPUT
B SIN θ COS (ωt + α)
B COS θ COS (ωt + α) SYNTHESIZEDREFERENCEK COS (ωt + α )
S1
S2
PHASECOMPARATOR
REFERENCE GENERATOR
QUADRANT SELECTOR
EXTERNAL REFERENCE
INPUT
A COS (ωt )
PHASE-LEADNETWORK
(+α)
REFERENCEINPUTTOCONVERTERf (cos ωt - α)
REFERENCEVOLTAGEFROMSYSTEMf (cos ωt)
Figure 2.8. Method of Synthesizing a Reference Carrier without Phase Error.
Figure 2.7. Phase-Advancing Network.
In Figure 2.8, we see a system in which a referencesynthesizer (or "reference generator," as it is some-times called) receives three inputs:
1. The external reference, a carrier frequency signalof essentially constant amplitude: A cos (ωt).
2. The sin θ output of the quadrant selector circuitthat is part of the tracking servo of Figure 2.1:
B sinθ cos (ωt+α). Note that is the carrier phase-lead error between the external reference signaland the stator input signals.
3. The cosθ output of the quadrant selector circuit ofFigure 2.1, which has the same phase-leaderror:
B cosθ cos(ωt+α).
Inputs 2 and 3, which are always of opposite polari-ty, are subtracted algebraically into a single carriersignal, and amplitude leveled. This signal can beshown to be either K cos (ωt+α) or K cos(ωt+α+180°), where K is a constant ... either in phaseor 180° out of phase with the desired reference, andcorrected for the carrier-phase-lead error. By com-paring it with the external reference, in a "coarse"phase comparator (which merely determineswhether or not it is within ±90° of the external refer-ence), the logical decision is made between closingS1 (using the leveled algebraic sum), or closing S2(inverting the leveled algebraic sum). The output ofS1 or S2 is, then, the synthesized reference.
The time phase of the synthesized reference signalcan be dependably held to within ±5 minutes of thesin (θ - φ) signal presented to the demodulator, sincephase shifts in the multipliers and differencing circuitare very small at the carrier frequency. This level oftime-phase coherence ensures optimum quadraturerejection in the demodulator .. at least 200:1, and asmuch as 2000:1 in special designs.
The error introduced by a nominal 5.7° phase shiftand 0.1% quadrature in a converter without a syn-thesized reference is approximately:
While in a converter with a synthesized reference the5.7° phase shift is effectively reduced to 5 minutes(or 0.01°) and the error is approximately:
A very small number indeed.
The use of a synthesized reference allows an engi-neer to use the same circuit card or system design invarious applications without being concerned aboutthe phase shifts of the various synchro or resolvertransducers used.
Sampling A/D Converters
The tracking converter described first in this sectionis a very high-performance device, and is the logicalchoice for many applications; however, there areother methods of digitizing the input data represent-ing the angle θ, and at least two of them are worthdetailed study. Both take advantage of the fact thatall the data needed to determine the angle θ isknown in the carrier-envelope amplitudes of the tworesolver-format inputs at one selected instant of timeduring the carrier cycle, provided that they are mea-sured simultaneously ... assuming appropriate scal-ing. Thus, if the reference input is:
Vref = K1cos (ωt), after correction for rotor-statorphase shift, and the two resolver-format inputs are:
Vx = K2 sinθ cos(ωt);
and Vy = K3 cosθ cos(ωt),
then simultaneous samples of Vx and Vy will yield asmuch information about sinθ and cosθ as would con-tinuous observation.
The only essential requirement of this approach is toread Vx and Vy simultaneously—we must measure
Eq = tan 0.01˚ = 0.006'0.1100
Eq = tan 5.7˚ = 0.34'0.1100
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
26
the envelope amplitudes at the same instant in time.Reflection will show that the ideal time for this mea-surement is at the peak of the carrier wave (eitherpositive or negative peak), when the carrier ampli-tude is largest, so that the modulated carrier waves(Vx and Vy ) will yield the largest signals with respectto noise, drift, quadrature, and other imperfections inthe measuring circuits. This optimum samplinginstant is readily obtained from the reference signal(after correcting it for synchro time-phase shift), byfirst phase-shifting that signal by 90°, so that its zero-crossing is at the correct time, then converting it byclipping (squaring off) into a pulse of the desiredwidth, whose trailing edge occurs at the peak of thephase-corrected reference wave.
Thus, most sampling converters use circuits that: (1)generate a control pulse at the peak of the referencewave; and (2) with that pulse, sample and hold - i.e.,"freeze" - the amplitudes of Vx and Vy. Note thatthis procedure yields DC levels proportional tocosθθ and sinθθ.
The simplified circuit and waveform diagrams ofFigure 2.9 illustrate the sampling proceduredescribed in the preceding paragraph.
Successive-Approximation Sampling Synchro-to-Digital Converter
Figure 2.10 shows one of the two types of samplingS/D converters to be studied in this section. Notethat the circuit contained within the dashed-line area,labeled "SSCT,” is almost identical to the quadrantselector and sine/cosine multiplier section of Figure2.1, which was analyzed earlier in this section. Infact, the only differences between Figures 2.1 and2.10 are:
1. The signals presented to the SSCT are sampledsine and cosine DC levels obtained by samplingVx and Vy, rather than continuous modulated car-riers.
2. The circuit that establishes and stores the digitalangle output word is a sequentially addressed reg-ister, rather than an up-down counter.
3. The "error processor" performs a simpler functionthan the one used in Figure 2.1, as explainedbelow.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
27
PHASESHIFTER
PEAKDETECTOR
REFERENCE GENERATED HERE
S/H STROBE LINE
RH
RLRE
F IN
SY
NC
HR
O IN
S2
S1
CH. 1 INPUT MODULE
CONVERTER
SELECTCH.1
STROBE GENERATED HERE
PH
AS
E C
OR
RE
CT
ED
RE
FE
RE
NC
E W
AVE
DC=Vx peak
DC=Vy peak
Vx
Vy
S3
DIGITAL OUTPUT
Figure 2.9. Sample/Hold Technique.
The error processor comprises only two elements: acomparator, which senses the polarity of the inputsignal, sin (θ - φ); and a gated clock-pulse generator,which produces an output pulse whenever sin (θ - φ)is positive - i.e., whenever θ is greater than φ. Thus,as long as θ exceeds φ, the error processor will feedclock pulses to the register.
The complete S/D conversion procedure may now bedescribed as follows. First, assume that the registerhas been cleared i.e., preset to all ZEROES, eitherby the internal programming logic or by externalcommand, before the peak of the reference carrierinitiates its sample command. Then, the resolver-for-mat outputs of the Scott-T synchro isolation trans-former are sampled simultaneously, at the carrierpeak, by a circuit of the type shown in Figure 2.9.The resultant DC levels are presented to the SSCT,and sin (θ - φ) is computed.
At this point, all of the bits stored in the "n"-bit regis-ter - i.e., all of the bits of the output word - are atZERO; so that the digital word presented to the sineand cosine multipliers (as the angle φ) is a set of "n"ZEROES.
Now begins a sequence of n logical "decisions,"each of which follows the pattern of the first one. Thefirst three decisions will be described in detail:
(1) The most-significant bit of the register is set toONE, so that the word φ fed to the sine and
cosine multipliers is 1000...0, corresponding toφ =180°.
(2) The error processor is then "interrogated" - thatis, its output is examined. Now, if θ is larger than180°, the value of sin (θ - φ) will be positive, andthe error processor will produce a ONE. The ONEwill allow the first stage (most significant bit) of theoutput register to remain at the ONE state. If θ isless than 180°, the error processor will not put outa ONE, but a ZERO state ... which it should be, forθ < 180°.
(3) The first decision has now been reached, andthe logic automatically proceeds to the next deci-sion...that concerning the correct state for the sec-ond most-significant bit (second stage of the reg-ister).
(4) The second stage is set to ONE, so that the out-put word is either 11000...0 (for θ > 180° in deci-sion #1) or 01000...0 (for θ > 180° in decision #1.)
(5) Again, the error processor is interrogated. Sincedecision #1 had two possible results, we shallconsider both.
(a) If θ is greater than 180°, the value of φ at thisinterrogation is 11000...0, or 270°. Thus, if θ liesbetween 270° and 360°, the second decision willbe to leave the second register stage in the ONEstate; and if θ lies between 180° and 270°, the
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
28
Vx
Vy
SAMPLINGCIRCUIT
(SEE FIG. 2.9)θIN
SSCT
SEQUENTIAL ADDRESS LOGIC
REGISTER
QUADRANTSELECTOR
SINEMULTIPLIER
COSINEMULTIPLIER
SIN(θ - φ)
180 90
CLOCK PULSES
DIGITALOUTPUT
ERRORPROCESSOR
Figure 2.10. Successive-Approximation S/D Converter.
second decision will be to return the second stageto the ZERO state.
(b) If θ is not greater than 180°, the value of φ at thisinterrogation is 01000...0, or 90°. Thus, if θ liesbetween 90° and 180°, the second decision will beto leave the second register stage in the ONEstate; and if θ lies between 0° and 90°, the secondregister stage will be returned to the ZERO state.
(6) Now, the decision-making process moves to thethird register stage, into which a ONE is intro-duced...and the process continues. Note that thisthird decision will have a "weight" of 45°, whereasthe second decision added or subtracted a possi-ble 90°, and the first decision was the "largestweight"...corresponding to ±180°.
The process described above continues through atotal of "n" decisions, each one causing the digitaloutput angle word to come closer to the exact valueof θ - "successively approximating" θ; hence thename successive-approximation converter. The lastdecision has the weight:
...and leaves the final result with ±1/2 LSB uncer-tainty. For example, for n = 13, 2² = 8,192, and the"quantization uncertainty" of the result is 360°/ 8192,or ±2.6 minutes. The resolution of the converter,then, is ±2.6 minutes, or about ±0.044 degrees.
The entire conversion process requires very littletime - indeed, if every carrier peak is to be sampledand converted, the conversion must be completed inless than one carrier period. Modern high-speedconverters are so fast that hundreds of complete,high-resolution conversions can be done in one car-rier period ... a fact that becomes important whenmultiplexed systems are considered, later in this sec-tion.
Despite this high conversion speed, the successive-approximation converter can suffer from a "stale-ness" error, due to the fact that the data determining
Least Significant Bit = n360˚
2
θ are sampled only once per carrier period. If θ ischanging, a periodically varying velocity error willresult. This error is reduced almost to zero immedi-ately after each new sample updates the register,and thereafter increases to a maximum of:
for constant velocity between samples.
The Sampling Harmonic Oscillator Synchro-to-Digital Converter
The second type of sampling S/D converter that weshall examine is illustrated in Figure 2.11. Althoughnot in common use anymore, it is discussed here forhistorical purposes. Note that the sampling tech-nique used in the converter is somewhat differentfrom that used in the sampling successive-approxi-mation converter of Figure 2.10, in that the resolver-format input signals are first fed to phase-sensitivedemodulators, the outputs of which are DC levels:
Vx = K sin θ
Vy = K cos θ
Velocity Error(in degrees)
Velocity (in )carrier frequency (in Hertz)
degreessecond=
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
29
SCOTT"T"
XFMR
SYNCHROINPUTS
SIGNALS
VrefINPUT STROBE
INPUT
STROBE
PHASESENSITIVEDEMOD'R
PHASESENSITIVEDEMOD'R
S/H
S/H
S1
S1
S2
S2
Vy
Vy
Vx
R1 R2 R RC1 C2
CLOCKPULSE
GENERATOR
CONTROLLOGIC
DIGITALCOUNTER
GATE
DIGITAL OUTPUT
AVx
Figure 2.11. Sampling Harmonic Oscillator S/DConverter.
where K is a constant and θ is the shaft angle to bedigitized. It is these DC levels that are sampled atthe appropriate time, to set the initial conditions ofthe integrators in a harmonic oscillator converter.
The remainder of the circuit comprises two main sec-tions:
(1) A two-integrator-plus-inverter chain, enclosed ina positive-feedback loop. This loop, if "unclamped"(by appropriate programming of the electronicswitches S1 and S2), will oscillate at a frequencydetermined solely in the integrator time constants.
(2) A clock-pulse generator/digital-counter circuit thatcan be gated on when the oscillator is unclamped,and gated off at the positive-going zero-crossing ofthe voltage at point "A" in Figure 2.11.
Initially, however, the loop is clamped, and preventedfrom oscillating by the closure of the electronicswitches S1 and S2 which apply the sampled DC lev-els, Vx and Vy, as initial conditions to the two inte-grators. When the integrators have stabilized atthese initial conditions, the switches are opened, theoscillation begins (see Figure 2.12) and, simultane-ously, clock pulses are gated into the counter. Whenthe positive-going zero crossing is reached (point "X"in Figure 2.12), the clock pulses are inhibited, andcounting stops. At that point, the total stored in thecounter is the digitized value of θ, the shaftangle...provided only that the clock frequency bearsthe correct relationship to the integrator time con-
stants. The proof of this relationship between θ andthe stored count, for the initial conditions described,is given below.
The voltage at point A can be shown to bear the fol-lowing relationship to the initial conditions:
If the integrator time constants are equal, and theinverter gain is unity, the natural loop-oscillation fre-quency, fL, is given by:
Note that if the time constants are not equal, the nat-ural frequency is:
where Ai is the gain of the inverter. Referring now tothe waveform of Figure 2.12, we see that at point"X", the positive zero crossing that stops the count-ing process, the following relationships hold:
sin ( - ) = 02πθ360˚
tRC
or 2πθ360˚
tRC
=
2π R , C , R , C , A
1
11 22 i
so that V = sin ( - )2πθ360˚A
f = 12πRCL
from which ω = 1RCL
tRC
V = sin (ω t - )2πθ360˚LA
where ω = 2πfL L
f = the natural oscillation frequency of the loop,L
t = the time, in seconds, measured from the moment of unclamping,
and θ = the input angle to be digitized, in degrees.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
30
X
360θRC
RC
START STOPS
COUNTING
Va
VX
(INITIALCONDITION)
t = 0
Figure 2.12. Timing Diagram for Figure 2.11.
Clearly, then, if the clock rate is proportioned so thatsome convenient number of pulses - say, 3600 - areproduced in 2πRC seconds, the count at point "X"will be:
and the total stored in the counter will represent theangle θ to a resolution of 0.1°, or 1 part in 3600. Anydesired resolution may be obtained (within the stabil-ity and accuracy limits discussed below) by selectingthe appropriate clock frequency - usually some deci-mal multiple of 360. Although it is easy and relative-ly inexpensive to stabilize the frequency of a clock-pulse generator, it is not easy to stabilize the RC timeconstants of the integrators, and it is the ratio of theclock frequency to the integrator time constants thatdetermines the attainable accuracy and meaningfulresolution ... ignoring all other sources of error. It isthis stability problem which has caused this tech-nique to be abandoned by most manufacturers.
In the most advanced harmonic oscillator designs, aphase-locked-loop clock generator is used to forcethe clock frequency to track the unavoidable driftintegrator time-constant (and to compensate forother error sources, as well), so that meaningfuloverall accuracy can be achieved. The best worst-
3600360
(θ)
case "static" error for this class of designs is ±6 min-utes at considerable cost and complexity.
In Section III, the use of the harmonic oscillator forsynchro/DC and synchro/sine-cosine conversion willbe discussed.
Multiplexing Synchro-to-Digital Converters
Either of the two sampling S/D converters previouslydescribed can be "shared" by a group of synchros orresolvers, so that more than one source of input data(i.e., more than one shaft angle) can be digitized bythe same converter circuitry, with a consequent sav-ings, not only of initial equipment cost, but also ofrequired power-supply energy, space, and weight. Inaddition, reliability is greatly enhanced, by reductionin component count. Some additional circuitry isalways required, at least to perform the multiplexing(switching) of the converter from sensor to sensor,and some systems require the use of a separate setof sample-hold circuits for each data input, as weshall see. Consequently, the use of multiplexing isless attractive for only two or three input sensorsthan it is for many more.
In the simplest approach to sharing an S/D convert-er (see Figure 2.13), the pair of sample-hold circuitsshown in Figure 2.9 are successively switched from
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
31
θ1
θ2
θn
SCOTTT
SCOTTT
SCOTTT
MUXADDRESSINPUT
MULTIPLEXER
DUAL S/HCIRCUIT
AS INFIGURE 2.9
S/DCONVERTER
STROBEINPUT
DIGITALOUTPUT
CHANNEL "N"
CHANNEL 1
CHANNEL 2
Figure 2.13. Multiplexed-Sample/Hold (Sequential Sampling) Approach to Sharing an S/D Converter.
input to input, sampling each, holding the value dur-ing conversion (which takes considerably less timethan one carrier cycle), and then sampling the next atthe peak of the next succeeding carrier cycle.
This scheme has the advantage of simplicity andeconomy, since all that is added in the way of hard-ware is a multiplexer module and one input isolationmodule (synchro or resolver) per input sensor. Thedisadvantage of successive-peak sampling is thefact that it compounds the "staleness error" men-tioned on page 29, by making each successive read-ing one full carrier period later than the precedingone; therefore, in multiplexing n inputs, the possible"skew error", as it is called, between readings of thefirst and the nth channels (as well as between twosuccessive readings of any channel) is n times thepossible skew error (due to staleness) of a convert-er-per-channel system.
(There are some second-order advantages and dis-advantages of the sequential-on-successive-peak multiplexed approach to time-sharing a converter,but they will be discussed later sections).
For data-acquisition systems in which the velocity ofone or more of the input channels is high, and for allsystems in which optimum accuracy is essential, a
much better technique for time-sharing the converteris that shown in Figure 2.14 - the simultaneous-sam-ple-and-hold approach. In this scheme, each inputsensor is equipped with its own pair of sample-holds,and all sample-holds are strobed (activated) at thesame instant ... at carrier peak, as before. The mul-tiplexer then switches the converter (only) from onepair of "frozen" sine/cosine inputs to the next, paus-ing at each input channel only long enough to digi-tize the shaft-angle data and store or report it. If theconverter and multiplexer are fast enough, manychannels can thus be scanned and converted in asingle carrier cycle, thereby freeing the sample-holds for simultaneous sampling of the very next car-rier peak, thus minimizing the possible stalenesserror to the single carrier-period value attained bythe circuits of Figures 2.10 and 2.11. Regardless ofscanning speed, however, the data sampled, held,converted, and reported in a single pass is essen-tially free of channel-to-channel skew, although it willsoon be "out of date" (stale).
Here again, there are many second-order effects toconsider, but they will merely be mentioned brieflynow, and considered in more detail in later sections:
• A possible source of skew is the aperture-timeuncertainty among the various sample-holds.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
32
CHANNEL 1
CHANNEL 2
CHANNEL "N"
θ1
θ2
θn
SCOTTT
SCOTTT
SCOTTT
S/H
S/H
S/H
S/DCONVERTER
STROBEINPUT
MULTIPLEXER
Figure 2.14. Simultaneous-Sample/Hold (Sequential Sampling) Approach to Sharing an S/D Converter.
This is the uncertainty (often called "jitter") in theinterval between the application of the hold com-mand and the actual "freezing" of the signal.
• The input/output (or transfer) gain of the sample-holds may vary slightly, creating an error.
• The hold circuits have a finite "droop rate," causedby switch leakage in the sample-hold circuit.
Note that all the above effects have the potential ofcausing error even in single channel systems,because they can create differences between thesine and cosine sample obtained by a single pair ofsample-holds. Fortunately, modern high-perfor-mance sample-holds are available that render all ofthe above effects negligible, except in the most pre-cise systems .. and even then, they can be mini-mized.
The individual multiplexer channels must be subject-ed to the same scrutiny. They, too, have settling timeand transfer-gain uncertainties, and can contributeerrors. And the isolation transformers do not all haveexactly the same time phase shifts, either. All ofthese uncertainties, however, yield to the use of themore advanced, modern hardware, and can almostalways be rendered negligible.
Finally, one must recognize that there is an errorsource that cannot be controlled by the design of thesynchro-to-digital sampling/multiplexing/conversionsystem: the random variation in rotor-to-stator time-phase-shift in the sensors themselves. First-ordercorrection of these uncertainties is discussed later,but they are always a final limitation on all multichan-nel systems.
In the "addressing" of the multiplexer - i.e., themeans by which it is commanded to switch fromchannel to channel - it is important to note that thescanning of a set of channels need not be sequen-tial. The multiplexer may be commanded to selectchannels in any order. This capability is called "ran-dom" scanning, and may take many forms - arbitrarysequences that have no predictable pattern butrespond instead to a computer's reactive behavior; ordeliberate "skipping" of certain channels in asequence on certain passes; or attenuated-scan/full-scan programs, in which some channels are exam-ined in every pass, some in every tenth pass, etc.
Synchro- or Resolver-To-Digital Converters forTwo-Speed Systems
Earlier, on page 11, the characteristics of two-speedsynchros for very high-resolution applications were
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
33
QUADRANTSELECTOR
FUNCTIONGENERATOR
ISOLATIONXFMR(FINE)
ERRORPROCESSOR
UP-DOWN COUNTER
QUADRANTSELECTOR
ISOLATIONXFMR
(COARSE)
DIGITALMULTIPLIER
S1S2S3
S1
S2
S3
RHRL
FINEERROR
COARSEERROR
CROSS-OVERDETECTOR
INHCB
DIGITALOUTPUT
sin
sin
sin
cos
cos
cos
FG H
D E1
16
A B C
COARSESYNCHRO
FINESYNCHRO
FUNCTIONGENERATOR
I
Figure 2.15. Two-Speed S/D Converter.
introduced. Typical converter circuitry for digitizingtwo-speed inputs is shown in Figure 2.15. Note itssimilarity to the basic single-speed tracking convert-er of Figure 2.1. In fact, if one considers only circuitblocks A through E, the "coarse" converter, the cir-cuits are identical. The "fine" converter feeds circuitblocks F, G, and H, and shares blocks I, D, and E, theerror processor, cross-over detector and switchingcircuit and the up-down counter, with the coarse-syn-chro converter.
Each of the two sets of circuit blocks describedabove constitutes, in itself, a single-speed trackingconverter. The only difference between them is thatthe coarse loop has much lower resolution - i.e.,fewer "bits". The fine-synchro converter provides theadditional resolution required by the application. The
number of bits provided by the coarse converter isdetermined by the speed ratio, and is always at leasta fraction of a bit higher than the value of Nc, calcu-lated from:
Where Nc is the resolution of the coarse-synchroconverter, and Vf/Vc is the speed ratio of the syn-chros.
Circuit block I, the crossover detector, monitors thesin (θ - φ) error signal produced at the differencingjunction following the sine/cosine multipliers of the
1 N2
90˚ of the fine synchro V /V
≤f cc
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
34
COARSEGEAR
FINEGEAR TRANSDUCER
DIGITALDATA
DIGITALPROCESSOR
M
1
18
Figure 2.16. Microprocessor Combining of Two-Speed Data.
R/D
R/D
FINE
COARSE
RESULTANTANGLE
nx
1x
5483
5483
Figure 2.17. Two-Speed Resolvers.
The output data can be interpreted by a user written software program or through hardware using 4-bit binaryadders with carry (5483). See Figure 11.22 for details.
coarse converter, and, when that error signal fallsbelow approximately 90° of the fine converter it gatesthe error signal of the fine converter into the errorprocessor.
It is important to note that the sine/cosine multipliersof both converters are simultaneously presented withthe digital state of the up-down counter ... so thatwhen the coarse-to-fine crossover occurs, the transi-tion is smooth, and the tracking continues withoutsignificant discontinuity. Anytime the coarse-convert-er error signal exceeds the crossover threshold ofthe coarse converter, the crossover detector switch-es the error processor back to the error signal pro-duced by the coarse converter.
Although it may not be immediately obvious, it is truethat the behavior of this two-speed tracking convert-er is exactly the same as that of the single-speedtracking converter. Both are true Type II closed-loopservos; both are free of velocity error, and both pre-sent information that is always "fresh."
Testing S/D Converters
Testing or evaluating a synchro-to-digital or resolver-to-digital converter will generally require a synchrostandard (a calibrated synchro with an accurate dial ora synchro/resolver simulator), an interconnection boxor fixture, and LED bank or Digital Voltmeter (DVM).
Single Channel S/D or R/D Converter
Figure 2.18 illustrates configurations to test static accuracy on single-channel tracking or samplingconverters. A LED driver or suitable readout is nec-essary for each of the data outputs. (The circuitshown in Figure 7.7, is recommended.) The syn-chro/resolver standard is set to the test angles. Theangles corresponding to the LEDs that are on areadded and compared with the standard angle. Table2.2 shows the relationship of angles vs. bits.
A typical room temperature error curve is shown inFigure 2.19. Each quadrant is identical; the errorshown is for the first quadrant. Error limits are alsoindicated for temperature extremes.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
35
+15 +5 -15 GND
S1
S2
S3
S1
S2
S3
S1
S2
S3
RH
RH
RH
RHRL
RL
RL
RL
SYNCHROSIMULATORSIM 31200
CX WITHVERNIER
S/DCONVERTER
MSB
LSB
LAMP &DRIVER
LAMP &DRIVER
TOOR
REFERENCESR 203
SYNCHRO ANGLEINDICATOR
(a) (b)(c)
Figure 2.18. Test Configurations, Single-Channel Tracking and Sampling Converters.
36
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
Multiplexed S/D Converters
Figure 2.20 illustrates the test setup for multiplexedS/D converters. It requires, in addition to power sup-plies, an accurate source of synchro or resolver sig-nals, a synchro standard or a synchro with a vernierdial, and a synchro angle indicator. Either a rotaryswitch or individual toggle switches can be used toselect the channel. The delay one-shot (OS) insuresthat the conversion occurs after the completion ofsampling. It is recommended that the displays beoperated from a separate power supply to preventoverloading of the test power supplies, which canresult in erratic behavior. (For example, surge cur-rent when several displays are turned on can bequite high, momentarily pulling the supply out of reg-ulation.) Testing is accomplished in the same man-ner as for single-channel S/D converters. The syn-chro standard is set to the test angles, and valuescorresponding to the lighted lamps are added andcompared to the input.
Dynamic Testing
In many applications, the dynamic performance ofS/D or R/D converters is very important. Figure 2.21
illustrates a relatively simple method of verifying thetracking capability of a S/D or R/D converter. A D/Sor D/R is used to drive the S/D or R/D because of itsease of programming and fast response. The clockdrives the up-down counter (up-down for directioncontrol) at various rates to cause the D/S or D/R con-verter output to simulate a rotating synchro orresolver. The output of the counter is then comparedwith the output of the converter in a digital compara-tor and the difference is displayed as the loop error.Usually, to make observation easier, the comparator output has a freeze line to enable taking data on thefly at random. This is called the "Monte Carlo" tech-nique since the samples are random and the datastatistical. With units having position error outputs (eor E), these can be monitored.
With the advent of converters with a high-qualityanalog velocity output (VEL) suitable for use as thevelocity feedback in a servo loop, it has become nec-essary for manufacturers to test this parameterunder conditions dynamically similar to how they areexpected to be used. This is done by driving an up-down counter with a precision variable clock which inturn drives a very accurate D/S or D/R converter.The D/S or D/R converter drives the S/D or R/D
2N LSB AS % OFFULL SCALE
DEGREESPER BIT
MINUTESPER BIT
SECONDSPER BIT
RADIANSPER BIT
RESOLUTIONN IN BITS
1248
163264
128256512
1,0242,0484,0968,192
16,38432,76865,536
131,072262,144524,288
1,048,576
100.50.25.12.56.253.1251.5625.78125.390625.1953125.09765625.04882813.02441406.01220703.00610352.00305176.00152588.00076294.00038147.00019074.00009537
360.180.90.45.22.511.255.6252.81251.40625.703125.3515625.1757813.0878906.0439453.0219727.0109863.0054932.0027466.0013733.0006866.0003433
21,600.10,800.5,400.2,700.1,350.
675.337.5168.7584.37542.187521.0937510.546885.273442.636821.31836.65918.32959.16479.08240.04120.02060
296,000.648,000.324,000.162,000.81,000.40,500.20,250.10,125.5,062.52,531.251,265.6250
632.8125316.4063158.203179.101639.550819.77549.88774.94382.47191.2360
01234567891011121314151617181920
6.283185313.141592651.57079633.78539816.39269908.19634954.09817477.04908739.02454369.01227185.00613592.00306796.00153398.00076699.00038350.00019175.00009587.00004794.00002397.00001199.00000599
Table 2.2. Binary Angle Relationships
37
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
SYNCHROSTANDARD
PEAKSAMPLINGMODULE
STROBEVref
CHANNEL #1INPUT MODULE
CHANNEL #2INPUT MODULE
CHANNEL #3INPUT MODULE
CHANNEL #4INPUT MODULE
A
B
C
D
CENTRALCONVERTER
MSB
LSBCB
to A
to B
to C
to D
SCOTTT
DUALS/H
(SEEFIG 2.9)
MUX
TO LAMPDRIVERS
Figure 2.20. Test Configuration for Multiplexed S/D Converters.
under test and the velocity output is monitoredthrough a low-pass RC filter by a DVM. The up-downcounter is run at various rates in both directions andthe input rate is compared with the output of theDVM. Usually a PC is used to control the test andcompute the linearity, voltage scaling, full-scaleaccuracy, zero offset and direction reversal error(voltage gradient difference in clockwise and coun-terclockwise directions). This is shown in Figure2.22.
Checking acceleration is a much more difficult tasksince a steady-state acceleration is not practical.The velocity soon builds up to unreasonable levels.
Generally it is measured indirectly by determining theclosed-loop small-signal response and deriving theacceleration constant from them.
5 10 15
20 25 30 35 40 45
50 55 60 65 70
8075 85 90
MIN
UT
ES
OF
ER
RO
R
SPEC LIMIT OVER TEMP.
SPEC LIMIT OVER TEMP.
5
-5
4
-4
3
-3
2
-2
1
-10
ANGULARDEGREES
Figure 2.19. Room Temperature Error Curve.
THEORY OF OPERATION OF MODERNS/D AND R/D CONVERTERS
38
UP-DOWNCOUNTER
PRECISIONCLOCK
PRECISIOND/S
S/DUNDERTEST
DVMVEL
S1
S2
S3
PCCONTROLLER
Figure 2.22. Analog Velocity Dynamic Test Diagram.
D/SCONVERTER
S/DCONVERTER
DIGITALCOMPARATOR
0000UP-DOWNCOUNTER
CLOCK
Figure 2.21. Dynamic Test Configuration for S/D Converters.
THEORY OF OPERATION OF SYNCHRO-TO-DC CONVERTERS
Theory of Operation of Synchro- or Resolver-to-Linear DC Converters
A synchro-to-DC converter accepts 3-wire synchroinput signals (or 4-wire resolver input signals) andputs out a bipolar DC (analog) signal proportional tothe shaft angle. In general, then,
where K is the full-scale constant, typically 10 Volts,so that +10 V = 180°, -10V = -180°, and 0V = 0°.
Any of the synchro-to-digital converters describedearlier in this handbook could be converted to a syn-chro-to-DC converter by feeding its digital output to aD/A converter with appropriate input coding. This isthe recommended approach for synchro- or resolver-to-DC conversion. A typical example is illustrated inFigure 3.1.
By suitably inverting the various interface lines vari-ous code formats for the D/A can be accommodated.Additionally, system offsets and zeroing can beimplemented digitally with an adder between the twoconverters.
Some of the advantages of this technique are:
• Output DC not affected by variations in synchrovoltage or frequency. It is broadband.
• Ease of scaling.
Vout (DC) = ± Kθ180˚
• No staleness due to sampling. Use of a trackingS/D eliminates staleness.
• High reliability due to minimal part count.
• Relatively low cost.
• Noise rejection characteristics of the tracking S/Dconversion.
The circuit of Figure 3.2 shows an older techniqueused before the advent of lower cost data converters.This older method used the harmonic oscillator con-verter to produce a DC level proportional to θ.Reference to pages 29 to 30 and Figure 2.11 willshow that the design of Figure 3.2 is essentially thatof a sampling harmonic oscillator synchro-to-digitalconverter except for the output circuit. In Figure 2.11,the time interval t, between the start of oscillationand the positive-going zero crossing (Figure 2.12), isused to control the number of clock pulses gated intoa binary counter. In Figure 3.2, a precisely scaled,very linear voltage ramp, starting at -K1 Volts, isallowed to rise for the time interval t, and then"frozen" at that value. Since the value of t is given by:
where RC is the integrator time constant, and theramp voltage is given by:
where -K1 is a constant that determines full scale,then
and K is proportioned conveniently ... usually, so that
when | θ | = 360˚ | e | = 20 Volts ramp
e ramp1K RC
360˚= θ
e = K tramp 1
t = θRC360˚
39
SECTION III
S/D D/ADC
OUTPUT
S1
S2
S3
Figure 3.1. Recommended Method of ConvertingSynchro or Resolver Data to DC.
THEORY OF OPERATION OF SYNCHRO-TO-DC CONVERTERS
The "freezing" of the output is accomplished by sam-pling the ramp at the end of the harmonic oscillatorperiod, and storing the output in a sample-hold circuit(see page 29 for details), so that the output remainsessentially constant until the next measurement ismade. Since a complete conversion is made once ineach carrier cycle, the maximum possible stalenesserror is the same for this synchro-to-DC converter asit was for the circuit of Figure 2.11:
for constant velocity between samples.
Returning to the harmonic oscillator configuration ofFigure 3.2, we may note the following design con-straints of the harmonic oscillator approach:
• The uncertainty of the zero-crossing detector is afirst-order error source.
• Any zero-offset or nonlinearity in the ramp is afirst-order error source.
• Any variation in "K", the constant determining theslope of the ramp, is a first-order error source.
velocity error = velocity in degrees/second
carrier frequency
• As discussed on page 30, only converters withsome means of compensating for the inevitabledrift in the integrator time constant are capable ofreasonable accuracy. In the converter of Figure3.2, this is accomplished by checking (betweenconversions) the value of a half-period of the har-monic oscillator - which should bring the output tozero (halfway between -10V and +10V). Any off-set from zero is used to correct for time-constantdrift. Thus, the circuit is recalibrated before eachmeasurement.
Synchro/Resolver-to-Nonvariant DC Sine/CosineConverters
In many systems it is desirable to convert synchrodata to DC sine and cosine that does not vary withthe synchro reference amplitude. The preferredmethod is to use a tracking S/D and a DC coupledD/R converter as shown in Figure 3.3. In this config-uration the D/R converter reference can be the sys-tem DC reference, which is far more stable than theAC reference. The output variations are now onlydependent on the DC reference and the synchroangle. The prime source of errors in this method, asin any DC system, are offsets. These must be care-fully controlled to preserve angular integrity. Don't
40
OUTPUTRATE
SMOOTHING
SAMPLEAND
HOLD
PRECISIONRAMP
GENERATOR
TIMING&
CONTROL
ISOL.XFMR
SYNCHROREF
SYNCHROINPUT
(θ)
SCOTT TXFMR
ZEROCROSSINGDETECTOR
V1
R1
R1R1 R2
S3A S3B
S2S1
V2
C1 C2
HARMONIC OSC
-V2
Figure 3.2. Older Method of Synchro-to-DC Conversion
THEORY OF OPERATION OF SYNCHRO-TO-DC CONVERTERS
forget, at angles where the sine or cosine are at zerovolts the impact of the offset will be maximized. Thetransfer function of the S/D converter is given on thedata sheet for the particular product used while forsystem purposes the transfer function of the D/Rconverter is unity (to three decimal places).
Using this technique all the circuitry needed to com-pensate for temperature, aging of components andstaleness can be eliminated thereby reducing partscount, increasing reliability and reducing cost.
Prior to the general availability of DC-coupled D/Rconverters, the most common method of achievingsynchro-to-nonvariant DC sine/cosine conversionwas the sampling harmonic oscillator converter
shown in Figure 3.4 - a configuration that accepts 3-wire synchro data (or 4-wire resolver-format data)and puts out two analog DC levels proportional to thesine and cosine of the shaft angle sampled.Although no longer used in new designs, it is exam-ined here for its historical merit. The relationshipbetween the outputs and are:
where K is the scale factor, typically, 10 Volts.
Before examining the behavior of Figure 3.4, it wouldbe useful to consider the fact that the sampled and
e (1) = Ksin θ out
e (2) = Kcos θ out
41
DR 11525DR 11520DR 11524
or equivelantDC-
COUPLEDD/R
DCOUTPUT
S1
S2
S3
DC REFERENCE(instead of A/C OSC)
SIN
COS
RDC 19220or equivelant S/D
Example to get Synchro Signal Output to DC SIN and DC COS:
Note: This process offers least latency of data vs. doing this with a processor.
-V2
R3
R3R1 R2
S2A
S2S1
ZEROCROSSINGDETECTOR
CLOCK
CONTROL LOGIC
UP-DOWN COUNTER
S1S2S3
S/H
S/H
K sin θ
K cos θ
S2B
C1 C2B A
SCOTTT
XFMR
Vx
VyEref(Establishes K)
SWITCH CONTROL LINES
S3
+
Figure 3.3 Preferred Synchro-to-Nonvariant DC Sine/Cosine Converter.
Figure 3.4 Older Method of Synchro-to-Nonvariant DC Sine/Cosine Converter.
THEORY OF OPERATION OF SYNCHRO-TO-DC CONVERTERS
held resolver-format signals (at points A and B inFigure 3.4) are already DC signals proportional tosinθ and cosθ. Unfortunately, these signals are alsoproportional to the reference excitation, which can,and does, vary over as wide a range as ±10% inpractical systems.
Furthermore, the rotor-to-stator transfer coefficient inthe synchro or resolver itself varies from unit to unit.
In another possible "short-cut" approach, theresolver-format signals may be demodulated inphase-sensitive detectors to produce DC sine/cosineoutputs; but this configuration, while essentially freeof speed-voltage is still entirely vulnerable to varia-tions in reference excitation.
The circuit of Figure 3.4 produces nonvariantsine/cosine outputs - i.e., outputs in which the scalefactor, K, is held constant within very narrow limits,and is essentially independent of the reference exci-tation.
Once again, it would be well to review pages 29 to30, and Figure 2.11, to recall how the sampling har-monic oscillator synchro-to-digital converter works.The circuit of Figure 3.4 differs from that of Figure2.11 in three important ways:
• The digital counter is an up-down counter.
• The output is not a digital word derived from thecounter state (at the end of the time interval t), butis derived by sampling the levels at points A and Bin the circuit, and holding them for one carriercycle until the next (updated) measurement ismade.
• Additional programming logic is provided to imple-ment the up-down count behavior describedbelow.
The first phase of the conversion process is identicalto that described on pages 29 to 30, with the resultsindicated in Figure 2.12. This phase involves:strobed sampling and holding of the resolver-formatsine/cosine signals; setting the integrators to zero;applying the sampled data as initial conditions to the
42
Transducer
S/D FPGA
DAC
DAC
SIN
COS
V OUT
Bit 0 15
16 Bit
16 Bit
16Bit
Note: Using a FPGA will cause latency in process.
FPGA }
16 BitDAC
Figure 3.5. Additional Method of Synchro to DC SIN/COS
THEORY OF OPERATION OF SYNCHRO-TO-DC CONVERTERS
43
integrators; unclamping the loop; and allowing it (andthe clock-pulse counter) to run until the positive zero-crossing is reached. At the end of this phase, notethat point A is at zero (which is the condition thatstopped the counter), and point B is at maximum(cosine of zero degrees=one). Note that the actualmagnitude of the voltage at B is proportional to thereference excitation that generated the samples usedto set the initial conditions.
The second phase of the conversion, begins by set-ting point B to a new level that is independent of therotor excitation, or any other source of scale factoruncertainty. This new level is an accurately calibratedand stabilized voltage that will establish the desiredscale factor, K, in the final output. Now having estab-lished this new set of initial conditions, the loop isunclamped, and allowed to run for exactly the sametime interval as it ran in first phase ... a time intervalgenerated by allowing the counter to count down, atthe same clock-pulse rate, to zero. At this point, theloop is again clamped, and points A and B are sam-pled and held, to yield outputs that are scaled correct-
ly, and are proportional to the sine and cosine of θ ...non-variant sine/cosine outputs.
Here again, as before, the clock-pulse generatormust be phase-locked to compensate for integrator-RC drift, and there is a maximum staleness error ofone carrier cycle.
These then are a few of the techniques used to con-vert synchro data to nonvariant DC sine/cosine data.There is, of course, the method gaining in populari-ty, of using a microprocessor, a sine/cosine ROMand two D/A converters to achieve the same result.Where the microprocessor is not fully utilized this isa good approach but for designers not wishing tofurther burden it the S/D and DC-coupled D/Rmethod is recommended.
Refer to Figure 11.26 for an illustration of a syn-chro/resolver-to-DC converter using a DDC modelRDC-19220 series converter and the Burr BrownDAC 703 digital-to-analog converter.
45
THEORY OF MODERN RVDT/LVDT-TO-DIGITAL CONVERTERS
SECTION IV
Rotary and Linear Variable DifferentialTransformers
The Rotary and Linear Variable DifferentialTransformers (RVDT/LVDT) shown in Figure 4.1, areelectromechanical transducers that provide an ACanalog output that is proportional to the displace-ment of a separate movable magnetic core. Almostunknown 45 years ago, it is widely used todaybecause of its extremely accurate and repeatablenull position, even in extreme environments.
Also known as reluctance transducers, they use theratio of the reluctance of the magnetic flux path of twocoils. Since it is a ratiometric device it is relativelyinsensitive to temperature effects. Figure 4.2 is aschematic presentation of a typical RVDT/LVDT. Itconsists of a primary coil and two secondary coils sym-metrically spaced on either a cylindrical or rotary form.A separate movable magnetic core inside the coilassembly provides a path for the flux linking the coils.
When the primary coil is excited with an AC refer-ence, voltages are induced in the secondary coils.With the core placed symmetrically the flux paths to
the two secondary coils have the same reluctanceand the induced voltages are equal in magnitude. Byconnecting the coils in series the opposing output willbe at a null. When the core moves from null the fluxpaths will have different reluctance and the outputvoltages will be different. The coil toward which thecore moved will have a lower voltage. The differen-tial output is linearly proportional to the displace-ment. The phase of the output abruptly changes 180degrees as the core moves through null.
The RVDT/LVDT-to-Digital Converter operates verymuch like an R/D converter except it operates in alinear fashion as opposed to a sin/cos trigonometricfashion. DDC converters use the same custom ICwith pin programming to switch between the twomodes of operation.
The DTC-19300 block diagram shown in Figure 4.3consists of four main parts: signal input conditioning,a feedback loop (whose elements are the high accu-racy bridge, demodulator, error processor, VCO andup-down counter), a power oscillator to excite theRVDT/LVDT, and digital interface circuitry (includingvarious latches and buffers).
Figure 4.1. Rotary and Linear Variable Differential Transformers.
THEORY OF MODERN RVDT/LVDT-TO-DIGITAL CONVERTERS
46
The converter receives the difference and sum volt-ages at its inputs and internally produces a digitalposition σ which tracks the differential position λ.
A high accuracy bridge is used to compute λ – σ,where:
λ = the RVDT/LVDTs core position
σ = the digital position contained in the converter'sup-down counter.
The tracking process consists of continually adjust-ing σ to make λ – σ approach zero so that σ will rep-resent the core's position, λ.
The ratios bridge output is fed to a demodulator whoseoutput is an analog DC level proportional to λ – σ. The error processor receives its input from thedemodulator and integrates the error signal λ – σwhich then drives a voltage-controlled oscillator (VCO). Figure 4.2. LVDT Schematic. (also see Figure 1.6)
50 ns DELAY
C1
+
LVDT
14 BIT BRIDGETRANSPARENT
LATCH
14 BITU-D COUNTER
3 STATETTL BUFFER
3 STATETTL BUFFER
FULLSCALE
R2
PHASECOMP
C2
ZERO SETTIMING
REFERENCECONDITIONER
BITDETECT
DEMOD ERRORPROCESSOR
VCO
1 LSB ANTILITTERFEEDBACK
U T
DTC-19300
INHIBITTRANSPARENT
LATCH
POWERSUPPLY
CONDITIONER
INTERNALDC REF (11V)
14 BIT OUTPUTTRANSPARENT
LATCH
POWEROSCILLATOR
HIGHACCURACY
RATIO BRIDGE
ERRORAMP
10kR1
10kR5
35
SO
29
SJ
34 SG -
+
DIFF SIG
REF
SUM(REF)DIF
GAIN
S
R
33
32
25
31
36 RI
RO
V
19 OSC
21
FREQR4 22
AMPLR3
RM
20 1
EM BITS 1-6 BITS 7-14 EL
16
23A
17INH
30+5 V
+15 V27
24e
VEL26
BIT18
U
TU/D
INHQ
PROGGAINAMP
Figure 4.3. RVDT/LVDT-to-Digital Converter Block Diagram.
Functionally, the up-down counter is an incrementalintegrator. Therefore, there are two stages of inte-gration which make the converter a type II trackingservo. In type II servo, the VCO always settles to thecounting rate which makes the dλ/dt equal dσ/dtwithout lag. The output data will always be fresh andavailable as long as the maximum tracking rate of theconverter is not exceeded.
Modern RVDT/LVDT converters have output trans-parent latches and tri-state buffers for easy data
THEORY OF MODERN RVDT/LVDT-TO-DIGITAL CONVERTERS
transfer and interfacing to µP buses with the appro-priate inhibits and enables. Built-in Test (BIT) circuitsare included which will toggle when the errorexceeds about 65 LSBs.
Historically, it has been difficult to provideRVDT/LVDT-to-digital conversion without seriousdata lag whose root cause was the phase shift vari-ation with position off null. This necessitated a halfwave or full wave rectification with filter and A/Dapproach which introduced the data lag. DDC's newtracking type converters have eliminated this con-cern by using a synthesized reference to drive thedemodulator. The reference drive is derived fromand is in phase with the RVDT/LVDT signal therebyvirtually eliminating errors due to the transducersphase shift variations.
Dynamic performance and characteristics are thesame as their closely related R/D converters. Figure4.4 shows the control loop block diagram and thetransfer function, and the open-loop Bode plot isshown in Figure 4.5. Bandwidth can be determinedby the following formula:
The variables can be found on the data sheet of thespecific converter.
π=
A2BW
Since RVDT/LVDTs are not standardized in their char-acteristics, as are synchros and resolvers, the convert-ers will have to be adjusted for input gain to accommo-date the full-scale voltage of the particular type trans-ducer. Similarly, the phase shift will have to be com-pensated for. This usually requires a simple resistorand capacitor trim done once with exact proceduresgiven on the converter data sheet. As in their R/Dcounterparts, DDC's RVDT/LVDT converters have avelocity (VEL) output for stabilizing the velocity loop ofa servo, thereby eliminating the need for a tachometer.
The converter is a ratiometric device which com-pares the difference and the sum of the signal inputson the ±S and ±C. The RDC-19220 Series requires asignal input conditioner (see Figure 4.6) whereas thethe DTC-19300 contains a signal input conditioner,and is designed for phase shift compensation. Whenusing the RDC-19220, phase and amplitude mis-matches must be kept to a minimum. Adjust the gainaccordingly using the capacitors and resistors in theamplifier (signal conditioner) input to the converter.
The DDC RDC-19220 series resolver-to-digital con-verters can be made to operate as RVDT/LVDT-to-digital converters. By connecting the ResolutionControl inputs A and B to "0", "1", or the -5 volt sup-ply, the RDC-19220 functions as a ratiometric track-ing linear converter. When linear ac inputs areapplied from a LVDT, the converter operates overone quarter of its range. This results in two less bits
47
ERROR PROCESSOR
RESOLVERINPUT
(θ)
VELOCITYOUT
DIGITALPOSITIONOUT
VCOCT SA + 1 1 B
S S + 1 10B
H = 1
+
-
e A 2 S
SA + 1 B
S S + 1 10B
2
2Open-Loop Transfer Function =
Where A = A A 221
FIGURE 4.4. Transfer Function Block Diagram. FIGURE 4.5. Open loop Bode Plot.
B A
BWω (rad/sec)
THEORY OF MODERN RVDT/LVDT-TO-DIGITAL CONVERTERS
(the MSB and MSB -1) of resolution for LVDT modethan are provided in resolver mode.
Some LVDT inputs will need to be scaled to be com-patible with the converter input. Suggested compo-nents for implementing the input scaling circuit are aquad op amp, such as a 4741 type, and precisionthin-film resistors of 0.1% tolerance.
The data output of the RDC-19220 Series is binarycoded in LVDT mode. The most negative stroke ofthe LVDT is represented by ALL ZEROS and themost positive stroke of the LVDT is represented byALL ONES. The most significant 2 bits (2 MSBs)may be used as overrange indicators. Positive over-range is indicated by code "01" and negative over-range is indicated by code "11." See Table 4.1.
48
FIGURE 4.6. RDC-19220 Series Input Signal Conditioning.
1
DIGITAL OUTPUT BIT
LVDT OUTPUT
+ Over Full Scale - LSB
+ Full Travel - LSB
+ 0.5 Travel
+ 1 LSB
Null
- 1 LSB
- 0.5 Travel
- Full Travel - LSB
- Over Full Travel - LSB
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 1 X X X X X X X X X X X X X X
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 X X X X X X X X X X X X X X
Table 4.1. Digital Output Of The RDC-19220 Series In LVDT Mode
x = Don’t care.
R iS1
S3+S
-S
SIN
R f
R i
R f
R i
S2+C
-C
R /2 i
COS
A GND
CONVERTER
R i
R / 3 f
R / 3 f
-
+
-
+
49
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
The Programmed-Function Generator Digital-to-Synchro/Resolver Converter
Figure 5.1 is a general block diagram that will serveto introduce the many different implementations ofboth Digital-to-Synchro (D/S) and Digital-to-Resolver(D/R) converters. As indicated, the input to a D/S orD/R converter is a set of digitally coded “logic level”(ONES and ZEROES) presenting the shaft angle, θ,to some number of bits of resolution. As explained inSection I, when natural binary coding is used themost-significant bits of this input “word” representrespectively: 180°, 90°, 45°, etc. Thus, an input wordbeginning 11....etc. designates an angle in the fourthquadrant, a word beginning 10.....etc., designates anangle in the third quadrant, a word beginning01.....etc. designates an angle in the second quad-rant, and a word beginning 00.....etc. designates anangle in the first quadrant. Clearly, then, the first twomost-significant bits of any pure binary-coded wordare the quadrant-designating bits. (The first three, bysimilar reasoning, are the octant-designating bits.)
The remaining (less-significant) bits of the digitalword determine the angle precisely by adding (to thecardinal quadrant value) some value between 0° (allZEROES) and 90° (all ONES). If we have set asidethe first three bits, for octant designation, the remain-
ing bits designate an angle between 0° and 45°. Byconverting these bits into analog levels correspond-ing to the sine and cosine of that angle (which lies,as we have noted, between 0° and 90°), we may thenuse the quadrant-designating bits to establish theappropriate polarity for these analog levels, in accor-dance with the following identities:
sin θ (2nd quadrant) = cos (θ-90°)
sin θ (3rd quadrant) = -sin (θ-180°)
sin θ (4th quadrant) = -cos (θ-270°)
cos θ (2nd quadrant) = -sin (θ-90°)
cos θ (3rd quadrant) = -cos (θ-180°)
cos θ (4th quadrant) = sin (θ-270°)
The application of these identities may be more read-ily seen by examination of the following table:
If first two MSB’sare:
Then polarity ofsinθ is:
and polarity ofcosθ is:
11100100
negativenegativepositivepositive
positivenegativenegativepositive
Table 5.1. Quadrant Designation
POWERAMPLIFIER
(OPTIONAL)SCOTT-T
XFMR
FUNCTIONGENERATION
QUADRANTSELECTOR
MSB
DIGITALINPUTWORD
LSB
Vref
sin θ
sin
cos θ
cos
RESOLVER FORMATOUTPUTS
SYNCHRO FORMATOUTPUTS
Figure 5.1. Basic Digital-to-Synchro/ResolverConverter.
SECTION V
A very similar table may be made for octant-desig-nation schemes, in which the first three MSB’s deter-mine, not only the polarity of the analog level repre-senting the sine and cosine of, but also which of twoavailable values shall be called the sine, and whichshall be called the cosine. This need to selectbetween two available values arises from the trigono-metric identity:
sin θ = cos (90°-θ) for θ in the first quadrant.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
Thus, if we have translated all but the first threeMSB’s into two analog voltages:
then the following table can be used to operate VAand VB so as to create the correct analog sine/cosinepolarities:
V = sin θ (where 0 < θ < 45˚) A
and V = cos θ (where 0 < θ < 45˚) B
equal carrier frequency sine waves of oppositephase. After quadrant selection, they are fed to theinputs of the function generators. (Note that byappropriate phasing, both function generators mayactually be sine multipliers - but it will be simpler,perhaps, to think of them as sine and cosine multi-pliers, as in the discussions above.)
The outputs of the function generators are, then,accurate, resolver-format signals:
All that remains for D/R conversion is to provide suf-ficient amplification (and, if necessary, isolation) todrive a resolver. These power-output stages aredescribed later in this section.
For D/S conversion, an additional step is required:the use of a “reversed” Scott-T transformer (seeFigure 5.1) to convert from 4-wire resolver format to3-wire synchro format. As indicated in the diagram,the power amplifiers are interposed between theScott-T and the multipliers.
The design constraints of this circuit are clearlyfocused on the function generators and the poweramplifiers, since everything else in the device is alogic circuit, it is not a major design concern.Subsequent discussions will cover these constraints.
Types of Function Generators
Figure 5.2 shows four types of circuits currently usedfor multiplying a reference (carrier) signal by the sineor cosine of a digital angle (θ):
• Figure 5.2a applies the reference carrier to a multi-section, multi-tapped ratio transformer, and useselectronic switches to select non-linear spaced tapscorresponding to the desired input/output ratio - i.e.,the ratio that corresponds to the sine (or cosine) ofthe digitally coded angle. This is a precise andextremely stable way of obtaining sine/cosine D/A
V = K cos θ sin ωt x
V = K sin θ sin ωt y
where K sin ωt is the carrier envelope
50
First 3 MSB’s Sin θ Cos θ
111110101100011010001000
-VA-VB-VB-VA+VA+VB+VB+VA
+VA+VA-VA-VB-VB-VA+VA+VB
Table 5.2. Octant Designation
Clearly, then, by routing the first two (or first three)most significant bits to a simple set of polarity/signalselector logic circuits, we may reduce our problem totrigonometric D/A conversion in only one quadrant(or octant). That is what we have done in Figure 5.1,in which the first two MSB’s are diverted to a quad-rant selector circuit, and the remaining bits are usedto program 0°-90° sine and cosine function genera-tors. These generators may be described as nonlin-ear, bipolar, multiplying D/A converters, in which thereference input signal is the carrier wave (Eref), andthe transfer function is either
EA = Eref sinθ (sine function generator)
or EB = Eref cosθ (cosine function generator)
where θ is the angle represented by the digital input.
NOTE: the specific design of these function generatorsis perhaps one of the most widely discussed topics inthe synchro conversion field, but we shall reserve dis-cussion of that subject until later in this section.
The reference voltage supplied to the D/S converteris generally buffer-isolated, and converted into two
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
multiplication, but it is also the most expensive,largest, and heaviest. It is most likely undesirable toproduce switching transients, and second ordererrors due to reference harmonics.
• Figure 5.2b is a variation of the tapped-ratio-trans-former technique of Figure 5.2a, but with resistorratio sets substituted for the transformer(s) thatsynthesize less-significant-bit increments whichare less critical as to both accuracy and stability.This circuit is less precise and somewhat less sta-ble, but also somewhat lower in cost, size, andweight compared to the all-transformer approachof figure 5.2a. It retains its sensitivity to error pro-duced by reference harmonics.
• Figure 5.2c applies the reference signal to a resis-tor-ratio network, electronically switched inresponse to the digitally coded input. The resis-tors are “weighted” in exactly the same way as thetaps in the tapped-transformer function generator
of Figure 5.2a, so as to create the sine (or cosine)function. This technique can be made to approachthe precision of the tapped-transformer design byusing modern nichrome-film or (non-inductive)wire-wound resistors, and has entirely satisfactoryaccuracy and stability for one minute or even moredemanding applications...at a small fraction of the
51
VrefINPUT
DIGITAL INPUT
OUTPUT
Figure 5.2a. Tapped-Ratio-Transformer Function Generator (greatly simplified).
VrefINPUT
DIGITAL INPUT
OUTPUT
Figure 5.2b. Hybrid (Transformer/Resistor Network)Function Generator (greatly simplified).
VrefINPUT
DIGITAL INPUT
OUTPUT
Figure 5.2c. Weighted Resistor-Network FunctionGenerator (simplified).
VrefINPUT
DIGITAL INPUT
OUTPUT
etc.
Figure 5.2d. Linear/Selectively-Loaded Resistor-Network Function Generator (simplified).
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
cost, size, and weight. Reference-harmonic effectsare negligible.
• Figure 5.2d is by far the most economical, small-est, lightest, and simplest means of generating thesine/cosine D/A multiplication. It uses a linearresistor network, but achieves its sine or cosinefunction non-linearity by selective loading of theoutput of the ratio divider. For two minute long-term accuracy over wide temperature ranges, thisapproach has proved to be the logical choice,because of its simplicity and economy. In the past,this approach was optimized for angular accuracyand as such had one characteristic that restrictedits usefulness in some applications. It exhibited ascale factor variation as it generated the sine orcosine function. Since the angle information is theratio of the sine/cosine outputs, and the scale fac-tor variations of the two function generators trackeach other, no appreciable angular error is intro-duced. However, the absolute amplitudes variedand some corrective measure, or some alternateapproach, was required for applications like vector(polar-coordinate) plotting.
The Stored-Table-Look-up Digital-To-Synchro orDigital-To-Resolver Converter
An alternative approach to generating synchro orresolver analog signals is to use a ROM look-uptable with sine/cosine functions. The output of theROM can then be fed to two appropriately scaledfour-quadrant multiplying D/A converters using theAC reference for the analog channel input.
The major disadvantages of this approach are theburden on the µP and the number of componentsneeded to implement it compared to a dedicatedD/S. Modern D/S hybrids have double-bufferedinputs and fully protected outputs of up to 5 VA.
Output Circuits for D/S and D/R Converters
The resolver-format (sine/cosine) outputs producedby all of the foregoing D/S and D/R converters arelow-energy, relatively low-voltage signals. The ampli-fiers required to increase the power and voltage lev-
els of these signals must have the following charac-teristics:
• Relatively low output impedance - low enough todrive either a resolver winding or a “reversed”Scott-T reflecting the load of a synchro, efficientlyand rapidly, without significant distortion, and inthe presence of reactive loading.
• High linearity - under the load conditionsdescribed above, to prevent the introduction ofharmonics.
• High Efficiency.
• Minimum (and closely controlled) phase shift -again, under the load conditions described above,so that angular error is not introduced. Note that itis not necessary to achieve negligible phase shift,but merely to make the phase shifts of the twopower amplifiers (sine and cosine) identical. Inother words, any differential phase shift betweenthe two channels must be minimized.
• The ability to absorb (and dissipate) energy overthat part of the voltage-output cycle in which thereactive nature of the load pumps energy backinto the amplifier.
• Short-circuit protection and output over-voltageprotection.
The Scott-T transformer used in D/S converters tochange resolver-format signals into synchro-formatsignals at high power levels must be capable of han-dling the relatively high input voltage swings, atthose power levels, without saturation or significantdistortion. Its phase shift should be low, and (evenmore important) it must be balanced, so that differ-ential phase shifts do not create significant angularerrors. For best performance, then, this transformershould have low leakage reactance, and low prima-ry-to-secondary stray capacitance. For efficiency,the core and copper losses should be minimized.
The transfer function, for system considerations, ofmodern D/S or D/R converters is unity.
52
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
Some System Considerations
• Power surge at turn-on - When power is initiallyapplied, the output power stages can go fully onbefore all the supplies stabilize. Current limitingprevents damage, but when multiple D/S convert-ers with substantial loads are present, the heavyload can cause the power supply to have difficultycoming up and indeed may even shut down. It isbest then to be sure the supply can handle theturn-on surge or to stagger the D/S turn-ons sothat the supply can handle it. Typically, the surgewill be twice the maximum rated draw of the con-verter.
• Torque load management - When multiple torqueloads (TR) are being driven the above problems areexacerbated by the high power levels involved andpower supply fold back problems are commonunless the stagger technique is used. Also allowtime for the loads to stabilize. On turn-on it is notlikely that all the output loads will be at the sameangle as the D/S output. As the angular differenceincreases so does the power draw until the differ-ence is 180 degrees. At this point, the load imped-ance drops to Zss and current draw is at maximum.
• Pulsating power supplies - The new generationof D/S and D/R converters has been designed tooperate their output power stages with pulsatingpower to reduce power dissipation and power
demand from regulated supplies. Figures 5.3 and5.4 illustrate this technique. Essentially the poweroutput stage is only supplied with enough instan-taneous voltage to be able to drive the requiredinstantaneous signal level. Since the output signalis required to be in phase with the AC reference,the AC reference can be full-wave rectified andapplied to the push-pull type output drivers. Thesupply voltage will then be just a few volts morethan the signal being output, and internal powerdissipation is minimized.
Thermal Considerations
Power dissipation in D/S and D/R circuits are depen-dent on the load whether active (TR) or passive (CTor CDX), and the power supply, whether DC or pul-sating. With inductive loads we must bear in mindthat virtually all the power consumed will have to bedissipated in the output amplifiers. This sometimesrequires considerable care in heat sinking.
For illustrative purposes, let’s examine a typicalhybrid power D/S, DDC’s DSC-10510, capable of 5VA drive.
Let us take the simplest case first: PassiveInductive Load and ±15 Volt DC power stage sup-plies (as shown in figure 5.3). The power dissipat-
53
+v
- v
+DC SUPPLY LEVEL
-DC SUPPLY LEVEL
POSITIVE PULSATINGSUPPLY VOLTAGE
NEGATIVE PULSATINGSUPPLY VOLTAGE
AMPLIFIER OUTPUTVOLTAGE ENVELOPE
Figure 5.4. Pulsating Power Supply Waveforms.
REFERENCESOURCE
26V rms 400Hz
1
2
3
4
5
6
7
3.4V rms
21.6V rmsC.T.
D1 D2
D3D4
C1
C2
+
+
RL' RH'
+V
GND
-V
S1
S2
S3
DIGITALINPUT
±15VDC
DSC10510
S1
S1'
S2
S2'
S3
S3'
T1
42359
NOTES: PARTS LIST FOR 400Hz D1, D2, D3, D4 = 1N4245 C1 AND C2 = 47µF, 35V DC CAPACITOR
Figure 5.3. Typical Connection Diagram UtilizingPulsating Power Source.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
ed in the power stage can be calculated by taking theintegral of the instantaneous current multiplied by thevoltage difference from the DC supply that suppliesthe current and the instantaneous output voltageover one cycle of the reference. For an inductiveload this is a rather tedious calculation. Instead letus take the difference between the power input fromthe DC supplies minus the power delivered to theload. A real synchro load is highly inductive with a Qof 4-6; therefore, let’s assume that it is purely reac-tive. The power out, then, is 0 Watts. As a worstcase we will also assume the load is the full 5.0 VA,the converter’ s rated load. The VA delivered to theload is independent of the angle but the voltageacross the synchro varies with the angle from a highof 11.8 Volts line-to-line (L-L) to a low of 10.2 V L-L.The maximum current therefore is:
The output is L-L push-pull, that is, all the currentflows from the positive supply out to the load andback to the negative supply. The power input is theDC voltage times the average current or:
The power dissipated by the output driver stage isover 13 Watts shared by the six power transistors.Since one synchro line supplies all the current whilethe other two share it equally, one will dissipate 2/3of the power and the other two will each dissipate1/3. There are two transistors per power stage soeach of the two transistors dissipates 1/3 of thepower and each of the other transistors dissipates1/6 of the power. This results in a maximum power inany one transistor of:
• 13.24 W = 4.41 Watts13
= 13.24 Watts.7070.49 A • 0.635 avg
rms[ ] [ ]30 V •
= 0.49 A rms10.2 V5 VA
The heat rise from the junction to the outside of thepackage, assuming a thermal impedance of 4degrees C per watt, is:
At an operating case temperature of +125°C themaximum junction temperature will be 142.65°C.
The other extreme condition to consider is when theoutput voltage is 11.8. The current then will be .42 Aand the power will be
A similar calculation will show the maximum powerper transistor to be 2.3 Watts. Much less than theother extreme.
For Pulsating Supplies, the analysis is much moredifficult. Theoretical calculations, for a purely reac-tive load with DC supplies equal to the output voltagepeak vs. pulsating supplies with a supply voltageequal to the output voltage yield an exact halving ofthe power dissipated. The practical circuit alsoresults in halving of the power dissipated. At lightloads the pulsating supplies approximate DC sup-plies and at heavy loads, which is the worst case, theyapproximate a pulsating supply as shown in figure 5.5.Advantages of the pulsating supply technique are:
• Reduced load on the regulated ±15 VDC supplies.
• Halving of the total power.
• Simplified power dissipation management.
30 • [ 0.42 A • ] = 11.32 Watts0.6350.707
4.41 W • 4˚C / W = 17.65˚C
54
+15VDC
-15VDC
LIGHT LOAD
HEAVY LOAD
Figure 5.5. Loaded Waveforms.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
Active Load - that is torque receivers - make it moredifficult to calculate power dissipation. The load iscomposed of an active part and a passive part.Figure 5.6 illustrates the equivalent two-wire circuit.At null, when the torque receiver’s shaft rotates to theangle that minimizes the current in R2, the power dis-sipated is lowest. The typical ratio of Zso/Zss=4.3.For the maximum specified load of Zss=2 ohms, theZso=2 x 4.3=8.6 ohms. Also the typical ratio ofR2/R1=2. In all synchro systems (torque transmitterdriving a torque receiver) the actual line impedancesare as shown in Figure 5.7. The torque transmitterand torque receiver are electrically identical, hencethe total line impedance is double that of Figure 5.6.The torque system is designed to operate that way.The higher the total line impedances, the lower the cur-rent flow at null and the lower the power dissipation. Itis recommended that with torque loads, discrete resis-tors be used as shown in Figure 5.8 and 5.9.
A torque load is usually at null. Once the torquereceiver nulls at power turn on, the digital commandsto the D/S are usually in small angular steps, so thetorque system is always at or near null. Large digitalsteps, load disturbances, a stuck torque receiver orone synchro line open causes an off null condition.
Theoretically, at null the load current could be zero(see Figure 5.10). If Vac = Vbc, both in magnitudeand phase, then, when “a” was connected to “b”, nocurrent would flow. Pick C1 and C2 to match thephase lead of R1-Zso. In practice this ideal situationis not realized. The input-to-output transformationratio of torque receivers are specified at 2% and the
turns ratio at 0.4%. The in-phase current flow due tothis nominal output voltage (10.2 V) multiplied by the% error (2.4/100) divided by total resistance (4 ohms)= 61 mA. A phase lead mismatch between the torquereceiver and the converter of 1 degree results in aquadrature current of:
Total current is the phaser sum:
Since this is a light load condition, even pulsatingsupplies would be approximating DC supplies.
The off null condition is a different story. Real syn-chros have no current limiting, so that the current thatwould flow would be the current that the circuit con-ditions demanded. The worst case would be for a180 degree error between the two synchros asshown in Figure 5.11. For this condition the twoequivalent voltage sources would be 10.2 V oppos-ing. The current would be
= 5.1 A in phase10.2 • 24
30 Vdc • 75.5 mA • 0.9 (avg/rms) = 2.04 Watts
Power dissipation is:
61 + 44.5 mA = 75.5 mA
10.2 V • = 44.5 mAsin 1˚4 ohms
55
REF IN D/S
R2=1 1/3Ω R1=2/3Ω
REF≈ ZSO=8.6Ω
NOTES: R1 + R2 ≈ ZSS
3-WIRE SYNCHRO 2-WIRE REF
ACTIVE LOAD
Figure 5.6. Equivalent Two-Wire Circuit.
R1 R2 R1R2
REF REF
TORQUE TRANSMITTER TORQUE RECEIVER
Figure 5.7. Torque System.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
The power dissipated in the converter is the powersupplied by the ±15 VDC supplies minus the powerdelivered to the load.
This would require a large power supply and highwattage resistors. The converter output current isusually limited (in the case of the DSC-10510, to 0.8 Apeak).This limits the power supply to more reasonablevalues but introduces another problem - the torquereceiver can become disoriented and confused, hang-ing up in a continuous current limited condition at afalse stable null. Fortunately the DSC-10510 has spe-
(30 V • 5.1 A • 0.9) – (10.2 V • 5.1 A)= 85.7 Watts for DC supplies
cial circuits that sense this continuous current over-load condition and sends a momentary 45° “kick” tothe torque receiver thus knocking it off the false null.The torque receiver will then swing to the correctangle and properly null. If the torque receiver is stuckit will not be able to eliminate the over-current condi-tion. In this case, the converter will send a BIT signalwhen the case exceeds 140°C. This BIT signal can beused to shut down the output power stage.
An additional advantage of using pulsating powersupplies is that the loss of reference when drivingtorque loads is fail safe. The load will pump up the±V voltages through the power stage clamp diodesand the loss of the reference detector will disable thepower stage. The power stage will, therefore, be
56
REF IN
RH
RL
D/S
2Ω 1 1/3Ω 2/3Ω
ZSO=8.6Ω REF
TORQUE LOAD WITH DISCRETE EXTERNAL RESISTOR
Figure 5.8. D/S Equivalent.
1.33Ω
1.33Ω
1.33Ω
S1
S2
S3
RH
RL
S1
S2
S3
D/S TRREF IN REF
Figure 5.9. D/S Actual Hook-up.
2Ω
RH
RL
A
D/S
1 1/3Ω 2/3Ω
REFZso=8.6Ω
B
C
REF IN
C1
C2
R1
Figure 5.10. Ideal Null Condition.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
turned off with the needed power supply voltages.The pulsating power supply diodes will isolate thepumped up pulsating supplies from the reference. Ifthe DC power supplies are to be used for the powerstage and there is a possibility of the DC suppliesbeing off while the reference to the torque receiver ison, then the protection circuitry shown in Figure 5.12is highly recommended.
A note should be made here about the ability ofDDC’s synchro booster amplifiers to drive activeloads with impedance well below that implied by theirVA rating. A case in point being the SBA-25000series amplifiers. Rated at 25 VA these units areable to drive active loads as low as 6 Ohms at 90 VL-L. On the surface this seems to be inconsistent. Inactuality it is not. When a torque receiver or anotheractive load device is at null the impedance is muchhigher than the Zss. It is only in the off-null conditionthat Zss can be as low as 6 Ohms. The off-null con-
dition is normally a transient condition, only existingfor a second or so. During this time the amplifier out-put operates in a non-linear manner; it goes into cur-rent limiting. At this current-limited output level it willproduce sufficient power to drive the torque receiverto null but not enough to damage itself. As the torquereceiver comes into null it’s impedance increasesand the amplifier will come out of current limiting andoperate normally. Should the load remain at a lowlevel and the amplifier be forced to remain in currentlimiting for more than 4 seconds or so the SBA-25000 will introduce a 1/2 second angle change(120°) to try to free the torque receiver. Should theload persist the output driver temperature will rise to+125°C at which point the thermal cut-out will disablethe output drivers.
The remote sense feature is incorporated in DDC’snewest hybrid digital-to-synchro converters. Ratedat 5 VA, the DSC-10510 offers accuracies to ±2
57
2Ω
D/S
2Ω
10.2V
+15V
10.2V
- 15V
Figure 5.11. Worst Case 180° Error.
D/S
+V
-V
+
-V
+15VDC
-15VDC
Figure 5.12. Protection Circuitry.
D/R
D/R
PA
PA
REF OUT
OUT
WITHOUT XFMR
WITH XFMR
STABILIZINGNETWORK
PRECISIONXFORMER
POWERXFORMER
REF
Figure 5.13. Feedback Transformer.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
minutes of arc at the load. This remote sense fea-ture operates just as other precision sources do. Aseparate line is run to each leg of the synchro (inaddition to the drive line) to sense the voltage actu-ally appearing on the load. This is then used to reg-ulate the output based on load voltage rather thanconverter output voltage. This feature is very usefulin driving heavy passive loads in precision systems.
Another technique sometimes used to reduce thesize and cost of the output isolation transformers isto incorporate an additional output feedback trans-former (as shown in Figure 5.13) to feed the outputback to the output drivers in such a way that the out-put power transformer is inside the feedback loop,thus allowing the transformer parameters to varyconsiderably without degrading accuracy or drivecapability. Thus the output power transformers aresimple power transformers, not large precision trans-formers, and only the small feedback transformersneed be precise. This technique requires carefuldesign since there are now two transformers withinthe loop where before there were none.
Tuning The Load
Figure 5.14 shows how to accommodate a D/S con-verter to low impedance loads - such as several syn-chro control transformers (CT) in parallel - eventhough the converter is not designed to drive such alow impedance. Since the synchro CT presents ahighly inductive impedance, of moderately high Q, itis possible to resonate each winding, with a parallelcapacitor of suitable current rating, and thereby raisethe equivalent impedance by a factor approaching Q.
NOTE: capacitor tolerance and drift, as well as thetolerance and drift of the inductance of the winding,make it impractical to attain or maintain perfect reso-nance; therefore, it is wise to estimate no greaterimpedance rise than about 0.8 Q, even using rela-tively stable capacitors.
Computing Value of Capacitor for TuningSynchro Stator Windings
Where:
C=Tuning capacitor in farads in delta connection.
X’LSO=Reactive component of impedance of one sta-tor winding leg with rotor open circuit.
f=Frequency in Hz
R’SO=Resistive component of impedance of one sta-tor winding leg with rotor open circuit.
Z' = ( Z )SO23 SO
Z = Stator winding impedance with rotor open circuit.
SO
Z' = per leg winding impedance with rotor open circuit.
SO
Note:
C = X'LSO
6 π f [(R' ) + (X' ) ]SO LSO22
58
Figure 5.14. Resonating Paralled or other Low-Impedance Loads, to Raise Drive Capabilities of a D/S (orD/R) Converter.
CTCT CT
C
CCD/S
CONVERTER(INCLUDING
REQ'DAMPLIFIERS)
FOR "N" PARALLEL CT'S,
C ≈ WHERE ω = 2π (carrier frequency) N
ω2L
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
Figure 5.15 shows the use of external synchro driverdifferential operational amplifiers to boost both theaverage and the peak power capabilities of a D/Rconverter. (The same amplifiers may be used toboost the output capabilities of D/S, synchro-to-dcand synchro-to-sine/cosine dc converters). Modernsynchro-drive amplifiers are generally available withoutput voltage ranges up to ±150 Volts, at volt-ampere levels as high as ±35 VA. They are espe-cially well suited to driving multiple resolvers.
It is important to note that not all high power ampli-fiers are suitable for use as synchro drivers becauseof the lower power factor of the load. In driving ahighly inductive load, most of the real power must bedissipated in the amplifier, since the current levelsand phase shifts can be quite high. Another impor-tant consideration is overload protection and/or cur-rent limiting. If a synchro torque receiver (TR) locksup at 180° from the D/S converter angle, the TRessentially acts as a generator aiding the D/S con-verter output rather than bucking it as it does in nor-mal operation. In this situation the amplifier will becalled upon to drive the resistive portion of the TR’simpedance (ZSO) and to absorb an additional equalcurrent from the TR. Some form of protection is verydesirable in this situation to prevent burning out theamplifiers and/or synchro.
Figure 5.16 shows how two external power amplifiersmay be used to drive one or more three-wire synchroreceivers in parallel (or a high-power torque syn-chro). This is possible because of the Y-connectionconfiguration of the synchro receiver stator windings.It can be shown that supplying the high-level energy
to two of the three input lines, and directly connect-ing the third (ground is the common connection) isjust as effective as using three power boosters. Oneword of caution: do not allow the ground-return cur-rent from the third terminal to flow through any of thelow-level analog-circuit ground paths - e.g., the ±15V power-supply common. Instead, connect the thirdsynchro input directly to the third output terminal onthe D/S converter, and ground that third output ter-minal to common.
Testing D/S Converters
To test or evaluate a digital-to-synchro converter willgenerally require a synchro bridge or a synchro angleindicator. Testing D/S converters is similar to testingS/D converters except that the inputs and outputs arereversed. The inputs are toggle switches, and the out-put is monitored or measured by means of a synchroangle indicator or a synchro bridge and phase anglevoltmeter (PAV). As shown in Figure 5.17, bit switch-es are set to obtain the desired angle, and the outputis read off the angle indicator. If the bridge and PAVtechnique is used, the bridge is adjusted for a null onthe PAV and the output angle is read on the bridge.
Most D/S converters have guaranteed angular errors(generally on the order of ±4’ and up to ±1’ ). This erroris defined as the difference between the selected inputangle and tan-1 [K(θ) sin θ / K (θ) cos θ]. K (θ) is ascale factor variation in the output amplitude, general-ly 7% for older converters and on the order of 0.1% forthe new generation. The sine and cosine outputs ofolder converters should not be demodulated and usedseparately to display circles on a CRT because the 7%
59
Figure 5.15. Boosting Output of D/R Converter.Figure 5.16. Using Two Power Amplifiers to Drive a
Three-Wire Synchro from a D/S Converter.
D/RCONVERTER
MULITIPLERESOLVERS
Vx
Vy
–
–
+
+
10K10K
10K
10K
D/SCONVERTER
TORQUE SYNCHRO
Vref
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
variation in scale factor will cause distortions in the cir-cle tending to make it diamond shaped. This general-ly is of no consequence in other applications sinceangular accuracy is the important parameter. Thepractical effect of this variation is slightly increased cir-culating currents in some applications.
How to Calculate Power Requirements for D/SConverters
Before a D/S converter can be selected for a particularapplication, the power required by the load (expressedin volt-amperes, or VA) must be determined. Most ofthe time, this must be calculated from other availableinformation, such as the type of load (e.g., 23CT4c) orthe impedance of the load (e.g., 1230 + j14300).
Enough information must be available to allow theuser to determine Zso for control transformer loadsor Zss for torque receiver loads, since this plus theRMS line-to-line voltage is all that is needed to cal-culate the required power. Zso is the impedancebetween one of the three stator terminals of the syn-chro load and the other two shorted together with therotor open, while Zss is the same impedance but withthe two rotor terminals shorted, as shown in Figure5.18. Each leg of the synchro has an impedance ofZso or Zss. Zso is used for control transformer typeloads since, in actual use the rotor sees a very highimpedance, while Zss is used for torque receiver
type loads, since their rotors are usually driven froma very low impedance generator. From Figure 5.18we can see that in the equation:
where Zs is either Zso or Zss depending on the typeof load.
Zs = Z ’s +
32
Z ’s2
= Z ’s
23
Z ’s = Z ’s
60
Figure 5.17. Testing D/S (or D/R) Converters.
STABLEOSCILLATOR
D/SCONVERTER
UNDERTEST
MSB
ONELEVEL
ANGLEINDICATOR
ORPAV
CT LOAD
Vref
OUTPUT
+
S1 S1
R1 R1
S3 S3
S2 S2
R2 R2
Z′SO
Z′SO
Z′SO
ZSO ZSS
Z′SS
Z′SS
Z′SS
Figure 5.18. Illustration of ZSO and ZSS - SynchroLoad Impedance.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
Referring now to Figure 5.19, we show the output sec-tion of a D/S converter, with the sine and cosine voltagesconnected to the load through a Scott-T transformer.
The impedance Zsin seen by the sine voltage isdetermined by drawing the Thevenin equivalent cir-cuit of Figure 5.19 with the cosine channel shorted.See Figure 5.20.
Similarly, we redraw Figure 5.19 to determine Zcos,this time with each half of sine transformer shorted.See Figure 5.21.
The impedance, Zcos is:
Since Zsin = Zcos = 2 Z’s, we can substitute this inequation 2:
Zcos = + Z ’s1N
Z ’s22
= 123
2√[ ]
32
[ ] Z ’s
= 43
32
Z ’s[ ] Zcos = 2 Z ’s
Zsin = 2 Z ’s
The impedance, Zsin is:
Notice that total power does not vary with angle.Now substitute Zs for Z’s from equation 1:
This is the equation to remember when calculatingpower from either Zso or Zss. As an aid, Table 5.3lists the power required by many common controltransformers (CT) and torque receivers (TR). Table
2VL-L
2 [ Zs ]23
34
V Zs
L-L2 = Total RMS Power (VA)•
(V sin θ)2 Z ’sL-L (V cos θ)
2 Z ’sL-L+ = Total RMS Power
2 2
V 2 Z ’s
L-L 2(sin θ + cos θ) = Total RMS Power22
61
VLL SIN θ
1:1S1
S3
S2
Z's
Z's
Z's
VLL COS θ
1 : 32
Figure 5.19. D/S Converter Output Connected toLoad Through a Scott-T.
Zcos
COS θ
1: 3/2
S1
S3
Z's
Z's
Z's
S2
Figure 5.21. Thevenin Equivalent of D/S Circuit in Figure 5.19 with Each Half of the
Sine Transformer Shorted.
Zsin
S1
S3
Z's
Z's
Z's
S2CT
CTSIN θ
1=0
1:1
Figure 5.20. Thevenin Equivalent of D/S Circuit inFigure 5.19 with the Cosine Shorted.
THEORY OF OPERATION OF MODERN DIGITAL-TO-SYNCHRO/RESOLVER CONVERTERS
5.4 gives the power capability of all our standard D/Sconverters.
Finally, a word of caution. Torque receiver loads, asdiscussed here, are assumed to be at a null, or stat-ic. When off null, or moving, they draw large surgesof power because their rotor is also being driven.Therefore, verify that the minimum Zss is not lessthan that given in Table 5.4 for the converter youhave in mind.
Example: DSC 644-H
At 400 Hz the DSC 644 will drive a minimum load of4kΩ.
34
904000
2 = 1.5 VA•
62
TYPE FREQUENCY(HZ)
VL-L ZSO OR ZSS ZSO ORZSS (ΩΩ))
POWER(VA)
Control Transformers26 V 08CT4c26 V 08CT4d115 V 11CT4e115 V 15CT4c115 V 15CT6d115 V 18CT4c115 V 18CT6d115 V 23CT4c115 V 23CT6d
400400400400604006040060
11.89090909090909090
100 + j50620 + j128
700 + j49001020 + j83301140 + j6240
1360 + j126001690 + j4800
1230 + j143001380 + j4790
516130
495083926343
126705089
143504985
0.20.8
1.230.720.960.481.190.421.22
Torque Receivers26 V 11TR4b115 V 11TR4b115 V 15TR4c115 V 15TR6a115 V 18TR4b
40040040060400
11.890909090
3.3 + j1.3191 + j7648 + j33
509 + j10612 + j12
3.520658
52017
29.829.510511.7360
Table 5.3. Control Transformers and Torque Receiver Parameters.
MODEL RESOLUTION(BITS)
ACCURACY(MINUTES)
OUTPUT DRIVEPACKAGE
DSC-11520 16 ± 1 2 ma 36-pin DDIP
DSC-11522* 16 ± 1 2 ma 36-pin DDIP
DSC-11524* 16 ± 2 15 ma 36-pin DDIP
DRC-10520 16 ± 1 2 V/A 32-pin DDIP
DSC-10510 16 ± 2 7 V/A 40-pin DDIP
DSC-644 14 ± 4 1.5 V/A 2.6 x 3.1 x 0.5 inch module
DSC-644 14 ± 4 4.5 V/A 2.6 x 3.1 x 0.8inch module
DR-11525* 16 ± 1 2 ma 36-pin DDIP
DR-11800 16 ± 1 2 ma 1.0 x 1.0 x 0.21inch
DS-11802 16 ± 1 2 ma 0.6 x 1.4 x 0.2inch
Table 5.4. Digital-To-Synchro/Resolver (D/S, D/R) Converters.
* Two Channel Device.
63
OTHER FUNCTIONS AND INSTRUMENTS
Figure 6.1a. Solid-State Control Transformer (SSCT).
SECTION VI
Solid-State Control Transformer (SSCT)
Modern electronic-system design is generally basedon the "modular-building-block" approach, where thesystem designer interfaces predesigned (and, prefer-ably, versatile) standard modules. One such moduleis the SSCT, shown in Figure 6.1a in block diagramform. By comparing this block diagram with thetracking converter of Figure 2.1, and the diagram foran electromechanical CT of Figure 1.10b, we cansee that the SSCT preforms exactly the same func-tion as an electromechanical synchro control trans-former, and provides a large part of the circuitry usedin a tracking converter.
(Note also that the SSCT is essentially the same asthe programmed-function-generator discussed inSection V - e.g., Figure 5.1 - except that thesine/cosine outputs of the function generators aresubtracted at a differencing junction, and isolated.)
The inputs to an SSCT are a three-wire set of syn-chro-format analog signals at the carrier frequency(representing θ), and a digitally coded word (repre-
senting φ). The output is simply sin (θ-φ), which, overa small range of (θ-φ), is equal to (θ-φ). Typically theoutput may be considered equal to (θ-φ) within a fewminutes of error over a range of ±7°. Since the SSCTis always used in systems that attempt to drive (θ-φ)to null-zero, the momentary off-null errors are notsignificant.
Note that resolver-format inputs may be accommo-dated by replacing the Scott-T input transformer by asimple isolation transformer ... or, under the right sig-nal-source circuit conditions, by simply eliminatingthe input transformer.
In the past SSCTs were dedicated modules orhybrids. Today SSCT operation is a pin-programma-ble option built into the S/D (i.e., the SDC-14560Series). By simply grounding the appropriate pin(usually labeled S) the converter can be used as aSSCT. In this mode, shown in Figure 6.1b, the digi-tal output becomes a double-buffered input feedingthe up-down counter. The output is now AC Error
INPUTISOL.
SCOTT-T
OUTPUTISOL.
TRANS.
+SIN
-SIN
+COS
-COS
QUADRANTSWITCHING
COSINEMULITIPLIER
SINEMULITIPLIER
+5 -15 +15 GND
3 14
LSBMSB
DIGITAL INPUT φ
SUBTRACTINGAMP
R1
R2
SYNCHROINPUT
S1
S2
S3
1 32 14
SIN (θ - φ)OUTPUT
OTHER FUNCTIONS AND INSTRUMENTS
and the enable lines (EL and EM) and inhibit (INH)become latch control lines (LL, LM, and LA).
Electronic Control Differential Transmitter (ECDX)
Another useful module is one that performs the taskof an electromechanical CDX (synchro control differ-ential transmitter). It is apparent from the block dia-gram of Figure 6.2 that this device may be explainedalmost entirely by reference to earlier discussions.Indeed, the ECDX is nothing more than a pair ofSSCT's that share a common input transformer ...
except that the sine and cosine inputs to the lowerpair of function generators have been reversed. Thisproduces the two outputs shown, which result fromsynthesis, in the SSCT's of the two complementarytrigonometric identities:
sin θ cos φ - cos θ sin φ = sin (θ-φ)
cos θ cos φ + sin θ sin φ =cos (θ-φ)
...of which the first is the normal function of theSSCT, and the second is the complementary func-
64
Figure 6.1b. S/D in the SSCT Mode.
LOS 28
LOSS OFSIGNAL
DETECTOR
SIGNALINPUT
SIN θ
COS θ1-3SYNCHRO
INPUT
LA (INH)9
HIGH ACCURACYCONTROL
TRANSFORMER
16-BIT CTTRANSPARENT
LATCH
GAIN
SIN(θ-φ)
e
ZEROSET TIMING
DEMODULATOR
REFERENCECONDITIONER
BITDETECT
40
29
39
34
DIFFGAINOF 2
POWER SUPPLYCONDITIONER
+11V
+5.5V
REF
BIT
+15V
16-BITU-D COUNTER(SET MODE)
10 11
12-19 20-27
LM(EM) LL(EL)
9-161-8
A B
RESOLUTIONCONTROL
7 8
+15V
-15VDIGITAL ANGLE φ
e
Figure 6.2. Electronic Control Differential Transformer (ECDX).
INPUTISOL.
SCOTTT
+SIN θSIN θ–SIN θ
+COS θ COS θ
COS (θ - φ)
–COS θ
S1
S2
S3
MSB
QUADRANTSWITCHING
SCOTT-TXFMR
COSINEMULTIPLIER
COSINEMULTIPLIER
SINEMULTIPLIER
SINEMULTIPLIER
SUBTRACTOR
SUBTRACTOR
SIN (θ - φ)
1 2 3 14
θ
φ
OTHER FUNCTIONS AND INSTRUMENTS
tion. In the ECDX, accuracy is maintained over 0° to360°. This module, like all the other signal-level mod-ules that may be required to drive electromechanicalresolvers, is compatible with synchro power ampli-fiers.
Isolation and Format-Conversion Transformers
Figure 6.3 shows the equivalent schematic diagramsof both reference-coupling and Scott-T transformersof typical modern input-coupling modules. The refer-ence-coupling transformer must be designed for min-imum phase-shifts, and excellent primary-secondaryisolation, to prevent noise and signal-frequencyanomalies due to ground loops in the external sys-tem. In critical applications, the transformers mayhave to be shielded as well. Core excitation shouldbe well below saturation to prevent harmonic gener-ation due to nonlinearity, and leakage reactancemust be minimized.
The Scott-T transformer is a two-core device, ideallywithout appreciable magnetic coupling from core tocore. Electrostatic isolation from unit to unit must beequally effective to preserve the integrity of the angledata transformed. Linearity is essential. In the Scott-T configuration, perfect balance must be preservedbetween the transfer characteristics to the sine andcosine outputs, and the leakage reactance must beminimized, and balanced, to preserve high accuracy.Shielding is sometimes required, for extremely highaccuracy in adverse environments.
Signal Booster Amplifiers
Figure 6.4 shows the construction, equivalent circuit-ry, and modular packaging of a typical dual poweramplifier capable of coupling synchro- or resolver-format signals (through a suitable coupling trans-former) to a synchro. It can also be used to buffer theoutput of digital-to-sine/cosine converter. The volt-age and power levels are more than adequate todrive most synchros or resolvers, and many torquereceivers.
Signal booster amplifiers require careful heat sinkingand transient protection but are otherwise simple to
use, efficient and very rugged. Modern designsoperate their power stages off the reference therebyreducing power dissipation by 50% over a DC oper-ated amplifier. They have a disable input and a BIToutput that senses thermal overload. Current limitingprevents damage from overload and short circuitswhile voltage clamps protect again reference andload transients. The thermal cutout disables the out-put at +125°C. A new feature is a unique "kick" cir-cuit to overcome the inertia of an off null condition oftorque receivers or kick them off a false null. If anoverload exists for over 4 seconds the kick circuit will
65
S1
S2
S3
+S
-S
+CANALOG GND-C
REF HIR1
R2
Figure 6.3. Reference-Coupling and and Scott-TTransformers.
SIN
+
–
COS
+
–
Figure 6.4. Dual Power Amplifier.
OTHER FUNCTIONS AND INSTRUMENTS
shift the output 120 degrees for 1/2 second and willrepeat this kick every 4 to 5 seconds as long as theoverload persists.
When driving CT and CDX loads, the synchro boost-er amplifier must have enough steady-state powercapability to drive the Zso of the load. Zso (statorimpedance with the rotor open circuited) is mea-sured as shown in Figure 6.5.
Table 6.1 shows the load impedance of some typicalcontrol transformers and control differential transmit-ters.
Control transformers are highly inductive loads and itis possible to save power by tuning such loads.Figure 6.6 illustrates how three capacitors placedacross the legs of a CT in a delta configuration cantune the load. The correct value of the capacitanceC in farads is given by:
where f is the carrier frequency and R and X are theseries real and reactive components of Zso. Goodgrade capacitors must be used and they must beable to withstand the full AC output voltage.
When the load has been tuned more loads can bedriven in parallel because the load impedance, Z,has been increased to:
It must be remembered that if the synchro isremoved from a system that has been tuned and thetuning capacitors remain in the system they will pre-sent a very low impedance to the driving amplifierand will probably drive it into overload. See page 56for more details.
R + X R
C = L22
X4πf (R +X )
C = L
L22
66
Figure 6.5. ZSO Measurement.
S3
2/3 Zso
2/3 Zso 2/3 Zso
S1 S2
Z = R + jXso L
MILITARY TYPE NUMBER SIZE ZSO (NOMINAL)
CONTROL TRANSFORMERS:11CT4e15CT4e15CT6b18CT4c18CT6b23CT4a23CT6a
11151518182323
838 + j49551600 + j93001170 + j67801420 + j132601680 + j50401460 + j110501250 + j3980
CONTROL DIFFERENTIAL TRANSMITTERS:
11CDX4b15CDX4d15CDX6c18CDX4c18CDX6d23CDX4c23CDX6c
11151518182323
253 + j1802140 + j1000404 + j229063 + j695
521 + j160532 + j306
221 + j958
Table 6.1. Common CT and CDX LoadImpedances.
S1 S2
S3
C C
C
Figure 6.6. CT Load Tuning.
OTHER FUNCTIONS AND INSTRUMENTS
Driving Torque Receiver Loads
In addition to having enough steady state powercapability to maintain a torque receiver at null, atorque driver must have peak transient power suffi-cient to drive the torque receiver back to null. Thistransient power capability is indicated by the maxi-mum torque receiver load Zss which can be driven.Some common torque receivers and their loadimpedances are listed in Table 6.2.
Reference Oscillators
The reference oscillator shown in Figure 6.7 pro-vides AC excitation for synchro, resolvers andinductosyns in systems where an AC reference isnot readily available. It is generally pin program-mable for various common frequencies and canbe used with a wide variety of standard transduc-ers. Some have a quadrature output for induc-tosyn applications. Drive capability is in the 200mA range. They come in a hybrid or modularform.
Power-Output Transformers
Figure 6.8 shows the construction, equivalent circuit-ry, and modular packaging of a typical Scott-T outputcoupling transformer, with load parameters indicat-ed, to give some idea of the design constraints in thisclass of applications. The key features of such atransformer are:
• Low distributed capacitance shunt and interwinding.
• Low leakage reactance.
• High magnetizing inductance.
• Low core and copper losses.
• Low static regulation.
• Low flux density - well below the saturation kneeof the B-H curve.
• Accurate centertapping.
67
SYNCHRO VL-L/FREQ (HZ) ZSS (ΩΩ)
11TR4c15TRx4a15TRx6a18TRx4a18TRx6b23TR623TR6a23TRx4a23TRx6b
90V/40090V/40090V/6090V/40090V/6090V/6090V/6090V/40090V/60
180 to 25050 to82
92016 to 21
350 to 430110 to 145110 to 1456.5 to 8.1
110 to 145
Table 6.2. Common Torque Receivers and theirLoad Impedances.
Figure 6.7. Reference Oscillator.
S1
S3
S2
L
L
L
R
R
SIN
COS
L = Leakage ReactanceR = Loss Resistance
Figure 6.8. Scott-T Output Coupling Transformer.
69
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
SECTION VII
Worst-Case Error Analysis of Typical S/D or R/DConverters
Let us begin this important topic with a comprehen-sive listing of error sources, together with brief expo-sitions of the nature of their possible effects on accu-racy ... assuming that they do affect a particular typeof converter. We shall first list the possible "external"error sources - those that derive from system char-acteristics and environment stresses outside theconverter.
• Reference carrier frequency variations from thenominal. These can be first-order error sources,but only in the RC-phase-shift types of converters.
• Reference-carrier rotor-to-stator time-phase shift(α). The effects of this error source have beenthoroughly discussed earlier (see Section II), butnote that second-order phase shifts can be intro-duced by circuit components, such as referenceand data isolation transformers, quadrant selec-tors, function generators, etc.
• Reference carrier harmonics. Note that it is impor-tant to distinguish between differential harmonics(those that do not also appear in the data signals)and total reference harmonics.
• Reference amplitude variations.
• Inequalities between the rotor-to-stator transferfunctions of the synchro or resolver by the con-verter input impedance, or asymmetrical synchroor resolver effective source impedances.
• Quadrature voltage components in the input datasignal including "speed voltage" quadrature com-ponents (discussed later in this section).
• Excessive shaft velocity - i.e., a greater rate ofchange of θ per unit time (dθ/dt) than the convert-er can track without error.
• Acceleration - the rate of change of velocity perunit time; or d²θ/dt².
• Ambient temperature changes.
• Changes in the power supply to the converter.
• The passage of time (in other words, aging effects,operating and/or nonoperating).
• Humidity and other atmospheric effects, includingaltitude changes, corrosion, etc.
• Shock and vibration effects.
• Noise - conducted, radiated, induced, and gener-ated in ground loops - entering via the data, refer-ence, and power-supply lines. Includes periodicand aperiodic, as well as random components.For convenience, common-mode errors may beincluded in this category, since they have thesame effect as ground-loop-coupled noise.
Now let us turn our attention to possible "internal"error sources; ones that derive from the inherent lim-itations of circuit technique, and/or imperfections inthe circuit design, components, adjustments, or qual-ity of control of the converter itself.
• Quantizing uncertainty - i.e., the inevitable uncer-tainty due to the fact that θ, being an analog quan-tity, is a continuum (has all values between any ini-tial condition and any other value to which it haschanged), and the digital output cannot change insmaller steps than 1 LSB. Thus, if the actual inputvalue is more than that expressed digitally, butless than that expressed by an additional LSB,there is a quantizing error. The higher the resolu-tion (i.e., the more bits in the angle-data word), thesmaller the uncertainty.
• Nonmonotonicity is the failure of the output tochange in the same direction as the input changes
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
(a problem at "major carry" transitions) in the out-put codes of certain types of A/D converters.
• Nonlinearity in the input/output response of theconverter, regardless of the physical cause. Thiserror cannot be detected by checking the accura-cy at one or a few points in the range. It is some-times called "relative accuracy", or the "deviationfrom the best straight-line characteristic."
• Calibration error - i.e., difference between theabsolute value of θ and the actual value of the out-put measure (usually) at full scale, under standard(nominal) conditions.
• Zero offset, due to internally generated anom-alous voltages and currents, at any point in the cir-cuit. These effects are dependent on time, tem-perature, and power supply.
• Internal noise (and the output "jitter" it causes).
Finally, let us consider the possible sources of errorthat may be present at the interfaces - input and out-put - of the converter:
• Sampling errors - uncertainties caused by varia-tion in the time of sampling (with respect to somereference), and in the relative accuracy of thesamples, from channel to channel, or from sampleto sample on a particular channel. ("Accuracy"includes gain, settling time, and aperture errors.)
• Skew - error caused by sampling different input-data channels on successive cycles (peaks of ref-erence carrier wave), caused by the non-simul-taneity of sampling.
• Staleness - errors caused by the fact that data istaken (in certain types of converters) only onceper carrier cycle, and any changes in θ betweensamples are not reflected in the output reading.
• Hold drift. After sampling, the sample/hold circuitmay not "freeze" the data perfectly, but may drift dur-ing (or while waiting for) conversion. (This source mayalternatively be considered part of the converter).
• Output loading errors.
The worst-case error statement for the performanceof a Synchro/Resolver-to-Digital converter can takemany forms, but the three most useful forms arethese:
1. A statement of the largest possible error in thedigitally coded value of θ, for specific standardexternal conditions (nominal values), including asummation of all internal errors, but excludinginterface errors (multiplexing, separate S/H, etc.).
2. A statement of the largest possible error in thedigitally coded value of θ, including a summationof both the effects of the rated ranges of externalerror sources, and all internal errors, but stillexcluding interface errors.
3. A statement of the largest possible error in thedigitally coded value of θ, computed by summingall possible error sources, for a given set of exter-nal conditions, a given set of interface hardware,and a given load.
70
Figure 7.1. I Servo used in many synchro-to-digitalconverters, has single-integrator feedback loop, and
exhibits both acceleration and velocity errors.
Ky
VELOCITYERROR = θ − φ
TIME
θ - φ
θ, φ
θ
φ
φ
Kv (θ - φ) dt = Kv φ
Kv (θ - φ) = dφ/dt
t
0
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
From these three statements, the first might be saidto characterize the typical performance of the con-verter. It is only useful in that it shows what thedevice is capable of doing, given ideal external andinterface conditions. It can be a trap for the unwary.Beware! The second statement might be said todefine the device's behavior realistically, as a guideto what external error sources may be tolerated.Finally, the third statement might be called the "sys-tem limit of error," and can only be made when thenature and magnitude of every error source isknown; therefore, it lies most properly in the domainof the system designer.
Velocity and Acceleration Errors in Type I andType II Servos
It is clear from the discussion of the tracking S/D orR/D converter on pages 19 to 22 that the dynamicperformance of any converter in which the measure-ment is the result of a null-seeking (or "servoing")action can be analyzed in the same way that aclosed-loop control system (or servomechanism) isanalyzed. In this field of analysis, a Type I servo is
one in which there is one significant time-constant(integration) in the feedback loop - i.e., the equationrelation error to correction is a first-order equation.The correction (feedback) loop is shown in Figure7.1, as is the graph of response to an accelerationfrom rest, followed by a (later) deceleration to rest, ata new value of θ. As predicted by the equationsshown, both velocity and acceleration errors areinevitable, for practical loop gains.
Figure 7.2 shows the two-time-constant (double-inte-grator) Type II servo, its response to an identical accel-eration from rest, and later deceleration to rest. As theequations predict, there is still a (momentary) acceler-ation error, but the velocity error is zero. To summarize:
Type I Converter
In a Type I servo S/D or R/D converter, there are bothacceleration errors and velocity errors in the positionreading (φ):
where Ea = error in f due to acceleration,Ev = error in f due to velocity,Ka = acceleration-error constant,Kv = velocity-error constant.
In a type I converter:
aK = 0
vK = 2000 (sec )-1
aE = = ∞80˚ / sec0
2
(constantly increasing error with constant acceleration)
d φdt
E =
2
aaK
dφdt
E = avK
71
Figure 7.2. Type II Servo used in many advanced-design synchro-to-digital converters, has double-integrator feedback loop, and exhibits no velocityerror — although both acceleration errors remain.
TIME
θ - φ
θ, φ
θ
φ
φθ
ZEROVELOCITYERROR
dφ/dt
Kv
Ka
Ka (θ - φ) dt2 = φ
Ka (θ - φ) = d2φ/dt2
Kv (θ - φ) = dφ/dt
t
0
t
0
φ
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
(fixed error at constant velocity)
Type II Converter
In a Type II servo S/D or R/D converter (such as thetrue tracking converter described on pages 19 to 22),there is no velocity error, but there is a finite acceler-ation error (only during acceleration) in the positionreading (φ):
The dynamic behavior of standard S/D or R/D con-verters is specified in terms of Kv and Ka. Typicalvalues and error calculations are given below, forboth Type I and Type II designs, for typical velocitiesand accelerations.
In a type II converter:
(fixed error with constant velocity)
(zero error at constant velocity)
E = = 0˚v360˚/sec
∞
E = = 0.01˚2
a80˚/sec8,000
K = 8,000(sec )-2a
K = ∞v
acceleration = 80˚/sec 2
velocity = 360˚/sec
d φdt
E =
2
aaK
dφdt
E = = 0 a ∞2
(K = ∞)v
Ev = = 0.18˚ 360˚/sec
2000
The Relationship Between Bandwidth, TrackingRate and Settling Time for Synchro/Resolver-To-Digital Conversion
When using the low cost RDC-19220 or RD-19230series monolithic converter for position and velocityfeedback it is important to understand the dynamicresponse for a changing input. When consideringwhat bandwidth to set your converter, several para-meters have to be taken into consideration. The abil-ity to track step responses and accelerations willdetermine what bandwidth to select. The lower thebandwidth the greater the noise immunity. The rela-tionship between maximum tracking rate and band-width determines the settling time for small and largesteps. For a small step the bandwidth is what deter-mines the settling time; when you have a large stepthe maximum slew rate and bandwidth is what deter-mines the settling time. It is recommended that youmaintain a 4:1 ratio between carrier frequency tobandwidth; this will provide a greater rejection of car-rier frequency ripple. As the bandwidth approachesthe carrier frequency, the converter may jitter due tocarrier frequency ripple.
RDC-19220 and RD-19230 Series TransferFunction
The dynamic performance of these converters canbe determined from their transfer function. SeeFigure 7.3.
72
ERROR PROCESSOR
RESOLVERINPUT
VELOCITYOUT
DIGITALPOSITION
OUT(φ)
VCOCT SA + 1 1 B
S S + 1 10B
H = 1
+
-
e A 2 S
Figure 7.3. Transfer Function Block Diagram.
73
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
The components of gain coefficient are error gradi-ent, integrator gain, and VCO gain. These can bebroken down as follows:
- Error Gradient = 0.011 volts per LSB (CT + ErrorAmp + Demod with 2 Vrms input)
- Integrator gain = (CS•FS) / 1.1•CBW [volts per sec-ond per volt]
- VCO gain = 1/1.25•RV•CVCO [LSB's per secondper volt]
FS = 70 KHz when RS = 30 KΩ, therefore R1 @ 1.5 MΩFS = 100 KHz when RS = 20 KΩ, therefore R1 @ 1 MΩFS = 134 KHz when RS = 15 KΩ, therefore R1 @ 750 KΩCVCO = 50 pF
Setup of bandwidth and velocity scaling for the opti-mized critically damped case should proceed as fol-lows:
0.011R1 • CBW • 1.1
1Rv • CVCO • 1.25
•
A1 A2
R1 =
CS = 10pf
1CS • FS
S = complex frequency variable (j ω)
Setup of bandwidth and velocity scaling for the opti-mized critically damped case should proceed as fol-lows:
• Select the desired fBW (closed loop)
• Select fcarrier 4 fBW
• Compute:
EXAMPLE:
Reference: 2 KHzResolution: 16 bitsBandwidth: 100 HzMax Tracking: 10 RPSRc = 30 KΩRs = 30 KΩFs = 70 KHz
3.2 • Fs (Hz) • 10Rv • (f )• Compute: C =BW(pf)
BW2
8
0.9C • f
• Compute: R =BBWBW
C 10
• Compute: = BW
R = 55 KΩ • see converter max tracking rate tapplication max ratev
A2
Open Loop Transfer Function = [ ][ ]S10B
SB
+ 1
S2 + 1
23 K N/A576230415 K N/A
23 K 108432172820 K 27
30 K or open 72*288*1152*30 K 18*
RC (ΩΩ) 141210RS (ΩΩ) 16
Table 7.1. Maximum Tracking Rate in rps (revolutions per second).
*Use when computing Rv.
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
Values calculated by using RDC-19220 componentselection software. (Contact factory or downloadfrom http://www.ddc-web.com)
RDC-19220 or RD-19230 Maximum Tracking Rate
The tracking rate (nominally 4 volts) is limited by twofactors: Velocity saturation and maximum internalclock rate (nominally 1,333,333 Hz).
The resistor Rv determines the velocity scaling. It isthe input resistor to an inverting integrator with a
C = .022 µfBW
R = 100 KΩV
C = 2200 pfBW/10
R = 410 KΩB
C 10
BW = 2200 pf
R = = 415 KΩ0.921656 • 10 • 100B -12
Rv = 55KΩ • = 99KΩ1810
CBW (pf) = 3.2 • 70,000 • 10
8
99,000 • (100) 2
= 22626 pf
= .022 µf
50 pf nominal feedback capacitor. When it inte-grates to -1.25, the converter counts up 1 LSB andwhen it integrates to +1.25, the converter countsdown 1 LSB. When a count is taken, a charge isdumped on the capacitor, such that the voltage on itchanges 1.25 V in a direction to bring it to 0 V. Theoutput counts per second per volt input is therefore:
With Rs @ 30KΩ the internal clock rate is 1,333,333Hz.
Absolute maximum tracking is calculated as follows:
For a 10-bit converter there are 210 = 1024 countsper rotation.
1,333,333/1024=1302.08 rps or 1302.08/4=325.52 x1024=333,333 counts per second per volt.
This is the absolute maximum rate; it is recommend-ed to only run at 90% of this rate therefore the mini-mum Rv will be limited to 55 KΩ.
Rs=20 KΩ internal clock nominally 2,000,000 Hz.
Rs=15 KΩ internal clock nominally 2,666,666 Hz.
Determining Acceleration Lag and Large StepResponse Settling Time
As you vary the bandwidth and the maximum track-ing rate this will determine your acceleration con-stant (Ka) and large step settling time.
(333,333) • (50 pf) • (1.25)V1R = = 48 KΩ
(Rv) • (50 pf) • (1.25)
1
74
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
EXAMPLE:
Find the acceleration constant (Ka) and the acceler-ation lag for a system with the following parameters:
Resolution: 16 bitsBandwidth: 100 HzReference: 1000 HzMax Tracking: 10 RPSTo solve for Ka:
EXAMPLE:
To solve for acceleration rate that results in 1 LSB of error:
Acceleration Lag = Acceleration RateKa
Acceleration Rate (for 1 LSB error, 16-bit mode) = (Ka)(Lag for 1 LSB error)
Acceleration Rate (for 1 LSB error, 16-bit mode)
= (49,348)(0.0055˚)
sec 2
Acceleration Rate (for 1 LSB error, 16-bit mode)
= 272˚sec2
BW = 2 • Aπ
and Ka = A2
therefore A = (BW)(π)
2
and Ka = (BW)(π)
2
2
Ka = (100 Hz)(π)
2
2
Ka = 49,348
sec 2
To determine a large step response you must takeinto account the maximum tracking rate and band-width.
EXAMPLE:
Solve for the large step response (179°) settling timefor a 16-bit mode system with the following parame-ters:
Bandwidth = 100 HzMaximum Tracking Rate = 10 rps
Then we must add the settling time due to bandwidthlimitation; this is approximately 11 time constants in16-bit mode.
Maximum Tracking = • 10 rps360˚1 revolution
= 3600˚/s
The Settling Time due to Tracking Rate:
tTR = step sizemax. tracking rate
= 179˚3600˚/sec
= 49 msec
75
RESOLUTION COUNTS/ROTATION TIME CONSTRAINTS (TC)
10 1024 7
12 4096 8
14 16384 10
16 65536 11
Table 7.2. Time Constants
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
Therefore the approximate settling time for a largestep would be 98.5 msec. This is an approximation.
Synchros and resolvers are used in a wide variety ofdynamic conditions. Understanding how the con-verter reacts to these input changes will allow you tooptimize the bandwidth and maximum tracking ratefor each application.
Speed-Voltage Susceptibility
When the synchro or resolver shaft is turning (dθ/dtnot equal to 0), a voltage is generated in the stator bythe motion of the rotor field. This voltage is analo-gous to the "counter-EMF" induced in the armatureof a DC motor; it is due the "generator action"inevitably produced by relative motion between a fluxfield and a winding. In the synchro or resolver, thisvoltage is proportional to the speed, has the samefrequency as the reference carrier, and is in quadra-ture to the position signal (data) normally found atany shaft angle. Thus, if the normal resolver-formatsignals produced at θ are:
V = K sin θ sin ωt V = K cos θ sin ωt,
xy
xy
Time Constant = 1A
A = 222
= 4.5 msec1A
11 Time Constants = 49.5 msec
Large Step settling time =
tTR + • tc 1A
= 49 msec + 49.5 msec = 98.5 msec
where tc is the number of time constants
Then, the so-called "speed-voltage" componentwould be a pair of signals in perfect quadrature tothem, with an amplitude (relative to the normal datasignals) that is proportional to dθ/dt, the shaft-anglevelocity:
Where A is a constant of proportionality, or speed-voltage coefficient. It is not uncommon for A toapproach unity in modern synchro-sensed systems.Therefore, speed voltage can hardly be consideredto be negligible, or even a second-order effectdespite the fact that it is often neglected as an errorsource, in specifying synchro/resolver converters!
Fortunately, in the more advanced types of syn-chro/resolver converters, the circuitry discriminatesso effectively against quadrature components thatthe susceptibility of the converter to speed-voltageerror is negligible - at least up to very high velocities.
V = AK sin θ sin ωt V = AK cos θ sin ωt, xsys
xy
76
1111111011011100101110101001100001110110010101000011001000010000
ANALOG OUTPUT(OR INPUT)
FULLSCALE
Figure 7.4. Ideal Transfer Function for a D/S (or S/D) Converter.
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
All converters should of course, be rated for "speed-voltage susceptibility" ... usually in terms of the high-est velocity at which a given synchro or resolver maybe driven without causing an increase in the conver-sion uncertainty (decrease in accuracy from ratedvalue).
Let us consider the effects of speed voltage of thetracking converter described on pages 19 to 22. Thenormal data signal presented to the demodulator is:
K sin θ cos φ sin ωt K cos θ sin φ sin ωt,
xy
which has been shown to be equal to
K sin(θ – φ)sin ωtprovided K = K = Kx y
and, for small values of (θ – φ),
K sin(θ – φ) ≅ K (θ – φ) sin ωt
In the presence of speed voltage, the demodulatorreceives another signal component, in quadrature:
If the demodulator has infinite quadrature rejection,no speed-voltage error would result; however, forvery large values of A, saturation might occur in thedemodulator, causing large errors. A well designeddemodulator should have wide dynamic range andexcellent quadrature rejection ... which points out theadvantage of using a synthesized reference as dis-cussed on page 22. (See page 83 for calculation ofquadrature rejection.)
Resolution, Linearity, Monotonicity, andAbsolute Accuracy
These terms have the same meaning and impor-tance for synchro/resolver-to-digital converters asthey do for conventional analog-to-digital converters.The resolution of a converter is the weight of thesmallest change in its digital output or the weight ofthe least-significant bit (LSB). Calculation of thisparameter was explained on page 9, but the basicexpression is repeated here, for convenience:
Where n is the number of bits in the conversion. Formost converters, full scale is 360°, so for a 16-bitconverter the LSB is:
Note that if noise introduced by either the externalcircuit or the converter circuitry itself is larger than±1/2 LSB (peak), the usable resolution will be
LSB = = ≅ 0.0055˚ 360˚ 2 16
360˚65536
LSB = full scale angle2n
AK sin(θ – φ) cos ωt ≅ AK (θ – φ) cos ωt
where A = revolutions/secondcarrier frequency
77
10001
10000
01111
01110
01101
01100
IDEALCHARACTERISTICS
NON-MONOTONICITYAT "MAJOR CARRY"
"MISSING CODE"
ANALOG INPUT
Figure 7.5. Nonmonotonic Behavior in an S/D Converter.
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
reduced by making it impossible to depend onchanges as small as 1 LSB.
The linearity of a converter is the measure of themaximum deviation from the ideal transfer functionshown in Figure 7.4. These are two kinds of lineari-ty: integral and differential.
• Integral nonlinearity is defined as the maximumdeviation from a straight line drawn through theideal transfer function, and is usually expressed asa percentage of the nominal full-scale value.
• Differential linearity is a measure of the deviationof the digital output from equal step-per-bit behav-ior. The worst-case deviation of the smallest orlargest step (bit) from the theoretical (LSB) size.The differential nonlinearity is expressed as a per-centage of the theoretical LSB.
Monotonicity is the property of S/D, R/D and A/Dconverters that ensure that an increase in the analoginput will never cause a corresponding decrease inthe digital output. In some kinds of converters(notably, the kind that employ successive approxima-tion or table-look-up techniques), nonmonotonicitycan occur at "major carry" transitions, as shown in
Figure 7.5, for the transition from 01111 to 10000.The cause of the nonmonotonic behavior shown inthe transfer characteristic of Figure 7.5 is a smallerror in the circuit that establishes the most-signifi-cant ONE or an error pile-up in the circuitry for theother, less significant bits, or both.
In either case, the effect is to associate a decreasein analog signals with an increase in the digitalresult. (If the analog signal changes by more thanone bit, but less than two bits, but the digital signalfails to change [skipping to a two-bit or larger stepwhen the analog input changes even more] this iscalled a "missing code." It may be considered to bea special form of nonmonotonicity.) Pulse-train-and-counter forms of S/D or R/D converters, like the har-monic oscillator designs described in Section II,have inherently perfect monotonicity since theyalways convert in uniform steps, and do not have cir-cuitry that can produce major-carry conversionerrors.
Accuracy is the most abused term in the entire fieldof "specmanship." Part of the abuse stems fromloose language and from differences between meth-ods of measurement.
Absolute accuracy must be measured (and/orspecified) under a standard set of conditions, andmust include all of the variation in operating range,environment, signal characteristics, and all parame-ters that make up the ratings of the instrument.Finally, these variations must be allowed for in the
78
ACCURACY (Note 1): ±1 arc minute
RESOLUTION: 16 bits
CODING: Natural Binary Angle
MAX. TRACKING VELOCITY: 360°/sec
1 LSB ERROR
ACCELERATION: 45°/sec/sec
NOTE 1: Accuracy applies over rated operat-ing temperature range, 5% variation of powersupplies, 10% amplitude and frequency varia-tion, and up to 10% harmonic distortion ofsynchro and reference inputs.
Figure 7.6. Example of a Valid Accuracy Statement.
Figure 7.7. LED Driver Schematic.
INPUT
LED
+5V
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
worst possible combination of their effects on thereading. Then, and only then, will the following defi-nitions be valid:
• Absolute accuracy is defined as the maximumdeviation of any conversion (any reading, in thecase of instruments) from the rated transfer char-acteristic, measured with reference to the absoluteunder standard conditions, such as the NationalBureau of Standards (NBS) and over all ratedoperating ranges. It is expressed (usually) as apercentage of the rated full-scale value.
• Relative accuracy is measured and expressed inthe same way, but is defined in terms of the actu-al, rather than the rated, full-scale value. Note thatthis means that Relative accuracy is merely anoth-er way of defining Linearity!
An example of a valid Absolute accuracy statementis given in Figure 7.6.
Static Errors and Instabilities
At times, the Absolute accuracy rating, or even theRelative accuracy rating, of a converter is too harsha judgement in the sense that any application maynot impose the full range of rated variations on theconverter. For this reason, it is important to be ableto measure and predict all of the components of errorthat contribute to the total worst-case uncertainty.One group of these components of error, each sepa-rately measurable, is the so-called "static" sources oferror. They do not arise from either signal dynamicsor signal characteristics. These include:
• Input Offsets (voltage and current) in multiplexers,sample/holds, and any DC-coupled circuitry insidethe converter — These may be susceptible toexternal "trimming" (Zeroing), but, since they driftwith time, temperature, and power supply, suchadjustments are at best crude and temporary cor-rections. The best equipment has inherently lowoffsets, inherently high offset stability, is rated foruntrimmed service and all initial adjustment doneat the factory only. Low current offset is mandato-ry for high-impedance sources.
• Gain errors and drifts — These result in calibration(scale) errors, and may be trimmed out for any onetemperature and power-supply condition, at anytime, but will inevitably drift again. Here again, thebest plan is to select a design that has inherentlyaccurate and stable full-scale calibration, withoutthe trimming.
Measurement of static error components in S/D orR/D converters is relatively straightforward and easy.The converter is connected to its synchro or resolvertransducer, and operated at the typical values of tem-perature and power supply (or line voltage, if self-powered). The transducer is excited by the typicalsine wave reference carrier, and is aligned so thatelectrical and mechanical zero coincide to an accu-racy significantly higher than the converter resolu-tion. If the converter has a zero-setting adjustment,it is used to set digital output to zero (e.g., allZEROES, in natural binary code). If the converterhas no zero adjustment, the digital output at zerodata input is a measure of zero offset. (NOTE: allowa reasonable warm-up time, to ensure thermal equi-librium. The manufacturer will recommend a warm-up delay period, if one is required.)
Maintaining the above typical conditions, the zerodrift with time may then be observed by monitoringthe digital output. (Figure 7.7 shows a useful displaycircuit for monitoring each digital output terminal.)Remember that all other parameters: temperature,power-supply levels, reference-carrier amplitude, fre-quency, and waveform, must be held constant duringthe entire period of the test. Gain stability is mea-sured by repeating all of the above steps for a full-scale input (corresponding to a full-scale digital out-put - i.e., all ONES in natural binary code), andobserving the output variation with time.
Temperature effects may be observed by raising theambient temperature of the converter (only) to therated upper limit. Allow it to reach the new thermalequilibrium, and then observing the output for bothzero and full-scale inputs. All other parameters must,of course, be maintained at typical values. Repeat,for an ambient temperature and at the rated lowerlimit.
79
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
Return the converter to thermal equilibrium at thetypical ambient temperature (i.e., 25°C), and raisethe power supply levels to the rated upper limits, andobserve the digital output at both zero and full-scaledata inputs. (Changing the power supply levels willprobably require waiting for a new thermal equilibri-um, since the internal dissipation will change.)Repeat the test with the power supply levels at therated lower limits.
Time-stability tests may also be run at various com-binations of upper and lower temperature and powersupply limits, but these may not be any more signifi-cant than the typical time-stability tests.
Maximum Tracking Rate
Regardless of the circuit approach used in a S/D orR/D converter, there is an upper limit on the velocity
(the rate of change of θ) that it can measure withoutexceeding its rated error. This is just as true for the"true tracking" converters as it is for harmonic-oscil-lator and successive approximation designs; theymay have different upper limits of dθ/dt, but they allhave such a limit.
The Type-II-loop tracking converter described onpages 19 to 22 may have no velocity error whendθ/dt implies a counting rate that is higher than thatprovided by its VCO (pulse generator), then it cannottrack θ, and will exhibit a rapidly increasing error.
Similarly, in the successive approximation and har-monic-oscillator converters, the "staleness" errorincreases in direct proportion to dθ/dt. Since theconverter samples once on each carrier peak, thestaleness (difference between the digitized value ofthe sampled data and the actual value of θ justbefore the next sample) will exceed the allowablesystem error when θ changes more than that allow-able error limit in one carrier period.
Measuring the tracking rate limit of a Type II con-verter requires special equipment. One method ofseveral in current use is described here:
• Drive the synchro or resolver at a constant veloc-ity well below the rated upper limit, and measurethe repetition rate of the MSB pulse on an electricfrequency meter (counter-timer).
• Slowly increase the velocity of the synchro orresolver until the measured repetition rate of theMSB pulse is no longer exactly proportioned tothe velocity. (Make several measurements of rep-etition rate at each increment of velocity, to ensurethat no acceleration errors are present, andexplore the velocity region near the apparent limitcarefully, to be sure that you have found the exactvelocity at which the repetition rate departs fromproportionality.)
Measurement of the tracking rate limit of samplingconverters is meaningless, because "staleness"error is readily calculated (see page 28), and noother limitation in the converter is significant.
80
PROBABILITYDISTRIBUTIONOF NOISEENERGY
ANALOG VALUE
IDEAL TRANSFERCHARACTERISTIC
EFFECTS OFNOISE
DIG
ITA
L V
ALU
E
±1 LSB
Figure 7.8. Effect of Gaussian Distribution of Noiseon Performance of and S/D Converter.
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
"Skew" in Sampled Systems
As described on pages 30 to 33, multi-channel sys-tems that employ a single multiplexed S/D or R/Dconverter and a single sample-hold that samples thechannel (sequentially or randomly) on successivecarrier peaks exhibit a skew error proportional to thevelocity. If θ can vary at a rate of:
then the maximum skew error, between the first andNth channel sampled is:
Measurement of this parameter is meaningless,since it is readily calculable from the system charac-teristics, and is unaffected by system performance -assuming the system functions normally.
Quantization Uncertainty
We have already mentioned the inevitability of aquantization uncertainty of ±1/2 LSB in synchro-to-digital or resolver-to-digital conversion (page 20) andwe have also noted that noise (random or periodic)can enlarge the quantization-uncertainty "band"without limit. Figure 7.8 illustrates the relationshipbetween the Gaussian, "white" noise, distribution ofpeak energy and the number of bits of uncertaintyone may observe, and demonstrates that it is notnecessarily correct to assume that the quantizationuncertainty is at its minimum value of ±1/2 LSB. Onlya test program that observes the last few LSB's, withinput set at full scale -1/2 LSB will verify that noisehas not broadened the quantization-uncertainty"band."
E = NVmax
f skewn=N
n=1 ˚/sec
VMAX = dθ dt
max˚/sec
and the carrier frequency is:
f = ω
2π Hertz
Jitter Due to Hunting in Tracking Converters
As noted in our discussion of the tracking converter(pages 19 to 22), the quantization uncertainty in thedigital output requires that inclusion of a hysteresisthreshold in the error-processor loop. This hysteresisis made smaller than the LSB; but, as discussedabove, noise or other disturbances (such as veryrapid speed pulsation in the system) will cause theoutput of the converter to hunt or jitter around someaverage value. Again, only careful observation ofseveral of the least-significant bits, with a data inputof full-scale -1/2 LSB will eliminate noise as thesource of jitter. Jitter due to speed pulsations is anormal and correct response to the acceleration -deceleration cycles implicit in the input variation, andcan only be accepted or ignored by not using the bitsthat represent the hunting "band."
LOS Circuit to Detect Loss of Signal
The loss of signal (LOS) output of the new genera-tion of S/D or R/D converters is used for system safe-ty and diagnostics. This circuit monitors the sine andcosine signals at the input of the converter andchanges logic state if both signals are disconnectedat the same time. With disconnected inputs convert-er performance and output are unpredictable, and ifin a motion control or monitoring system could causeserious problems.
BIT Logic to Detect Malfunction
In some modern synchro-to-digital or resolver-to-dig-ital converters, a Built-In-Test (BIT) capability is pro-vided, to signal when the velocity limit of the con-verter is exceeded, and/or when an internal malfunc-tion has caused an erroneous digital output. Oneimplementation of this circuit takes advantage of thefact that excessive velocity, as well as many grossmalfunctions that can occur in the converter, result inan error-processor output that exceeds a predeter-mined threshold for a sustained period. Once thisabnormal state is detected a one-bit signal is deliv-ered to the BIT output terminal. In angle indicators,this datum may be used to blank the display, or tolight a warning indicator.
81
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
Harmonic Errors
Even-order harmonics (2nd, 4th, 6th, etc.) in the datasignal fed to a tracking converter are effectivelyrejected by the phase-sensitive demodulator in theerror processor. (The degree of rejection will be dis-cussed next). Odd harmonics - the 3rd, 5th, 7th, etc.- do cause an error, and their effect on the outputmust be considered. A safe approximation of theireffect, which assumes the worst possible phase rela-tionship between the harmonic and the fundamentalis that the error (EH) due to a particular harmoniccomponent is:
Where %THC is the total harmonic content,expressed as a percentage of the fundamental, andn is the order of the harmonic in question.
The total error due to all (odd) harmonic componentsis conservatively estimated by the summation:
If all odd harmonics are present, the expressionapproaches a practical limit of:
In most sampling S/D or R/D converters, errors dueto odd harmonics are not attenuated by n, but ratherare felt fully and estimated by:
E = radians(%THC)
100H
E = radians(%THC)
50H
E = radians(%THC)
100nH
n=N
n=3Σ
E = radians(%THC)
50H13
15
17
– + …
or
E = radians(%THC)
100nH
Quadrature Errors
The quadrature rejection of an ideal balancedphase-sensitive demodulator is theoretically infinite,provided that the time-phase of the reference carrierfed to it is the same as that of the in-phase compo-nent of the data signal to be demodulated by it or, ifthe time-phase difference between the quadraturecomponent and the reference carrier is exactly 90°.Reference phase error (departure from the above)yields some error output in response to quadraturecomponent, in accordance with the following approx-imation.
where: EQ is the error due to the quadrature compo-nent in radians; (%QC) is the quadrature componentof the input signal to the demodulator, expressed asa percentage of the input data signal; and α is thereference-to-data time-phase error in degrees.
It is clear from the above equation that the quadra-ture rejection of an ideal phase-sensitive demodula-tor may be estimated at:
Note that for α = 0, the rejection is infinite.
The speed-voltage error, EVS, of a converter may becalculated from A, the ratio of speed voltage to datavoltage (see page 75):
Practical (as opposed to ideal) demodulators have afinite rejection ratio for both even harmonics andquadrature components, independent of the refer-ence-time-phase errors described above. If the
E = tan α radiansspeed voltagedata voltageVS
E = A tan α radiansVS
Quadrature Rejection = 1 tan α
E = tan α radians(%QC)
100Q
82
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
rejection coefficient at α = 0 is Kd, then the aboveequations must be modified to reflect this practicallimit. Thus, the preceding equation would become:
A typical value for Kd is 200.
Amplitude Errors
In the most advanced synchro-to-digital or resolver-to-digital converters, the only amplitude errors thatare significant are those that alter the ratio of the sineand cosine data signals in the resolver format signalset. These can result only from gain (transfer func-tion) inequalities in any of the following elements ofthe system:
• The synchro or resolver (rotor-to-stator gaininequalities).
• The isolation or Scott-T transformer.
• Sample-Hold circuits.
• Multiplexers (and buffer amplifiers associated withthem).
• Unbalanced loading of the signal sources (and ofthe cabling between them and the converterinputs).
E = A tan α + radiansVS1Kd
One additional source of sine/cosine ratio error is theinability of the converter to reject anomalous inputsignals, such as:
• Common-mode voltages at the carrier frequency (due to ground loop signal injection and/or straypickup from carrier-frequency electromagneticand electrostatic fields).
• Carrier-frequency ripple components in the powersupply voltages.
• Interaction between adjacent channels in a multi-channel system.
The magnitude of such errors may be estimated bycomputing the affect on the converter of a change inthe sine/cosine ratio (δ):
The error in the measurement of θ, Eamp, due to aratio error δ is, then
E = tan (δ) radians–1amp
and since for very small angles,
tan δ ≅ δ
E = 57δ degreesamp
K(1+ δ)VKV
(1+ δ)sinθcosθ
xy
= = (1+δ) tan α
83
MEASURING AND COMPUTING SYNCHRO/RESOLVER-TO-DIGITAL AND SYNCHRO/RESOLVER-TO-DC CONVERTER PARAMETERS
84
THIS PAGE INTENTIONALLY LEFT BLANK
MEASURING AND COMPUTING DIGITAL-TO-SYNCHRO OR DIGITAL-TO-RESOLVER CONVERTER PARAMETERS
Worst-Case Error Analyses of Typical Digital-to-Synchro (D/S) or Digital-to-Resolver (D/R)Converters
All of the error sources to be considered here havealready been mentioned in the preceding section forthe very simple reason that many Synchro-to-Digital(S/D) or Resolver-to-Digital (R/D) converters incor-porate a D/S or D/R converter. (Compare, for exam-ple, Figure 2.5 and 5.1.) By isolating the circuit ele-ments specifically used in the D/S or D/R function,we can develop insight into the error sources thataffect them only.
Of the many error sources listed and discussed inSection VII, the following may be significant, in someor all of the D/S or D/R configurations in common use:
External Influences:
• Ambient-temperature changes
• Power-supply changes
• The passage of time
• Environmental effects: Humidity, Altitude,Corrosion, Shock, Vibration, etc.
• Noise
• Reference harmonics
Interface Influences:
• Asymmetrical or excessive loading of the convert-er by the synchro or resolver
• Inadequate drive (or level mismatch) at the datainput or reference-input interfaces
Internal Influences:
• Nonmonotonicity
• Nonlinearity
• Calibration error (gain error)
• Zero offset
• Internally generated noise
• Function-generation errors
The above list is relatively shorter than that for theS/D or R/D converter; primarily because there ismuch less circuitry in the D/S or D/R converter, butalso because the D/S or D/R converter does not haveto supply the critical synchro- or resolver-input inter-face. The digital-input interface is much less critical(because it is digital), and the synchro- or resolver-output interface is inherently less demanding.
For a discussion of the various methods of combin-ing the effects of these error sources, please referback to the similar discussion in Section VII.
Static Accuracy (Network) Errors
A primary concern in all D/S or D/R converters thatuse function-generating networks (which means, ofcourse, the great majority of converters) is theintegrity with which the output generates the requiredsine or cosine function in response to the digitalinput. Ignoring such serious limitations as high cost,size, and weight, the ratio-transformer types of func-tion generators (see pages 17 and 18) are inherent-ly the most accurate.
Weighted resistor-ratio networks are subject to thefollowing uncertainties:
• Initial tolerances on the ratios
• Drift in ratio (failure to track) with respect to timeand temperature
• Offset voltages and currents in the switch circuitry
85
SECTION VIII
MEASURING AND COMPUTING DIGITAL-TO-SYNCHRO OR DIGITAL-TO-RESOLVER CONVERTER PARAMETERS
• Drift in offset voltages and currents, with respect totime, temperature, and power-supply levels
• Transient errors at high speed - e.g., failure to set-tle in a time consistent with the conversion rate,inadequate slew rate, "glitches"
• Inadequate bandwidth at the reference-carrier fre-quency, in one or more regions of the ratio range(This is rarely a significant error source, in a rea-sonably well-designed network)
Selectively loaded resistor-ratio networks are subjectto all of the above error sources, plus the inevitableapproximations inherent in the loaded-linear-networkapproach. On the other hand, the initial-toleranceproblem is less severe in constructing a linear net-work, so the ultimate performance of this class ofnetworks (for applications requiring no greater than1-minute long-term accuracy) is superior to manyweight-ratio designs).
Static testing of D/S or D/R networks (see Figure 8.1)requires very little equipment: a set of switches forapplying the logic levels corresponding to variousdigital inputs; a stable reference-carrier signalsource; a load and a four to five-digit angle indicator.(A phase-sensitive digital voltmeter is practical, butrequires calculations.) Dynamic testing is discussedlater in this section.
Effects of Settling Time and Maximum Slew Rate
The dynamic response parameters of the function-generator network, the output amplifier, and the var-ious logic circuits employed for quadrant selectioncan all contribute constraints to the dynamic perfor-mance of a D/S or D/R converter. The overalldynamic performance parameters of interest are:
• Settling Time, which in turn limits data throughputrate - i.e., the number of accurateconversions/second
• Slew Rate, which in turn limits dynamic range and(indirectly) data throughput rate
• "Glitch" energy, which imposes limits on both theuseful data throughput rate, and (indirectly) thedynamic range
Figure 8.2 illustrates all three dynamic performancefactors listed above. Note that the glitch-area ener-gy (volt-seconds) may be much larger than onemight infer from the ±1/2 LSB bandwidth shown as areference, provided that either one of the two com-pensatory system accommodations have beenmade:
1. A delay has been imposed (e.g., by inhibit-gatetechniques) between the application of the digital
86
MSB
ONELEVEL
D/S OR D/RCONVERTER
UNDERTEST
Vref
CT LOAD
ANGLEINDICATOR
ORPAV
OUTPUT
STABLEOSCILLATOR
+
Figure 8.1. Testing D/S (or D/R) Converters.
MEASURING AND COMPUTING DIGITAL-TO-SYNCHRO OR DIGITAL-TO-RESOLVER CONVERTER PARAMETERS
step-function change and the application of thatchange to the output circuit, to allow the glitch tosettle out.
2. Sufficient filtering between the converter and theload (synchro or resolver) has been provided - oris naturally present in the form of mechanical iner-tia - so that the effect of the glitch-area energy isrendered negligible. The accommodation impliesa sacrifice in slew rate and data throughput rate, ofcourse.
Dynamic testing of D/S or D/R converters may bestbe done with the aid of a computer, a ROM (read-only memory), or some other high-speed store-pro-
gram device; however, manual test methods arepractical, if slow and laborious. Figure 8.3 shows atest setup that used manually switched input words,strobed from a storage register into the D/S or D/Rconverter by means of a pulse that also simultane-ously triggers a storage oscilloscope. (An oscillo-scope equipped with fixed or adjustable signal delayis preferable, to avoid loss of the earliest part of theresponse characteristics). Assuming that the staticcharacteristics have already been verified, thedynamic response of the carrier envelope may bequalitatively judged from the single-transient record-ing provided by this setup.
In the real world of physical systems the D/S or D/R con-verter has a transfer function of one for small input stepchanges. For large input step changes the output trans-formers and/or the load (if it is inductive it may saturate orbecome non-linear) may cause large transients. This canalso occur at power turn on. In either case the result willbe high power supply demands by the power drivers. It isimportant, therefore to avoid large input step changes and,if multiple D/S or D/R converters are used to drive induc-tive loads, to sequence the application of power to them.
Loading Errors
To be meaningful, all tests on D/S or D/R convertersmust be made with either the actual or simulatedsynchro or resolver load connected. The actual loadto be driven is by far the better choice. As discussed
87
"GLITCH" AREA
1/2 LSB
SETTLINGTIME
SLOPE = SLEW RATE
INP
UT
& O
UT
PU
T(N
OR
MA
LIZ
ED
)
TIME
INPUT "STEP" CHANGE
Figure 8.3. Dynamic Testing of a D/S (or D/R) Converter.
Figure 8.2. Dynamic Parameters of D/S Converters.
ONELEVEL
MANUALSWITCHES
ONESHOT
D/S OR D/RCONVERTER
UNDERTEST
Vref
V
VTRIG
+REGISTER
MEASURING AND COMPUTING DIGITAL-TO-SYNCHRO OR DIGITAL-TO-RESOLVER CONVERTER PARAMETERS
on pages 85 and 86, the power amplifiers and outputtransformer are critical elements in the overall accu-racy-determining chain. This is particularly true if thesynchro or resolver specification allows significantunbalance in its loading on the converter.(Unbalance can be simulated statically by parallelingone or more windings of symmetrical synchro orresolver with additional resistive or reactive loads.)
The principal effects of loading on the performanceof a D/S or D/R converter are:
• Increased nonlinearity in certain regions
• Degradation of slew rate and data throughput rate
• Increased drift, due to self-heating
• Decreased absolute accuracy, due to gain loss
Figure 8.4 shows a static test setup that employsmanually switched data inputs, and a precise read-out of shaft angle, using another synchro or resolvertransducer and a synchro or resolver angle readoutas the result-reporting instrumentation. (Clearly, theaccuracy of the instrumentation should be an orderof magnitude better than the accuracy of the con-verter under test.)
Amplifier Mismatch Errors
Some D/S or D/R converters do not provide theexact voltage, power, or impedance ranges
required by the synchro or resolver to be used. Atfirst glance, it would seem that this kind of mis-match is unimportant, provided that the load fallswithin the limits implicit in the ratings of the D/Sor D/R converter, but that is not always the case.For example, a D/S or D/R converter rated todeliver 90 Volts into 5,000 Ohms or more can beused to drive a 26 Volt, 12,000 Ohm synchro orresolver control transformer, but the slew rate,accuracy, linearity, and possibly the data through-put rates of the converter will be altered consid-erably by the restricted range of operation andthe lightly loaded condition of the output amplifi-er. These mismatch effects can usually be avoid-ed or compensated for, by either internal or exter-nal design modifications.
Static Errors and Instabilities
Refer to pages 79 and 80, on which this subjecthas been discussed in detail for S/D or R/D con-verters, and follow the same general proceduresfor testing, substituting the test circuits given inthis section. Note that reference, power-supply,and temperature changes have far less effect onD/S or D/R converters than they do on S/D or R/Dconverters, because almost every critical para-meter is derived as a ratio. Even the basic refer-ence-carrier signal cannot have a first-ordereffect on accuracy, because the analog data out-put (the angle θ) is synthesized as the ratio of twocarrier-frequency amplitudes, both derived fromthe same reference input.
88
Figure 8.4. Testing D/S (or D/R) Converters Under Load.
STABLEOSCILLATOR
VrefINPUT
CT
PAV
DIALINDICATOR
(GONIOMETER)
D/S OR D/RCONVERTER
UNDERTEST
(INCLUDINGANY REQ'D
AMPLIFIERS)
LOGICONELEVEL
+
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
Parameter Tradeoffs vs. Price
In general (but with many exceptions and even a fewinconsistencies, notable from manufacturer to manu-facturer), the following approximate relationshipshold true for synchro/resolver-to-digital converters:
• Price increases with accuracy, when in the rangeof ±0.5 to ±1 minute.
• Price increases with operating temperature range,for a given electrical performance. The most com-mon ranges are 0° to +70°C, -40° to +85°C and -55°C to +125°C. The prices for the wider rangesare higher.
Typical Interface Circuits (Input and Output)
The following selected discussions are representa-tive of the design considerations encountered by thesystem planner in the field, but this information can-not do more than suggest the broad range of tech-niques possible for system optimization.
One large group of interface problems concerns syn-chronizing the converter (S/D or D/S) with the otherelements in the system. Older S/D converters pro-vided either a "Converter Busy" signal (CB), or a"Data Ready" pulse (DR). This allowed the designerto prevent data transfer or use while a conversionwas in process, thereby avoiding incorrect readings(or invalid data). System compatibility was alsoenhanced, in these S/D converters, by a ConversionInhibit terminal INH, which permitted holding outputdata stable during transfer. Figures 9.1a through9.1d show various ways of using these CB, DR,and/or INH signals in older converters. The newergeneration of S/Ds or R/Ds have internal latches andtri-state output buffers and are much easier to inter-face. We will discuss these S/Ds and R/Ds later.
• The simplest method of forcing synchronizationbetween an older S/D converter and system timingis to use the inhibit (INH) line. Figure 9.1a illus-trates this technique. In most converters with anINH line and Converter Busy (CB) pulse, the CB
89
SECTION IX
Z
Z
Z
3 µs
5 µs5 µs
60* µs MIN.DEPENDING
ON dθ/dt"1"
"0"
"1"
"0"
CONVERTERBUSY (CB)
INHIBITAPPLIED (INH)
DATA TRANSFER
Figure 9.1a. Forced synchronization between S/D and system.
Figure 9.1b. S/D Converter Timing.
S/D
INH CB
REG.
STROBECPU
* 15 µs for Fast Tracking 4 rps units (14-bit resolution)
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
pulse will complete its cycle once it starts. TheINH will prevent it from starting, but if CB has start-ed before an INH is applied, the CB will continueto completion (generally 2-4 µs) and then strobethe data into a register or computer for use in thesystem. Figure 9.1b shows typical timing wave-forms for such S/D converters.
• Figure 9.1c illustrates older S/D converter asyn-chronous data transfer - i.e., data transferred to itsdestination whenever the S/D converter has itavailable (regardless of system timing). A flip-flopbuffer register is enabled to receive the output ofthe converter (by jam transfer) when CB changesto CB ... from logic ONE to logic ZERO. The con-verter is then free to perform its next conversion,leaving the previous datum in the register.
• The response of most D/S converters is extreme-ly fast, and digital data may generally be fed intothe converter, without regard to the converter'sresponse time. In some cases, however, such asin multiplexed systems, or where the D/S convert-er is on a data bus, the data is only valid for a shortperiod of time. For these cases an input bufferregister must be provided, as shown in figure 9.1d.
This allows strobing the data into the converter atthe appropriate time and holding it until the nextupdate. Most digital data sources provide a strobeline for entering the data into a register.
Newer D/S or D/R converters have double-bufferedinput latches making the use of external registerssuperfluous.
Transferring data from the newer S/Ds or R/Ds withinternal latches and tri-state buffers to 8- and 16-bitbuses is shown in Figures 9.1e through 9.1h. Inthese converters the INHIBIT command will lock thedata in the output transparent latch without interfer-ing with the continuous tracking of the converter'sfeedback loop. Therefore, the counter is still allowedto update and the inhibit can be applied for an arbi-trary amount of time without having to worry aboutreacquisition time.
90
CB S/DCONVERTER
MSB MSB
LSB LSB
BUFFERREGISTER
TO COMPUTER,PRINTER, ETC.
STROBE
Figure 9.1c. Asynchronous Data Transfer.
ONE-SHOTDELAY
OR
MSB
D/SCONVERTER
LSB
STROBE
USEDELAYEDGATE OUTPUTor DELAYEDSTROBE SIGNALFROM SOURCE
FROM DATASOURCE
REGISTER
Figure 9.1d. Eliminating the Effects of RandomPropagation Delays.
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
91
RDC-19220
8-BIT BUS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
D7
D6
D5
D4
D3
D2
D1
D0
EM
EL
INH
SERIES
(MSB)
(LSB)
Figure 9.1e. Data Transfer to 8-bit Bus.
INH
DATA 1-8VALID
DATA 9-16VALID
300 ns MAX
150 ns MIN
100 ns MAX
150 ns MAX
100 ns MAX
EL
EM
��������
������
������������
��
Figure 9.1f. Data Transfer to 8-bit Bus Timing.
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
92
RDC-19220 16-BIT BUS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
EM EL
INH
SERIES
Figure 9.1g. Data Transfer to 16-bit Bus.
INH
DATA 1-16VALID
300 ns MAX
150 ns MAX
100 ns MAX
EM, EL
���������
��
Figure 9.1h. Data Transfer to 16-bit Bus Timing.
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
93
Another large group of interface problems concernspreserving the integrity of the input signals. Figures9.2a - 9.2b illustrate several important techniquescommonly used to avoid error-inducing conditions atthe data and reference inputs of an S/D converter.
Figure 9.2a shows recommended safeguards againstthe error sources that may be introduced by long-linecabling between remote transducers and the convert-er inputs. These error sources have all been dis-cussed earlier (see page 69) and need only to be list-ed here: common-mode voltages: ground-loop sig-nals; electromagnetic pickup; and electrostatic pickup.
The remedies suggested by Figure 9.2a are as fol-lows:
• For common-mode voltage (CMV), use of a care-fully balanced isolation circuit, providing highCMRR (common-mode rejection ratio). ThisCMRR also attenuates ground-loop signals thatmay be included in the signal path.
• For electromagnetic pickup, triple-twist shieldingof the cables and the input transformer ... and pos-sibly of the entire converter, if the disturbing field isvery strong.
• For electrostatic pickup, shielding of the cables and(probably) an electrostatic shield on the transformer.
• For noise, broadly tuned bandpass filtering, withnegligible phase shift in the pass band, which iscentered on the carrier frequency.
Note that Figure 9.2a implies coupling paths that arenot normally considered in high level DC input cir-cuits, but that may become more important at 400 Hz(and its harmonics) in high-precision devices. Notealso that the best of modern S/D or R/D converterdesigns provide very well isolated, guarded and bal-anced high-impedance input circuits. Note also thatcable impedance may be a problem, if the inputimpedance at 400 Hz is too low.
Figure 9.2b shows a simple means of provided highCMRR to a resolver-to-digital converter, the input ofwhich is not well balanced. The unity-gain differential-input buffers provide balanced, high-impedance inputs,low output impedance, and excellent long-term gainaccuracy. Offsets are unimportant because the signalsare AC coupled. Note that this aid is not required if theconverter is designed with a proper input circuit.
Let us now consider two input-circuit problems fre-quently encountered in module or PC board configu-rations (and other similar high-density system con-structions), and simple means of preventing them.One concerns digital-to-analog feedback caused bycommon grounds and stray coupling, and the otherconcerns pickup of power-supply spikes (and even
VRef
CX
CMV
BALANCEDSCOTT-T
ISOLATION
R/DCONV.
VRef
TRIPLE TWISTED(12 TURNS/FT)SHIELDED INSULATEDCABLE
S/D CONVERTER
DIGITALOUTPUT
θ
ELECTROSTATICSHIELD GROUNDEDLOCALLY
CONVERTERGROUND
Vy INPUT
Vx INPUT
R
R R
R
kR1
kR1
R1-
+
-
+
-
+
k<<1
SAME CIRCUIT AS ABOVE
Vref
RESOLVER
Figure 9.2a. Ensuring Input Interface Integrity.
Figure 9.2b. Providing very high CMRR by use of additional circuitry.
(not necessary if converter is well-designed.)
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
R1
R2
S1
S2
S3
R1
R2
S1
S2
S3
ACREF
ACREF
0 - 200V
V V
Figure 9.3. Synchro Zeroing.
Figure 9.3a. Figure 9.3b.
94
ripple if high-frequency switching regulators areused) by the input terminals. The solutions involve:careful isolation of digital and analog grounds andpower-supply returns; guard buses between thepower-supply buses and the signal paths on the PCcard; and the use of wide, low-inductance paths forgrounds to which multiple returns must be made.Ground-plane (strip-line) techniques, and bypass-decoupling are sometimes advisable for bringing thelogic-level power supply into the card. Rarely, shield-ing of the card from the logic-level power-supply busmay also be necessary.
Trimming and System Setup
Assuming the individual functional modules of a syn-chro or resolver system have been individually testedfor specified performance before assembly and inter-connection into a system, the adjustment of the com-plete system should be an extremely simple matter -provided that modern, high-performance designshave been employed. Indeed, by using the best avail-able converters (which required neither zero-settingnor gain trimming), the only system adjustmentsrequired are the mechanical nulling of the synchro orresolver elements (transducers for S/D or R/D sys-tems and/or receivers for the D/S or D/R systems), byalignment, at appropriate signal conditions.
Synchro Zeroing Procedure
All that is needed to zero a synchro is an AC Voltmeterwith a 200 V scale and a 0.1 V (or less) scale.
Proceed as follows:
1. Set the shaft whose position is being measuredto its zero position.
2. Remove all connections from the synchro andconnect as shown in Figure 9.3a.
3. Unclamp synchro body and rotate until meterreads a null, then connect meter between S1 andR2 as shown in Figure 9.3b.
4. If meter reads less than the reference voltage (37Vrms for 115 Vref), the synchro is at the correctnull and you should proceed to step 5. If the volt-age is greater than the reference (193 V for 115Vref), then the synchro body must be rotated 180°and renulled using the voltmeter as in step 3.
5. Once the correct null position is determined, thevoltmeter should be set successively on lower scalesand the synchro body adjusted for the best null pos-sible. The synchro is then clamped in position.
If the functional modules used are not permanentlyzeroed and/or calibrated, the trimming can be a time-consuming and tricky procedure, because it is veryoften an interactive process ... one in which an adjust-ment at one point in the system causes a shift in theadjustment made earlier at another point. Trim proce-dures, if necessary, should be obtained from the man-ufacturer, before purchase, to determine the degree ofcomplexity before a purchase decision is made.
SYNCHRO/RESOLVER CARDS
PC-Based Test Cards
Applications using synchro-to-digital (S/D) andresolver-to-digital (R/D) converters generally requiresome form of embedded card test equipment.Having the ability to simulate and readsynchro/resolver outputs is essential in evaluatingoverall system performance. A card-based teststand offers a low-cost flexible way to handle many ofthe testing requirements technicians and engineersencounter today. Data Device Corporation (DDC)has a variety of IBM PC-based Synchro/Resolvercards to accommodate all application or testingneeds.
For low-cost multiple channel applications DDC pro-vides a full range of component-grade PC basedcards. DDC cards for applications requiring the mea-surement of position or speed are available to viewvia the DDC website for Synchro cards.
These PC cards are available in 1 arc minute accu-racy grades. With the flexibility of programmable res-olutions (10-, 12-, 14- or 16-bits) and programmablebandwidth, these cards can handle a wide variety ofapplications.
With the ability to program reference level, band-width, and resolution, the DDC cards can interfacewith applications ranging from a high-speed motor
control feedback to a precision application requiring16-bits of resolution. The line-to line-inputs can beset for 2 volt sin/cos L-L, 11.8 volt L-L or 90 volt L-Lby changing a thin-film resistor network. The I/O andvelocity signals from these cards are brought off thecircuit card through a "D" type connector mounted onthe circuit card.
For applications where angle simulation is required,DDC has cards available using the DSC-11524,DSC-11520 and DR-11525 hybrids. The DSC-1152416-bit hybrid allows you to simulate 6.8 volt sin/cos or11.8 volt L-L synchro/resolver outputs with accuracyup to 2 arc minutes. A drive capability of 15 mAallows for an external 11.8 volt L-L to 90 volt L-Lstep-up transformer to be connected to the PC (DDCP/N 51538). The DSC-11520 16-bit hybrid allowsyou to simulate 11.8 volt L-L synchro or 6.8 voltsin/cos with an accuracy up to 1 arc minute. The DR-11525 16-bit hybrid is designed for high frequencyapplications (up to 10 kHz) and will allow you to sim-ulate 11.8 volt L-L resolver or 2 volt sin/cos. Both theDSC-11520 and DR-11525 have a drive capability of2mA. For wraparound testing of synchro/resolver-to-digital converters or driving high impedance loads
95
SECTION X
RHRL
S1
S2
S3
S4
RHRL
S1 S1
S2 S2
S3 S3
S1
S2
S3
S4
34
1
18
37
19
11
1
18
37
30
19
SB-36210Series
SYNCHRO*
RHRL
S1
S2
S3S4
11
1
37
19
SB-36210Series
DIRECT
SB-36210Series
RESOLVER*
REF INGND
REF INGND
REF INGND
18
COSSIN
(GROUND)
Figure 10.1. SDC-36015 Wiring Configurations.
SYNCHRO/RESOLVER CARDS
this low cost card gives you the ability to accuratelysimulate synchro or resolver outputs.
If more drive capability is required, the DSC-36022one- to four-channel PC-based card has sockets forthe DSC-644 and DSC-544 modular digital-to-syn-chro/resolver converters. The DSC-644 series con-verter will provide 1.5 VA of drive at 11.8 V L-L syn-chro and resolver or 90 V L-L synchro. When usingthe DSC-644 modules you will also require an exter-nal ±15 DC voltage supply. The DSC-544 series willprovide 1.5 VA synchro 90 V L-L at 60 Hz (-I version)or 4.5 VA at 90 V L-L at 400 Hz (-H version). This isa reference powered digital-to-synchro converter thatwill provide accuracy up to 4 minutes with no exter-nal DC power supplies required. See Figure 10.2.
96
RH
RL
S1
S2
S3
RH
RL
S1
S2
S3
RH
RL
S1
S2
S3
RH
RL
S1
S2
S3
17
35
36
18
37
17
35
36
18
37
19S4 S4
R/D CONVERTER
S/D CONVERTER
DSC-36022CHANNEL1RESOLVER
DSC-36022CHANNEL1SYNCHRO
WHEN USING DSC-644 MODULE YOU MUST CONNECT ±15 VOLTS TO THE 37-PIN "D" CONNECTOR
SEE DATA SHEET FOR ADDITIONAL CHANNELS
(with DSC-544 or DSC-644) (with DSC-644)
Figure 10.2. DSC-36022 Wiring Configurations.
Providing a low-cost alternative to bench top instru-ments gives today's engineer the tools to properlyevaluate systems at the component level reducing thecost impact when systems are tested at higher levelsof integration and problems are found. Visit DDC’swebsite for a complete listing of PCI, ISA, PC-104,PMC and VME cards.
Software, such as Windows, GUIs, Labview, Linux,and DataSims can be downloaded from DDC's web-site at www.ddc-web.com, or obtained through DDC'sApplications Engineering Department.
APPLICATION TIPS AND EXAMPLES
In this section we will illustrate a combination of tra-ditional applications of synchro and resolver convert-ers and how the increased functionality of the newgeneration of converters can be applied to solvingsystem needs.
Example #1: Coordinate Transformation (Polar toRectangular)
Figure 11.1 shows a very useful and fundamentalapplication of a synchro transducer and converter: toresolve a polar vector into rectangular-coordinatecomponents. One typical application might be indoing studies of temperature, salinity, conductivity,PH, or other physical or chemical gradients or distri-butions in a test tank by scanning a probe around afixed-diameter path, one full revolution at each ofseveral regularly-speeded test times after the initialexcitation of the phenomenon being measured. Theoutput of the probe is then fed to the inputs of a pairof analog multipliers, one of which is also fed the sinθoutput of the DC-coupled D/R, and the other of which
is fed the cosθ output of the D/R. Thus, the multipli-er outputs are proportional to the X and Y coordi-nates of the vector representing the sensed parame-ter at the scanning angle θ. These outputs drive thex and y deflection yokes of a storage oscilloscope (orthe inputs of an X-Y recorder). If there is to be a one-second scan every 20 seconds, the maximum accu-rate tracking rate required is 360°/sec or 1 rps.
Note that it is essential that the sine and cosine out-puts be DC level; that they both be bipolar (four-quadrant); that they be free of spikes or other tran-sients; and that they be independent of the refer-ence-carrier frequency and amplitude (over a rea-sonable range) and of the scale factor of the CT.
Example #2: Using an S/D in the CT Mode in aServo System
One of the most straightforward applications of anS/D converter in a servo system application is shownin Figure 11.2. In this application, changes in posi-
97
SECTION XI
Figure 11.1. Polar-to-Rectangular Conversion.
CX
ErefSYNCHRO-TO-DIGITAL CONVERTER
Es
SHAFTCOUPLED
TO SEARCHPROBE
EMF GENERATEDBY PROBE
RfRin
10 Cosθ
10 Sinθ
E1 = Es (Rf/Rin)
M
M10 E1 COSθ
10 E1 SINθ
K
K
Ix = 10K E1 Cosθ
DEFLECTIONCOILS OF
CRT DISPLAY
Z Cosθ
Z Sinθ
Iy = 10K E1 Sinθ
T5
T4
T3T2T1
θ
θZ
DIGITAL-TO-SINE/COSINECONVERTER
APPLICATION TIPS AND EXAMPLES
tion are commanded by the computer through sig-nals fed to the solid-state CT, or Control Transformer.The synchro is measuring the current position (θ),and the computer is writing the new position (φ) tothe CT (an S/D in the CT mode). The output is e = sin(θ-φ). The CT then drives the positioningmotors through DC power amplifiers.
Example #3: Using the Velocity (VEL) Output toStabilize a Position Loop
With a tachometer quality output, the VEL of thenewer generation of S/Ds and R/Ds can be used tostabilize a position servo and thereby eliminate thetraditional tachometer and its gears. Figure 11.3shows the block diagram of such an application.Quite high performance can be achieved in such sys-tems by taking full advantage of the reference fre-quency and bandwidth programmability of the newerconverters.
Example #4: Interfacing an S/D or R/D with anIBM PC
An S/D can be connected to an IBM PC through theIBM PC or PCI bus located at address HEX 300through 303. This location is reserved by the PC forinterface cards. Figure 11.4 illustrates the timingconsiderations for the interface; Figure 11.5 illus-trates the connection to the IBM PC bus.
Operation is as follows:
1. The port address where the S/D or R/D is locatedis hard wired with jumpers into the 74LS688address decoder. This address is HEX 300through 303 and is reserved for prototype cards.
2. Address line A1 selects the upper or lower 8 bitsof the S/D or R/D to be placed on the bus. WhenA1 is high, bits 1-8 are selected and when A1 islow, bits 9-16 are selected.
3. Address line A0 sets and resets the S/D or R/DINHIBIT line. When A0 is low, the INHIBIT com-mand (INH) is invoked or the digital data is frozen.
4. To read the output of the S/D or R/D, perform thefollowing:
a. Send address HEX 302 to INHIBIT the S/D orR/D (hold data stable) and place bits 1-8 on thebus. Read and store data on D0 to D7.
98
Figure 11.2. CT Mode Application.
SYNCHRO
AMP
DEMODULATORSDC-19204 or SDC-14560as a CT
µ COMPUTER
REFe = sin (θ − φ)
S
φ
θ
Figure 11.3. S/D with VEL to Stabilize Position.
D/A COMPUTERS/D OR R/D
CONVERTER
REFSOURCE
VEL
AMP
SYNCHRO OR RESOLVER
Figure 11.4. PC Application—I/O Read Cycle Timing.
LATCH READ DATA
OUT
OUT
OUT
IN
OUT
VALID ADDRESS
500nsec MIN PULSE
CLK
ALE
ADDR
I/OREADY
I/O R
APPLICATION TIPS AND EXAMPLES
99
Figure 11.5. S/D Converter to PC Connection Diagram.
BIT 16 (LSB)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A9
A8
A7
A6
A5
A4
A3
A2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
IBMBUS
BUS DRIVER74LS465
ADDRESSDECODER74LS688
ADDRESSSELECTIONJUMPERS
74LS374
74LS467
SDC-19204/674LS121
Q
A2
INH
ELEM
Q CLK
D
Y1 Y2 Y3 Y4
A1 A2 A3 A4
G
G P=Q
ALE
I/O READ
G
A1
A0
I/O READY
3 STATEBUFFER
500 nSEC MINPULSE
P0
P1
P2
P3
P4
P5
P6
P7
A1
A2
A3
A4
A5
A6
A7
A8
APPLICATION TIPS AND EXAMPLES
100
b. Send address 300 HEX to keep the S/D orR/D in the INHIBIT mode and place bits 9-16 onthe bus. Read and store data on D0 to D7.
c. Read address 301 HEX or 303 HEX torelease the S/D or R/D from the INHIBIT mode(allow data to track) and prepare for the next mea-surement. No valid data will be on the bus duringthis command.
5. Since the output data is not valid until 0.5 µs afterthe INHIBIT command is invoked, the I/O READYline is held low for this period of time. When I/OREADY returns to the high level, the data on thebus reads on the next negative clock edge.
Example #5: Using BIT or “Low Glitch Switch onthe Fly” to Speed Up Slew Rate
In many servo systems it is desirable to slew to agiven point very quickly and then track with someconflicting requirements since there is usually atrade off to be made between high speed and highprecision in a servo system. With the new R/Dsoffering pin-programmable resolution and a BIT(Built-in-Test) output you can have the best of bothworlds. By using the BIT signal to lower the resolu-tion the converter can slew faster and with more pre-cision automatically as the need to slew fast disap-pears.
Note that when the resolution is changed the analogvelocity (VEL) scaling also changes and since theVEL output is from an integrator with a capacitorfeedback, the VEL cannot change instantaneously.Therefore, when changing resolution while movingthere will be a transient with a magnitude propor-tional to the velocity and a duration determined bythe converter bandwidth.
Switch Resolution On The Fly – Implementation
For applications that cannot tolerate the glitch inposition and velocity, switching resolution on the flyshould be used. The RD-19230 will track four timesfaster for each step down in resolution (i.e., a stepfrom 16 bits to 14 bits). The steps for using the sec-
ond bandwidth in the RD-19230 for switching resolu-tion on the fly are as follows:
1.The SHIFT pin should be tied to the resolution con-trol line D0. For a set up with 100Hz bandwidth (RB
= 30k ohms and CBW = 0.033 µF), the delay for theshift line is 250ms maximum. When shift is logichigh, the VEL1 components are chosen, and whenshift is logic 0, the VEL2 components are chosen.
2.The second set of BW components (CBW2, RB2,CBW2/10) should be of the same value as the firstset of BW components (CBW1, RB1, CBW1/10). Thissecond set of components should be installed onVEL2 and VEL SJ2.
Note: The bandwidth components must be cho-sen so that the tracking rate to BW ratio is notexceeded for the resolutions that will be used.
3.Connect RV between VEL and -VCO.
4.UP/DN will program the direction of the gain. Priorto switching the resolution, the user must programthe direction. If the resolution is increasing (UP/DNlogic 0), the gain will be increased by a factor offour. If the resolution is decreasing (UP/DN logic 1), the gain will be decreased by four(or decreased to one fourth).
For example:
If the application required a switch between 14- and16-bit resolution only, the following five steps couldbe followed:
i) The shift pin should be tied to the resolution con-trol line D0 and the D1 resolution control lineshould remain a logic high. On initial turn-on, theD0 and shift line would be set to a logic low for 14-bit mode. The second set of bandwidth compo-nents (CBW2 RB2, CBW2/10) will be active.
ii) From 14-bit resolution the application is requiredto increase the resolution to 16-bits. The gain isthen required to increase. The UP/DN pin shouldbe set to a logic low.
APPLICATION TIPS AND EXAMPLES
101
iii) When the condition requiring the higher resolu-tion is met, the D0 and shift line will be set to alogic high for 16-bit mode. The first set of band-width components (CBW1, RBW1, CBW1/10) will beactive.
iv) The next option in the application is to switchback to 14-bit mode. The UP/DN pin should be setto a logic high to prepare the second set of band-width components for a decrease in resolution.
v) When the condition requiring the lower resolutionis met, the D0 and shift line will be set to a logiclow for 14-bit mode. The second set of bandwidthcomponents (CBW2, RBW2, CBW2/10) will be active.
Benefit of Switching on the Fly
Figure 11.6 shows a system at a constant velocitythat changes to a higher resolution. The signals thathave been recorded are:
1. VEL: velocity output pin on the RD-19230
2. DAC: this is the analog representation of the errorbetween the input to the digital-to-resolver converter and the digital output of the RD-19230
3. D0: an input resolution control line to the RD-19230
4. BIT: built-in-test output pin of the RD-19230
When this system type does not use the switch res-olution on the fly implementation, the velocity and thedigital position data response is similar to theresponse caused by a large step (179 degree step -refer to Figure 11.6). Since this is a type II trackingloop, the system will:
1 - overshoot the correct value2 - approach the correct value3 - overshoot the correct value again4 - then settle to the correct value
The overshoot will develop a large error [SIN(θ−φ)] inthe converter. This error will exceed 100 LSBs caus-ing the BIT to flag for a fault condition.
When this system uses the switch resolution on thefly implementation, the velocity signal and digitalposition data make a smoother transition similar tothe response caused by a small step (refer toFigure 11.6) and the BIT does not indicate a faultcondition.
Figure 11.6. “Switching On The Fly” Signal Comparisons.
0V
-5V
0V
5V
0V
5V
0V
VEL
DAC
D0
BIT
0V
-5V
0V
5V
0V
5V
0V
VEL
DAC
D0
BIT
50msec per division 50msec per division
Without switching Resolution on the Fly Implementation With switching Resolution on the Fly Implementation
APPLICATION TIPS AND EXAMPLES
102
Example #6: Using Major Carry (MC) andDirection (U) in Multiturn Applications
The MC and U lines of some S/Ds or R/Ds canbe used in multiturn applications as shown inFigures 11.7 and 11.8. The MC signal is similarto the four-bit up-down counter CO (Carry OUT),that is, it is normally high and goes low for all 1'swhen counting up or all 0's when counting down.The Direction Output, U, is at a logic 1 to countup and a logic 0 to count down. The logic levelat U is valid at least 0.5 µs before and at least 20 ns after the leading edge of CB (ConverterBusy).
Example #7: An On-Line Self-Test
In some systems the internal BIT (Built-in-Test) func-tion of an S/D or R/D is not adequate and an addi-tional level of built-in-test is required. One approach,shown in Figure 11.9, is to connect a solid-state CT(SSCT) to the input and output of the S/D or R/D andmonitor the Error Output (e) with a threshold detec-tor. The SSCT inputs are the analog input angle θand the S/D output angle (digital) φ. The AC erroroutput (e) will be the difference, or more exactly sin(θ - φ). The threshold detector must be set con-sistent with the accuracy of the S/D or R/D, the SSCTand the expected transient errors due to acceleration
UP/DOWNCOUNTER
C0C1
MC
U
CB
U T
SDC-19204 OR RDC-19200
4 BITS
TURNS COUNTING
Figure 11.7. Turns Counting Connection Diagram.
� �����DIRECTION (U)
0.5 μs MIN
MAJOR CARRYMC
�DON'T CARE
UPCOUNT
DOWNCOUNT
20 ns MIN0.5 μs MIN
0.5 μs MIN
0.5 μs MIN
CB
0.5 μs MIN
Figure 11.8. Direction Output (U) Timing.
DIGITALCOMPARATOR
B.I.T.E.OUTPUT
REF
DIGITALINPUT
D/S OR D/RCONVERTER
S/D OR R/DCONVERTER
REF
S3S1 S2
ANALOG OUTPUT TO SYSTEM
S4
Figure 11.10. On-Line Self-Test for D/S.
S/D (OR R/D)CONVERTER
SSCTCONVERTER
THRESHOLDDETECTOR
AC ERROR
S1
S2
S3
DIGITALOUTPUT
TO SYSTEM
B.I.T.E.OUTPUT
REF
ANALOGINPUT
S4
θφ
sin (θ − φ)
Figure 11.9. On-Line Self-Test for S/D.
APPLICATION TIPS AND EXAMPLES
103
D/RCONVERTER
POWER AMPLIFIERS
Vy
Vx
-+
-+
MULTIPLERESOLVERS
Figure 11.11. Boosting Output of D/R Converter.
D/SCONVERTER
10k
10k
10k
10k
Vref
TORQUE SYNCHRO
Figure 11.12. Using Two Power Amplifiers to Drive aThree-Wire Synchro from a D/S Converter.
in the system. The advantage of this scheme is thatit is on line and monitors continuously.
A similar scheme can be implemented for D/S or D/Rconverters as shown in Figure 11.10. Here, the D/Sor D/R is followed by an S/D or R/D and a digitalcomparator. The same factors must be taken intoconsideration here too. Also, be careful to allowenough settling time for the S/D or R/D, particularlyin the case of step inputs.
Example #8: Boosting the Output of D/S and D/R Converters
Figure 11.11 shows the use of differential operationalamplifiers to boost both the average and the peakpower capabilities of a digital-to-resolver converter.(The same amplifiers may be used to boost the out-put capabilities of digital-to-synchro, synchro-to-DCand synchro-to-sine/cosine DC converters). Modernsynchro-drive amplifiers are generally available withoutput voltage ranges up to ±90 Volts, at voltamperelevels as high as ±25 VA. They are especially wellsuited to driving multiple synchros.
It is important to note that not all high power ampli-fiers are suitable for use as synchro driversbecause of the low power factor of the load. In dri-ving a highly inductive load, most of the real powermust be dissipated in the amplifier, since the cur-rent levels and phase shifts can be quite high.Another important consideration is overload pro-tection and/or current limiting. If a synchro torque
receiver (TR) locks up at 180° from the D/S con-verter angle, the TR essentially acts as a generatoraiding the D/S converter output rather than buckingit as it does in normal operation. In this situationthe amplifier will be called upon to drive the resis-tive portion of the TR's impedance (ZSO) and toabsorb an additional equal current from the TR.Some form of protection is very desirable in this sit-uation to prevent burning out the amplifiers and/orsynchro.
Figure 11.12 shows how two external power ampli-fiers may be used to drive one or more three-wiresynchro receivers in parallel (or a high-power torquesynchro). This is possible because of the Y-connec-tion configuration of the synchro receiver stator wind-ings. It can be shown that supplying the high-levelenergy to two of the three input lines, and directlyconnecting the third (ground is the common connec-tion) is just as effective as using three power boost-ers. One word of caution: do not allow the ground-return current from the third terminal to flow throughany of the low-level analog-circuit ground paths -e.g., the ±15 V power-supply common. Instead, con-nect the third synchro input directly to the third out-put terminal on the D/S converter, and ground thatthird output terminal to common.
Caution: Modular D/S converters that have trans-former isolation on the output may have one out-put tied to ground; hybrid D/S converters thathave amplifier outputs cannot have one outputtied to ground—damage to the hybrid may result.
APPLICATION TIPS AND EXAMPLES
104
MASTERMOTOR
SLAVEMOTOR
S/D OR R/DCONVERTER
SSCTCONVERTER
SHAFT #1 SHAFT #2
Cx Cx
REF
MOTORCONTROLLER
PHASESENSITIVEDETECTOR
SHAPINGCIRCUIT AMP
ACERROR
START-UPCIRCUIT
e
REF
Figure 11.13. Synchronizing Two Shafts.
Figure 11.14. Synchronizing Two Shafts (method # 2).
MASTERMOTOR
SLAVEMOTOR
S/D OR R/DCONVERTER
S/D OR R/DCONVERTER
SHAFT #1 SHAFT #2
Cx Cx
REF
µP
MOTORCONTROLLER
D/ACONVERTER
SHAPINGCIRCUIT AMP
REF
Example #9: Synchronizing Two Rotating Shafts
In some applications the phase and speed ofremotely located shafts must be synchronized as ifthey were locked together by gears. This can beaccomplished in two ways.
The first is shown in Figure 11.13. In this methodone shaft (the master) has a CX and S/D or R/Dwhile the other has a CX and a SSCT. The output ofthe master S/D feeds the digital input of the SSCT
whose analog input is the slave shaft CX. The SSCToutput will now be the difference of the input angles,AC Error (e). This is for use in driving the slave shaftmotor. A separate start-up circuit is needed becausethe output of the SSCT is only linear over a smallangular range, usually about 10-12 degrees.
The second method is to simply use two S/Ds orR/Ds, a µP and a D/A as shown in Figure 11.14. Theadvantage of this scheme is the simplified start upsynchronizing because the µP can bring the speeds
APPLICATION TIPS AND EXAMPLES
105
into sync first, then the phasing. Additionally, thehardware implementation is simplified. Thisscheme can also be used to control speed differ-entials between remotely located shafts. Thisprovides great flexibility since all variations from sys-tem to system or job set-up to job set-up are com-pletely under software control while the hardwareremains constant.
Example #10: Using an R/D With an Inductosyn
Figure 11.15 shows how some of the new wide-bandwidth R/Ds, such as the RDC-19220 series, canbe used as an inductosyn-to-digital converter. TypeII tracking converters are excellent for inductosynapplications because of their noise immunity, negligi-ble drift, and fresh data.
In adapting an R/D to an inductosyn a few key pointsmust be kept in mind. Although conceptually quitesimilar, the resolver is an inductive device whereasthe inductosyn is resistive; phase shift through aresolver is generally minimal whereas the phase shiftthrough an inductosyn is substantial; resolver signals
are high level whereas inductosyn signals are lowlevel. As long as we keep these differences in mindthere should be no surprises.
In using an R/D you should treat the inductosyn as aspecial case resolver. Excite the fixed scale as if itwere the reference but excite it with a current sourceso the phase will be fixed. See the manufacturersrecommendations for the proper level. To compen-sate for the phase shift through the inductosyn,phase shift the reference input to the R/D converter.The output of the slider will be in sin/cos format butat a very low level, in the 20 mV range. Since theR/D needs on the order of 2.0 volts, it must be ampli-fied to that level by a pair of matched gain amplifiers.These should be kept as close to the slider patternas possible due to the low level of the signals. Theoutputs being higher and having low impedance candrive the cable to the converter better. The actualgain required of the amplifier will vary depending onthe inductosyn, its level of excitation and the spacingof the scale and slider. Actual gain is not critical butthe two amplifiers must be matched and track overtemperature.
Figure 11.15. Inductosyn-to-Digital Converter.
RESOLVER-TO-DIGITAL
CONVERTERDIGITAL
OUTPUT
DUAL MATCHED
INDUCTOSYNPREAMPS
INDUCTOSYNSCALE
QUADRATUREPOWER
OSCILLATOR
SHIFT90 PHASE0
QUADRATUREOUTPUT
INDUCTOSYNSLIDER
RH RL
CHASSIS GROUND
CIRCUIT GROUND
2 Vrms
RDC-19220SERIESOSC-15801
APPLICATION TIPS AND EXAMPLES
106
Example #11: A 7 VA Power Amplifier for DrivingSynchros
In some applications a little more drive capabilitythan is available in the 5 VA output of the DSC-10510is required or desired. In cases like this it is recom-mended you use either the DSC-11520 or DSC-11522 low power (2 mA) D/S converter with a sepa-rate power amplifier as shown in Figure 11.16. Thiscircuit can drive up to 7 VA and can be used for either11.8 V L-L or 90 V L-L applications.
Note: DDC’s DSC-10510 will drive 7 VA for 11.8 VL-L.
The op amp is rated at 1 Amp peak and will provideup to 7 VA output driving an 11.8 V synchro with aZso as low as 15 Ohms (similar to the UA791KM thatis no longer available). If transformer isolation isrequired use DDC's P/N 18883 for 11.8 V output,
18884 for 90 V 400 Hz, and 18885 for 90 V 60 Hz.With these 90 V transformers you can drive a Zso aslow as 868 Ohms.
If resolver format output is required use the sin/cosoutputs of the converter and the circuits shown inFigures 11.17 and 11.18. Figure 11.17 is a straightunity gain buffer giving an output of 6.8 Vrms whileFigure 11.18 gives 11.8 Vrms output.
Example #12: A Solid-State Scott-T
Figure 11.19 shows a solid-state Scott-T amplifieruseful for adapting an R/D converter to an 11.8V syn-chro application. It converts the synchro signals S1,S2 and S3 to the direct input resolver format signalssin and cos. The accuracy of this Scott-T is deter-mined by the match of the resistors R1 through R9.This circuit presents a light but unbalanced load to thesynchro and, for this reason, should not be used in
Figure 11.16. 7 VA 11.8 V 400 Hz Synchro Driver.
DSC-11520
RH
RL
DIGITALINPUTS
32
34, 35
6
5
10
3
2
1
4
9
+15V
R1C1
-15V
6
5
10
3
21
4
9
+15V
R1C1
-15V
+
–
+
U1
U2
+15V
GND
-15V
C7
C7
+
+
R2
R2
C2
6
5
10
3
2
1
4
9
+15V
R1C1
-15V
+
U3R2
C2
C2
S2
S3
S1
S1
S2
S3
TA
TB
1
2
3
4
5
6
7
8
9
10
OUTPUT TRANSFORMERSECTIONS TA AND TB
(OPTIONAL)
11.8VSYNCHROOUTPUT
11.8VL-L
33, 36
–
–
1:1 GAIN
COMPONENTS
U1, U2, U3 OP-AMP WITH CHARACTERISTICS OF UA 791KM (NOTE: THE UA 791KM IS OBSOLETE)C1 100PF, 10% CERAMICC2 3300PF, 10% CERAMICC7 10µF, 35 VDC, TANTALUMR1 3.9Ω, 5% CARBON COMPOSITIONR2 1.0Ω, 1W, 5% CARBON COMPOSITION
APPLICATION TIPS AND EXAMPLES
107
Figure 11.17. 7 VA 6.8 V Resolver Power Amplifier.
DSC-11520
RH
RL
DIGITALINPUTS
35
33
36+COS
6
5
10
3
21
4
9
+15V
R1C1
+COS
+SIN+SIN
-15V
6
5
10
3
21
4
9
+15V
R1C1
-15V
+
–
+
U1
U2
+15V
GND
-15V
C7
C7
+
+
R2
R2
C
C
–
1:1 GAIN
Figure 11.18. 7 VA 11.8 V Resolver Power Amplifier.
6
5
10
3
2
1
4
9
+15V
R1C1
-15V
+R
6
5
10
3
21
4
9
+15V
R1C1–
+R2
+SIN
C4
C4
S3
S1
7.33k*
6
5
10
3
21
9
+15V
R1C1
+R2
6
5
10
32
1
9
+15V
R1C
+R
C5
7.33k
U4
U2
U1
U3+COS
-15V
-15V
-15V
DSC-11520
DIGITALINPUTS
RH
RL 35
33
36
10k*
–
–
–
C6
S2
S4
10k*
* RESISTORS TO BE BALANCED TO WITHIN 0.025%
4
4
APPLICATION TIPS AND EXAMPLES
108
Figure 11.20. Replacing an Incremental Encoder with a Resolver or Synchro.
LSB +1
LSB
EL
-5 V
RDC-19220
CB/NRP
R12k
D11N4148
C1220 pF
4
5
C2220 pF
13
12
C3120 pF
9
10
R22k
U2A74AC86
2
1
A
B
NRP8
6
11
3
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL COMPATIBLE LOGIC WILL SKEW THE DELAYS.
U2D74AC86
U2B74AC86
U2C74AC86
R32k
Figure 11.19. A Solid-State Scott-T.
R1
R2
R3
R4
R5
R6
R8
R7
S1
S2
S3
INPUT
+SIN
+COS
OUTPUT
+
–
+
R9
–WHERE:SIN ~ S3 – S1
COS ~ [ S2 – ( )] S1 + S32
2√3
FOR THE GENERAL CASE:R1 = R2 = R3 = R4R5 = 1/2 R1R6 = R7 = R8 = R9
FOR 11.8 V INPUT AND 2.0 VRMS OUTPUT:R1 = R2 = R3 = R4 = 23kR5 = 11.5kR6 = R7 = R8 = R9 = 8k
APPLICATION TIPS AND EXAMPLES
109
combination with series dropping resistors. The val-ues given in the figure are for an 11.8 V synchro to 2.0 V resolver configuration suitable for adapting anR/D (such as DDC's RDC-19202, RDC-19220 series,or RD-19230 converter) to a synchro application. Bychanging the feedback and input resistor values mostline-to-line values can be accommodated.
Note: DDC suggests that the resistor tolerances arematched to within 0.02%.
Example #13: Replacing an Incremental EncoderWith a Synchro or Resolver
In updating older systems many designers would liketo replace an incremental encoder transducer toimprove reliability and maintainability. At the sametime they would like to retain as much of the existingcircuitry as possible for economic reasons. One wayto accomplish this is shown in Figure 11.20. Herethe synchro or resolver feeds a standard new gener-ation R/D converter. The Converter Busy is changedto the zero index or north marker pulse while the in-
phase and quadrature signals are derived from theLSB and next LSB as shown.
DDC’s latest RD-19230 monolithic R/D converterprovides the incremental encoder signals without theaddition of external circuitry (see Figure 11.21). TheRD-19230 allows you to program the resolution ofthe A and B lines independently of the digital angledata. Please refer to the RD-19230 data sheet foradditional information.
Example #14: A Binary Two-Speed Converter
Figure 11.22 shows a 1:32 two-speed S/D imple-mented with two single-speed tracking S/Ds. Theoutputs of the fine speed S/D are brought out direct-ly but shifted in bit value by the speed ratio. That is,all the bits are shifted by 1/32 (the MSB becomes the6th bit and the LSB becomes the 19th). The coarsedata provides the rest of the MSBs with the 5483 pro-viding the crossover ambiguity correction based oncomparing the two MSBs of the fine speed data withthe two overlapping bits of the coarse speed data. Ifthe bits match, the coarse data is correct and is used
Figure 11.21. Incremental Encoder Emulation Resolution Control.
RD-19230
1 MSB234
9 101112131415BIT 16 LSB
B
10
12
14
16
A
5678
APPLICATION TIPS AND EXAMPLES
110
for the 1 through 5 MSB outputs. If the fine is 1 LSB larger than the coarse then 1 LSB correction isadded to the coarse data. The premise is that thefine speed synchro defines the position and thecoarse synchro really just keeps track of which revo-lution the fine speed synchro is on, in effect justcounting turns. If the difference is greater than 1 LSBthe system is out of sync or a failure has occurred.See Two Speed Theory figure 2.16.
Example #15: Single Axis Servo Interfacing to aMotorola 6809 µP
Whereas some of the components in this examplemay no longer be available, the example is still listedfor the purpose of understanding the technique ofinterfacing with a microprocessor. Please note thatthe newer R/D converters have a 16-bit parallel wordavailable through a 16-bit bus. Figure 11.23 illus-
trates a simplified block diagram of a single axis µPbased position servo while Figure 11.24 shows theinterface to Motorola's 6809 in detail. The diagramalso indicates a significant economy of resolverbased feedback: both position and velocity informa-tion are readily derived from the same transducer.DC velocity feedback information is developed intrin-sically in the R/D converter as part of the conversionprocess. In addition to being necessary in situationswhere velocity and acceleration are to be tightly con-trolled, velocity feedback is used in the two mostcommon digital control algorithms: "minimum-time"or "bang-bang" control and proportional-integral-derivative (PID) control.
Figure 11.25 illustrates the classical block diagramfor a "minimum-time" or "bang-bang" type positioncontrol scheme. In this particular example, it isassumed that the dynamics of the motor and
Figure 11.22. Binary Two-Speed S/D.
COARSES/D
CONVERTER
COARSESYNCHRO
S1
S2
S3
C1
C2
C3
C4
C5
C6
C7
B3
A3
A2
B2
A1
B1
A3
B4
A4
A2
B2
B3
A1
B1
COE2
E3
E4
1/6 5404
1/6 5404
1/6 5404
E4
E3
E2
E1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
FINES/D
CONVERTER
S1
S2
S3
FINESYNCHRO
DIGITALOUTPUT
5483
5483
APPLICATION TIPS AND EXAMPLES
111
Figure 11.24. Resolver to 6809 µP Interface.
REFERENCEOSCILLATOR RESOLVER
DIFFERENTIALAMPLIFIER/
FILTER
LM311
10k
5k
+15V
100k
+5V
5k
V
100
RH
RL
S1
S1
S3 S3
S2S2
S4
S4
RH RL +15V
+15V +5V
VL
ENM
BITS 1~6
INH
ENL
BITS 7~14
VEL Ve
SDC-14565
.1
8-BITA-D
CONVERTERFILTERED
DC VELOCITY
E.O.C.S.C.
CB2
CA2
CS DO-07
6821
CA1 CB1PB0~PB7
RDL BIT
A13~A15
6809
E
Q
D0~D7
Y1
Y2
Y3
74LS138
A-B-C
G
+ –
+
–
.1
Figure 11.23. Single-Axis Position Servo.
POSITIONSETPOINT
MICROPROCESSORROM, RAM, 510
D-ACONVERTER
POWERAMPLIFIER MOTOR GEARING LOAD
POSITION ENCODER
VELOCITYFEEDBACK
APPLICATION TIPS AND EXAMPLES
112
Figure 11.25. “Bang-Bang” Motion Controller.
CONTROLLERMOTOR AND LOAD
e
e
e
eru = +|Imax|
u = ± |Imax| Ktj
IS
IS
VELOCITY FEEDBACK
POSITION FEEDBACK
XX
–
+
u = – |Imax|
–1
± |Amax|.
.
.
mechanical system loading may be accuratelymodeled as a double integrator. That is, itassumes that the overall load on the motor ischiefly inertial, with rotational inertia J, a reason-ably close approximation in many applications, byapplying either full accelerating torque or full decel-erating torque, the servomotor's load may be pro-grammed to travel from its origin to destinationpoints in minimum time. The control law for such asystem would be:
Where | Amax | = +KT | max/J |; KT is the motortorque constant. Note that for this control law, themotor current may assume only the two limiting val-ues of ±| Imax. | resulting in corresponding accelera-tion of ±| Amax. |.
It is important to note that accurate velocity feedbackis an essential ingredient in this design. Using a
+ | Imax | if e ≤ 0 and e > + e2 / 2 | Amax. | or e > 0 and e ≥ – e2 / 2 | Amax. |
IMOTOR = – | Imax | if e < 0 and e ≤ + e2 / 2 | Amax. | or e ≥ 0 and e < – e2 / 2 | Amax. |
. .
. .
. .
. .
direct speed measuring device such as a DCtachometer provides accurate, fresh velocity infor-mation, but it entails the use of an additional electro-mechanical part and an A/D converter. A similarquality signal is available in new generation S/D andR/D converters. A low-pass filter to eliminate carrierripple followed by a low-cost A/D converter can beused to interface this velocity output to the µP.
Along with the "bang-bang" type of control, the othertype of digital position control algorithm commonlyused is the PID technique. With this scheme, themotor command signal is derived from the raw errorsignal, and its digitized time derivative and integral.The relative amounts of the three terms are general-ly tuned on-line to optimize loop response. The pro-portional term, modified by the derivative term fordamping, constitutes the essential control law fortranslating between set-point positions. The integralterm provides a measure of stability near the nulland compensates for long-term disturbances suchas static friction. Dynamic response is oftenimproved by clamping the integral term to zero dur-ing periods of motion, allowing it to come into playonly when the loop is near null.
The PID type control law, while not providing a mini-mum time response as in the "bang-bang" system,offers the advantages of improved accuracy as well
APPLICATION TIPS AND EXAMPLES
113
as superior stability (jitter-free) near the error null. Itshould be emphasized, however, that both algo-rithms require a source of fresh, accurate angularvelocity feedback as well as the encoded positionfeedback. In some advanced controller schemes,the two algorithms are combined, reaping the advan-tages of both. The "bang-bang" law is used for thelarge step changes; the PID control law is then uti-lized near the error null.
Example #16: Interfacing a Microprocessor to aMultiturn Positioning Servo
In an increasing number of applications, it is desir-able to use multiturn as opposed to single-turn posi-tion feedback. An example of multiturn measure-ment is a screw-down system on a steel rolling millas illustrated in Figure 11.26.
The essential advantage of multiturn position mea-surement is that it provides improved resolution andtherefore improved accuracy over single-turn sens-ing. A second advantage is that it eliminates the
need for a reducing gearbox in applications such asthe screwdown, where single-turn position is notinherently available. The principle disadvantage isthat it is "absolute/incremental" rather than"absolute/absolute." That is, at any given time, thesingle-turn shaft position is known exactly (absoluteposition), but the turns count must be maintained bycounting full revolutions of the input shaft angle(incremental measurement). This turns-countingfunction may be implemented in either hardware orsoftware.
The primary disadvantage is that if there is amomentary loss of power in either the transducer,converter or counting electronics the turns countmay be lost. In addition, software turns-counting hasthe added disadvantage of limiting the maximumpermissible angular shaft speed (in rps) to one halfthe system sampling rate. If this speed is exceeded,one or more turns counts can be missed. Wherethese constraints are not limiting the multiturnscheme offers distinct economic benefits.
Figure 11.26. Multiturn Position Interface.
DCMOTORDRIVE
DCMOTOR
SPEEDREDUCINGGEARBOX
RESOLVERTRANSDUCER
REFERENCEOSCILLATOR
R-DCONVERTER
TURNSCOUNTERS
TRI-STATE
BUFFER
INH
EN
MICROPROCESSOR-BASED
NUMERICALPOSITION
CONTROLLER
D-ACONVERTER
SUPERVISORYCONTROL
COMPUTER
DIRECTIONOF
SCREWDOWNTRAVEL
MOVINGROLLER
CB C U
DIRECTION OFSTEEL WEB TRAVEL
FIXEDROLLER
SCREW-DOWNAPPARATUS
APPLICATION TIPS AND EXAMPLES
114
Figure 11.27. Block Diagram of a Typical Synchro/Resolver-to-DC Converter.
SIN
COS
-S+S
+C-C
RBW
RH RH
RLRL
+5 V
0.1 µF 0.1 µF
+15 V
VOUTVOUT
+VCC
BIT 1 (MSB)
BIT 16 (LSB)
COMMON-VCC VDD
+5 V-15 V
0.1 µF
-5 V
AGNDGND
BIT 1 (MSB)
BIT 16 (LSB)
RDC-19220 SERIES
BURR BROWNDAC 703ENL
ENM
B
-VCO
VEL
-VSUMCBWCBW
10 RBW
RV
NOTES: 1. CONCEPT DRAWING. SEE MANUFACTURERS' DATA SHEETS FOR COMPLETE INFORMATION. 2. RH AND RL ARE SWAPPED TO PROVIDE 2'S COMPLEMENT OPERATION. NORMAL WIRING OF RH AND RL PROVIDES OFFSET BINARY OPERATION.
A +5 V
A
AC error (e) 20, 63, 102, 104acceleration error 21, 71-72acceleration lag 74accuracyabsolute 2, 78, 79, 88relative 70, 79active loads 57amplifierpower 50, 52, 59, 65, 67amplifier mismatch 88amplifier, power 88, 98, 103, 106, 107amplifier, power boosting 57, 59, 103amplifier, signal boosting 65, 103, 106amplitude error 83analog-to-digital conversion 77angular error 21, 52, 59applications, for synchro and resolver systemsa 7 VA power amplifier for driving synchros 106a binary two-speed converter 109a solid-state Scott-T 106boosting the output of D/S and D/R converters 103coordinate transformation (polar to rectangular) 97interfacing a microprocessor to a multiturn positioning servo113interfacing an S/D or R/D with an IBM PC 98on-line self-test 102replacing an incremental encoder with a synchro or resolver109single axis servo interfacing to a Motorola 6809 µP 110synchronizing two rotating shafts 104using an R/D with an Inductosyn 105using an S/D in the CT mode in a servo system 97using BIT or low glitch switch on the fly to speed up slew rate100using major carry (MC) and direction (U) in multiturn applica-tions 102using the velocity (VEL) output to stabilize a position Loop 98asynchronous data transfer 90
B
bandwidth 21, 22, 47binary code, natural 8, 9, 78, 79bit, binary 9bode plot 22, 47built-in-test (BIT) 81
C
calibration error 70, 79, 85capacitor value, for tuning stator windings 58carrier signal (wave) 7, 26, 86, 88clock pulse 17, 18, 20, 28, 30, 39clock-pulse generator 28, 30, 31, 43common-mode rejection ratio (CMRR) 93
common-mode voltage (CMV) 93comparator, in error processor 28, 36components, synchro and resolverclassic combination 10control differential transmitter (CDX) 5resolver (RS) 5Scott-T transformer 6synchro control transformer (CT) 5synchro control transmitter (CX) 4torque components 6transolver (TY) 6computer, interconnections for 87, 98, 104, 110, 111control transformer, solid-state (SSCT) 19, 63, 64, 102, 104converter busy (CB) 20coordinate transformation (polar to rectangular) 97costfunction generator circuits 18, 51, 52price/parameter tradeoffs 89shaft angle transducers 2counter, up-down 20, 21, 30, 31, 35, 36, 45, 46, 63, 102crossover detector 34, 35
D
data conversion techniquesdemodulation, A/D, and µP approach 18double-RC phase-shift 17harmonic oscillator 18real-time function-generator 17single-RC phase-shift 16data conversion, synchro and resolver formats 10data throughput rate 86, 87, 88DC error (D) 20design constraints for S/D and D/S converter applications 53digital signal, "ONE" and "ZERO" states, voltage level, weight-ing 8, 9, 28, 78digital word, resolution 9digital-to-analog feedback 93digital-to-resolver (D/R) conversion 36, 40, 41, 42, 49, 50, 52,53, 54, 59, 85, 86, 87, 88, 94, 97, 103digital-to-resolver (D/R) systems, testing 59, 60, 61, 62digital-to-synchro (D/S) conversion 10, 36, 59, 60, 61, 62, 85,86, 87, 88, 106digital-to-synchro (D/S) systems, testing 59, 60, 61, 62direction (U) 20, 36, 102double RC phase shift circuitry 15, 17
E
enable (EL and EM) 21, 36, 64environmental sensitivity, transducers 3error processor 20, 27, 28, 34, 35, 45, 46, 82errors, error sources, in D/S conversionamplifier mismatch 88external 85function generator 85, 86interface 85
115
INDEX
INDEX
116
INDEX
internal 85loading 87, 88settling time and slew rate 86, 87static 88transient 86worst-case error analyses 85errors, error sources, in S/D conversionacceleration 69, 70, 71, 72, 74, 75, 80amplitude 83external 69harmonic 82interface 70internal 69jitter 81linearity 77nonmonotonic 77, 78quantization 81skew 81speed voltage 76, 77staleness 80static 79summarized 69, 70, 71tracking rate 73, 80velocity 70, 71, 72, 80worst-case error statement 70
F
feedback transformer 57, 58follow-up servo systems 10, 11, 12, 13, 15format conversion transformers 65function generatorcircuits 50, 51, 52programmed 49, 50, 51, 52ratio transformer 50, 85
G
gain error and drift 70, 79, 83glitch 86, 87
H
harmonic oscillator 16, 18, 29, 30, 31, 39, 40, 41, 42, 78hybrid servo and synchro systems 11, 12, 13hysteresis threshold and quantizing uncertainty 20, 21, 81
I
IBM PC interface 98inductosyn-to-digital converter 105inhibit (INH) 21, 64integrator 18, 20, 21, 30, 31integrity of input signals 93interconnections with computers, programs 87, 98, 99, 110,113interface circuits 89, 91, 92, 93, 94
isolation transformer 20, 28, 32, 33, 58, 63, 65, 69, 83
J
jitter 21, 22, 33, 70, 72, 81, 113
L
leakage reactance 52, 65, 67least significant bit (LSB) 9, 36, 69, 73, 74, 75, 77, 78, 81, 86,110light-emitting diode (LED), drivers, in test setups 35, 36, 78, 79"limit of error" of systems 17, 71Linear Variable Differential Transformer (LVDT) 1, 2, 3, 4, 46,47, 48linearity 21, 37, 52, 65, 70, 77, 78, 79, 85, 88loading error 70, 87, 88loading, mechanical of angle transducer 3loss of signal (LOS) 21, 81
M
major carry (MC) 20, 102mathematics, fundamental, of synchros and resolvers 4, 7, 8,9, 10, 11, 12, 13, 14, 15, 16, 17, 18"missing code," nonmonotonic 78modular design 63"Monte Carlo" technique 36monotonicity 3, 18, 69, 72, 77, 78most significant bit (MSB) 9, 48, 49, 50, 80, 109Motorola 6809 interface 110, 113multiplexer, addressing of 31multiplexing, synchro-to-digital converters 31multiplexing,synchro-to-digital conversion 32, 33multipliers, sine and cosine 19, 20, 21, 27, 28, 31, 32, 33, 34,35, 50, 97
N
noise 2, 3, 4, 9, 17, 18, 21, 27, 65, 69, 70, 72, 77, 80, 81, 85,93, 105nonmonotonicity 69, 78, 85null 3, 12, 13, 14, 17, 20, 21, 45, 47, 48, 55, 56, 57, 59, 62, 63,65, 67, 71, 94, 112, 113null, stable and unstable, in two-speed systems 13, 56
O
offset, input (voltage and current) 70, 79, 93
P
performance, of shaft angle transducer 1, 2, 3phase angle, spacial and time 7, 59phase correction 25polarity selection 49, 50position feedback servo system 1, 2, 3, 5, 6, 7, 8, 9, 10, 12, 13,
15position sensing, application 98, 110, 113power requirements, how to calculate for D/S 60, 61, 62programming device 10pulsating power supplies 53, 56, 57
Q
quadrant, of angle, selection 9, 19, 20, 26, 27, 49, 50, 86quadrature error 82quadrature errors 8, 13, 17, 18, 25, 26, 27quantization uncertainty 81quantizing uncertainty 20, 69
R
ratio error, sine/cosine 83ratio error, speed-voltage 82ratio network, resistor 51, 85, 86ratio transformer, tapped 50, 51, 67read-only memory (ROM) 10, 43, 52, 87readout, blanked by B.I.T. 81readout, shaft angle 88reference carrier, errors 17, 69, 83reference excitation of transducers 4reference generator or synthesizer 25, 26, 47, 77reference oscillators 67reference-coupling transformer 65reliability, of shaft angle transducers 1, 2, 3, 4remote sense 57, 58resolution 2, 3, 9, 11, 12, 13, 21, 29, 31, 33, 34, 36, 49, 62, 69,75, 77, 79, 95, 100, 101, 113resolution, and price 89resolver (RS) 2, 6, 7resolver format signals 7, 25, 26, 28, 29, 36, 39, 41, 42, 50, 52,63, 65, 76, 83, 105, 106rotary variable differential transformer (RVDT) 1, 2, 3, 4, 45, 46,47
S
sample-and-hold circuits and techniques 27, 28, 29, 30, 31, 32,33, 35, 40, 43, 79, 81, 83sampling error 70scale factor 41, 42, 43, 52, 60, 97scanning, random and sequential 32, 33Scott-T transformer 6, 25, 28, 50, 52, 61, 63, 65, 67, 83, 106Scott-T, solid-state 6, 19, 106self-test 102servo, two-speed 11, 12servo, types I and II 20, 22, 35, 46, 71, 72, 80servomechanism, electromechanical and hybrid 10, 11, 20, 71settling time 21, 22, 33, 70, 72, 74, 75, 76, 86, 103shaft angle measurement, uses of 1, 8, 11, 18, 20, 30, 31, 32,39, 41, 49, 104, 105, 113shielded 65, 93, 94signal conditioning 3, 4
signal, digital 8, 11, 17, 69, 78single-RC phase-shift circuitry 16, 17"skew" and "skew" error 32, 70, 81slew rate 72, 86, 87, 88, 100small signal settling 22solid-state control transformer (SSCT) 27, 28, 63, 64, 102, 104speed ratio 11, 13, 34, 109speed voltage 8, 25, 69, 76, 77, 82SSCT 27, 28, 104staleness error 17, 18, 29, 32, 40, 43, 70, 79, 80static error 31, 35, 79, 85, 88stick-off voltage 13, 14stored-table-look-up 52, 78subtractor, operational 20successive approximation sampling 28, 29, 78, 80successive-approximation sampling 27Switch Resolution On The Fly – Implementation 100synchro format signal 4, 5, 6, 7, 8, 52, 63, 65synchro zeroing 79, 94synchro, "coarse" and "fine" 11, 12, 13, 14, 15, 17, 26, 34, 35,109, 110synchro/resolver systemsarchitecture 10, 11, 12, 13hybrid 6, 10, 11multi-, single-, and two-speed 10, 11, 12, 13, 33, 34, 35, 109two-speed, electrical 13synchro/resolver-to-digital conversioncircuit approaches 15, 16, 17, 18demodulation 16, 18double-RC phase-shift 16, 17dynamic testing 36, 37dynamics 21, 22, 36, 38function generator, real time 17, 18harmonic oscillator 18, 29, 30, 31multiplexing 29, 31, 32, 33, 70, 79, 81, 83, 90relationship of bandwidth, tracking rate and settling time 72sampling 18, 26, 27, 28, 29, 30, 31sequential-on-successive peak 32simultaneous sample-and-hold 32single-RC phase-shift 16successive approximation 27techniques of data conversion 15, 16, 17, 18theory of operation 19-38tracking 19, 20, 21, 22, 23, 24synchronization of converters and systems 89synchronizing shafts 104synchro-to-DC conversionsynchro- or resolver-to-linear DC 39synchro/resolver-to-nonvariant DC 40, 42theory of operation 39, 40, 41, 42
T
testingdigital-to-synchro converters 59-60, 85dynamic testing of S/Ds 36synchro-to-digital converters 35
117
INDEX
118
INDEX
thermal considerations 53, 54, 57time constant, integrator 18, 29, 30, 31, 39, 40, 71time phase error and shift 8, 13, 15, 16, 17, 18, 25, 26, 27, 33,69, 82time phase synchronization 7torque load management 53torque receiver (TR) 55, 56, 57, 59, 60, 61, 62tracking converter 19, 20, 21, 22, 26, 34, 35tracking rate, maximum in RDC-19220 74tracking rate, measurement 72, 73, 74, 75, 76, 80transducers, shaft anglebrush encoders 1cost 2environmental sensitivity of 3loading of, dynamic and static 3optical encoder 1performance of 2-3potentiometers 1reference excitation 3reliability and stability of 1resolvers 1signal conditioning of 3-4transfer function (D/S) 76transfer function (RDC-19220) 72transfer function (S/D) 22, 72, 76, 78, 83transformers (see also components)format conversion 40isolation 58power output 58translation 1transmitter, electronic control differential (ECDX) (see alsocomponents) 11trimming, of synchro/resolver systems 94tuning of synchro stator windings 58, 59tuning the load 58turn-on power surge 53typical accuarcy and performance 71typical accuracy and performance 71
V
VA (volt-amperes) 60velocity (VEL) 20, 21, 29, 32, 35, 36, 37, 38, 47, 98, 100, 101,110, 112, 113velocity error 21, 29, 35, 70, 71, 72, 80velocity range 21voltage ramp, for S/DC converter 39voltage-controlled oscillator (VCO) 20, 21, 45, 46, 73, 80
W
worst-case error analysis, D/S converters 85worst-case error analysis, S/D converters 69, 70, 78, 79
Z
zero offset 37, 70, 79, 85