Martin Elhøj Giuseppe Desoli Arnaud Grasset Miguel Miranda Fabrizio Ferrandi Francesc Moll Andre Reis Nigel Woolaway

SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures and design platforms

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Duration: 36 monthsStart date: Nov. 2nd, 2009

Funding scheme: STREPTheme: ICT-2009.3.2 - Design of semiconductor components and electronic based miniaturised systems

Project coordinator: Mr. Martin Elhøj, Nangate (me@nangate.com)

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ability to exploit step and repeat approaches employing complex logic cells and complex logic building blocks realised by regular layout patterns

Motivations

GoalsThe Synaptic project targets the optimisation of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels. We focus the research e orts on exploring and developing innovative design techniques and methodologies, along with associated CAD tools and logic cell libraries, which extract and preserve regularity, and automate the creation of regular compound cells which implement the functionality of the extracted templates.

reduces sensitivity to process variations, improving predictability of design performance and enabling tighter design marginscomprehensive early architecture exploration

usage of regular architecturesautomatically choosing a target architecture from a high level architectural libraryidenti cation of a small set of repeated functions and creation of a target fabric that is able to implement them

de nition of logic cell libraries targeted to design requirementsidenti cation of complex cellstransistor-aware mapping to produce optimized Boolean expressions

resynthesis of the design on the new library cells of complex cellsimprove performance and its predictabilitypreserve and improve design regularity

extend a cell library generator producing all standard library views (Liberty, LEF, GDS, etc) to support

the possibility to start from a Boolean description or from a transistor network described in SPICE formatthe comparison of cells at di erent degrees of regularity

conventional standard-cellsregular (Restricted Design Rule - RDR) standard cellsregular fabrics

maximise predictability, manufacturability and reduce systematic variations though layout regularity

Physical limitations of current industrial lithography techniquesComplex patterned logic cells followed by advanced mask processing steps are still the dominant approachNecessity to counter the negative e ects of signi cant regularity restrictions on logic density for advanced process nodes (32nm and below)

MetricsLithography analysis to verify the e ects on conventional and RDR standard cells, as well as regular fabrics

Study of the e ects of RDR's on SRAM in terms of performance and manufacturabilityestablish the trade-o between area and yield

de nition of set of RDR's, which allow manufacturability optimisation while remaining compatible with SRAM design rules

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SYNAPTICCELLS REPOSITORY

W: 4 cols (960nm) H: 12 tracks (2280nm)Area: 2.1888 um2

W: 4 cols (760nm) H: 10 tracks (1400nm)Area: 1.064 um2

W: 4 cols (920nm) H: 9 tracks (1260nm)Area: 1.1592 um2

W: 4 cols (920nm) H: 10 tracks (1600nm)Area: 1.472 um2