System Design & Modeling with MATlab / Simulinkread.pudn.com/downloads152/doc/comm/662135/system design and... · System Design & Modeling with MATlab / Simulink ... Real-time analysis

1

System Design & Modeling System Design & Modeling with with MATlabMATlab / / SimulinkSimulink

Project Results and Solutions within Project Results and Solutions within Research and EducationResearch and Education

- A VLSI- System - Prototyping Test-bed -Real-time Analysis & Visualization

Dr. Alfred BlaicknerEmail: [email protected]

6/8/2002Dr.A.Blaickner, email: [email protected] 2

Overview

System Design Cycle & DSP/FPGA-test-bedProject & Research Activities Communication SystemsSignal Processing Systems & EducationMATlab SolutionsVLSI - Emulation / Prototyping-test-bedConclusion

2


Motivation

System - DesignNecessary due to non-linear behavior of many subsystems and reduced word-length effectsSystem design - important step prior to VHDL -coding, synthesis and VLSI - implementation

System - Design with MATlabFloating point models - most efficient & fastest solution for early analysis & performance resultsBit-true and cycle accurate modeling techniques have been developed for the presented projects


Define concept, a mathematical model, get suitable numeric algorithms

Design of a floating point model at system levelMATlab, System-C, Co-Centric, Cossap, SPW

Map floating point model to a constrained equivalent bit-true and cycleaccurate version - minimize data path processing / shared-architecture

Verify and optimize until functionality full-filled

Map the design manually to a hardware descriptionlanguage VHDL / HDL (today) ...System-C (future ?)

Synthesize, place and route - HW / SW- Co-design cyclesget test-vectors, back-annotate, optimize and verify

System Design Cycle - Overview

3


System Design Cycle - OverviewSystem - Design – Level (ML, SysC)

Idea and conceptMathematical modelNumerical algorithmNumerical simulation model;Bit-true & cycle accurate modelMapping to architecture - manually

Behavioral- / RTL- Level (HDL, SysC)Behavioral – architecture descriptionRTL – architecture descriptionE.g: Data bus, MUX, ADD, MUL, REG -pipeline;

Implementation (Route & Place)ASIC, FPGA, DSP, Embedded - Systems

System – Simulation (ML, Msim, SysC)Simulation and back annotation to prev.

DS

R

DSPASIC


System Design Cycle - OverviewMATlab based modeling and VHDL-generationLibraries and toolbox for VHDL/HDL generation

Easy usage for automatic generation of various VHDL/HDL designs of filters & arithmetic functions (MUL, CORDIC, .. ;) E.g. half-band filters, arbitrary filter chains

Bit-true and bus accuratemodeling techniques

Most important prior to architecture mappingGet first accurate hardware results

Bit - TrueRemove zero Values

Matlab FilterDesign Tool

Coefficint Array

ReadCoeffRam.m

RunHalfBandDez.m

MakePackage.m

HB_Filter_Pkg.vhd

- Create Input data vector- Write test patter in data file- Filter data- Write result file

4


System Design Cycle - OverviewHardware / Software - Co-designDevice under Test is directly embedded in design- & test- environmentShortened design cycles and rapid prototyping

DSP-PC_boardALTERA-FPGA1.5 mil. gates)

I/O Interfaces

Testvectors


System Design Cycle - OverviewSystem Architecture Integration & Synthesis

Architectural mapping and synthesis� VHDL / C++ / System-C; Cooperation with CAE-Vendors

System Implementation� Target is currently a modular DSP/FPGA VLSI-emulator - RT-test-bed

HW/SW-co-design and co-verification� Real-time analysis and control with MATlab / MEXfile- Interface plus

pattern generator / high-speed-digital-IO� In future with both SystemC and MATlab

Embedded Parallel Processing – DSP/FPGAScaleable multi-processing architecture

� Modular DSP(Sharc)- and FPGA(Apex)-based systemC++ based system control

� Real-time test vector and verification environment� Seamless integration to industry standard compact PCI-bus system

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WidebandRF frontend

WidebandRF frontend

DisplayCTRL

CCD-Interface

SYSTEM CONTROL

cPCI-BusCLK-RefJTAG-BusPPORT

Prog./Analyze

BITSI

LVDS

LVDS

ParPort

ParPort

SerPort

SerPort

SerPort

SerPort

ParPort

ParPort

ParPort

ParPort

ParPort

ParPort

BITSI

BITSI

BITSI

DSP-array / QUADsharc 21160FloatPnt-processing / Baseband processing / Adaptive filtering / Source- / Channel coding / Signal processing

FPGA-arrayInteger- / Channel processing / FilteringSignal processing / VLSI emulation

A/D - modulesAnalog to digitalconversion

Frontend / BackendUp-/down-conversionSpecific analogelectronics

NT-Workstation-BSystem - DesignVHDL - SynthesisHW/SW-Co-design

NT-Workstation-ASystem - ControlRealtime - TestVisualization

Vector-GenFast-IO

MV-IF (Prog.)MV-Analyzer

JTAG-IF (ICE)

QuadSHARC 21160Fast-ADC (2 Chan)

Fast-DAC (2 Chan)PCI-BUS-Bridge (NI)

PCI-Bus PCI-Bus

PASS Programable Array System Simulator, design by Dr. A. Blaickner

FPGAmoduleAPEX

400/600/1000FPGAmodule

APEX400/600/1000FPGAmodule

APEX400/600/1000FPGAmodule

APEX400/600/1000

DSPSHARC21160

DSPSHARC21160

DSPSHARC21160

DSPSHARC21160

ADC

ADC

DAC

DAC

Author: Dr. A. Blaickner

DSP/FPGA-based - VLSI-emulatorFPGAs

2 x 1.5mil. GatesSystem-Clk: 50-100 Msps

DSPs4x21161 ADI-Sharc~1.2 Mflops

IO-Bandwidth~320 Mbyte/s


Project & Research ActivitiesCommunications & Signal Processing

� Software Definable Radio Transceiver Design (GSM / UMTS)� System Level Design – MATlab & System-C� System Architecture Integration and Synthesis� Embedded Parallel Processing Systems – DSP/FPGA based

Projects done with MATlab / COSSAP (1991-1999)� FFTs, CORDICs, f-Synth., f/t/p-Synchronizers, TDMA burst modem � Trained / blind equalization subsystem for broadband channels � FSK/M-QAM-modems, Wireless networking / MC - modem (OFDM) � Viterbi codec (radix - 4(2) ) // RS-codes, GF-arithmetic� DVB- Receiver and FFT/IFFT - modeling, optimization, implement.� Pipe-lined- FFT, multi-rate filters, half-band- / Avg.- / CIC-filters � Bit-true modeling and DSP/FPGA- implementation, VLSI-emulation

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Project & Research ActivitiesRecent Projects on Software Definable Transceivers

Digital Channel Processing� Programmable pulse-shaping and multi-rate filters � Polynomial based re-sampling interpolation filters (Farrow / Poly-phase)� Digital frequency synthesis, frequency translation, pipelined- CORDICs

Digital Baseband Processing� Pulse-shaping, equalization, correlation, FFT-processing, modulation –

detection, synchronization, phase looked & control loops, system ctrl;

System Level Design with SystemC & MATlabFloating point system model

� System simulation and verification – Matlab / System-CBit-true system model – architectural mapping

� Bit-true simulation and co-verification – CoCentric / SystemC / MatlabBehavioral- / RTL- HW-description and synthesis

� Mapping to a real-time DSP/FPGA - VLSI emulator (test-bed)


Communication Systems - Status

Telecommunication systems - a current statusMultiple standards - fixed system solutionsVarious dedicated VLSI - implementations

Next generation system architectures - 3G/4GUMTS / HIPERLAN

� Air-interface: WCDMA / TD-CDMA, 384 Kbit/s ... 2 Mbit/s, (QPSK,FDD,TDD)� 54Mbit: OFDM, QAM

WLAN - IEEE802.11a/b, HIPERLAN, Home-RF� 2Mbit: DSSS, FHSS� 11Mbit: DSSS (CCK), OFDM, QAM

Digital Broadcasting - DVB, MMDS� Air-interface: OFDM, QAM

Coding: Viterbi, Trellis, Turbo, Reed-Solomon or concatenated

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Software Radio - Motivation

Software radio and base-station conceptsIdeal digital software radio receiverRealistic software receiver architectureSingle system provides various air-interfaces - modulation / codingSuitable technology: FPGAs, 2 mil. logic gates - e.g. Apex, Virtex

� Sufficient system performance and logic capacity for channel processing � Re-configurable and scaleable over LVDS, Remote re-programming service� In contrast to DSP-solutions no limits for parallel structures (e.g decoding)� A system per chip solutions, designed to exact requirements, no overhead� Cost is comparable to dedicated VLSI-products e.g. band-pass processing � Limitations: power budget - small terminals, but combine VLSI & FPGA area

Library of scaleable communication sub-modules� Modulator units, channel-processing, frequency-synthesis, mixer, NCO, data-filter,

interpolator, equalizer, FEC, FFT, adaptive filter, CORDICs, parallel- / bit-serial versions;


Software Radio - MotivationConventional coherent digital receiver architecture

Generic software radio receiver architectures

WidebandRF frontend

Digital IFchannelselection

Digital IFchannelselection

Basebandprocessing

Basebandprocessing

System control unit

ADC

Datastream 1

Datastream 2..stream M

I/Q

I/Q

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Software Radio - ArchitectureA more detailed software radio architecture

Source Coding / Channel Coding / MultiplexerInner TransceiverChannel ProcessingAnalog – Backend / Frontend

DataInp

DataOut

Generic Digital Re-configurable Software Radio Transceiver

Coding/Decoding

System Control Unit

Symbol/Frame Processing Inner Transceiver Channel Processing

ScramblerFEC (VIT,RS)Puncturing

Host-Processor / Test-Interface System Control Interface

DescramblerFEC(VIT,RS)

Depuncturing

Symbol-mappingDifCod

Symbol-demappingDifDecod

Multiplexing, R

ate-conversion

Multiplexing, R

ate-conversion

DataInter-

leaving

DataDeinter-leaving

Pilot-Frame-

assembly

Channel-equalizat.Synchron.

Mux/Demux

Cyclic-Extension

Guard-interval-removal

FFT-/IFFT-processing

Puls-shaping

Symbol-/Freq-/Phase-

Synchronization

Channel-Equalization

Timing-/

Author: Dr. A. Blaickner, J2000

Configur-able

Digitalto

AnalogProcessing

Complex-Mixer

Frequency-synthesis

(DDS, NCO)

DigitalAGC

Channel-filtering

Resampling

AnalogUp-/Down-Conversion

ISM-band-RF-TX/RX

AntennaProcessing

Signal-detection

Analog RF - Processing

Analog G

ain Control - A

GC

Clock-Control / State-MachineData-/Ctrl-BUS


Complex Pipeline Radix- 4 FFT- / IFFT- Processor

Delay(12)

Delay(8)

Delay(4)

CO

MM

UTA

TOR

Delay(12)

Delay(8)

Delay(4)

BU

TTERFLY

Radix - 4

Delay(3)

Delay(2)

Delay(1)

CO

MM

UTA

TOR

Delay(3)

Delay(2)

Delay(1)

BU

TTERFLY

Radix - 4

OutA

OutB

OutC

OutD

DA

TA PA

THM

ULTIPLEXER

TXout

RXout

RXclk

TXclk

DAclk

BU

TTERFLY

Radix - 4

TX-Din

Data Scheduer

System C

ontrol

InA

InB

InC

InD

RX-Din

DAclk

RXclk

TXclk

Init

CTRLbus CTRLbus

A. Blaickner

WidebandRF frontend

Digital IFchannel

selection

Digital IFchannel

selection

Basebandprocessing

Basebandprocessing

System control unit

ADCtunable

Datastream 1

Datastream 2..stream M

I/Q

I/Q

Subsystems - OverviewSOFTWARE - Radio

OFDM

CORDICsFILTERsFFT/IFFT CICx - Interpolation Filter Architecture (CIC-4)

DATAin

A. Blaickner

REG REG REG

REG

REGREG

Delay z-n

REG REG

Delay z-n

REG REG

Delay z-n

REG REG

Delay z-n

REG REG

REGDATAout

CLKo

Int

INT INT INT

CMBCMBCMBCMB

DEC

CLKi

Switch - Matrix A. Blaickner

Prog-FIRDecimate,

interpolate,resample

Base-band-PORT

IO,Buffers

Ctrl,Mod.

System - control - interfaceUnit ctrl, mode-ctrl, sync, clk-gen, sytem-test

CTRL-Data

CIC/FIRDecimate,

interpolate,resample

Data IO-Par

IO-Ser

CTRL-Data

Mux/Switch Mux/SwitchMux/Switch

BinaryData-

Source

FrequencySynthesis

(DDS)

Digital OFDM - Transceiver

FECCoding

(1/2, 3/4, 9/16)

Scrambler

Interleaver

QAM-Mapping

FRAME-AssemblyPilot-Ins.

BinaryData-Sink

FECDecoding(1/2, 3/4, 9/16)

De-scrambler

De-Interleaver

QAM-Decisions

ChannelEqualization

Post-AFC

IFFT-TX64-pointsRadix-(2)(4)

AddCyclic

Extension

FFT- RX64-pointsRadix-(2)(4)

RemoveCyclic

ExtensionTiming-

Frequency-Correction

Windowing

RX-Data

TX-Data

A. Blaickner

ADCRF-TX

Up-converter

DACRF-TX

Up-converter

CORDIC - Unit (Rotation-mode - Mixer, vector-mode - Sin/Cos-Gen)

Xin

A. Blaickner

Xout

CLK

ADDSUBREGDly z-i

REG REG

ADDSUBREG

Dly z-i

REG REG

ANGLE-Rotation

Stage - i

SGN

ADDSUBREGatan(2-i)

z-Path

ADDSUBREGDly z-i

REG REG

ADDSUBREG

Dly z-i

REG REG

ANGLE-Rotation

Stage - i

SGN

ADDSUBREGatan(2-i)

z-Path

ADDSUBREGDly z-i

REG REG

ADDSUBREG

Dly z-i

REG REG

ANGLE-Rotation

Stage - i

SGN

ADDSUBREGatan(2-i)

z-Path

Zout

Yin

Zin

Yout

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Downconverter / Decimation FIR - Filter A. Blaickne r '2 000

8 - Tap FIR (c00,c08, ... ,cN-7)

8 - Tap FIR (c07,c15, ... ,cN-0)

8 - Tap FIR (c02,c10, ... ,cN-5)

8 - Tap FIR (c03,c11, ... ,cN-4)

8 - Tap FIR (c04,c12, ... ,cN-3)

8 - Tap FIR (c05,c13, ... ,cN-2)

8 - Tap FIR (c06,c14, ... ,cN-1)

8 - Tap FIR (c01,c08, ... ,cN-6)

Xin - 80MHz

Clk - 80MHz

Clk-Ctrl

Real (I)

Imag (Q)

Data-Filter

RRCF / GAFMatched Filter64-Taps, I-Path

Delay z-n(.)*

Rx-Data

Cplx - MULTData-FilterRRCF / GAF

Matched Filter64-Taps, Q-Path

Carrier-FrequencyDirect Digital

Synthesis(DDS)

DecisionDevice(Slicer)

Data

Symbold TimingEstimator

Digital DMPSK - DemodulatorA. Blaickner '2000

I

Q

Abs(.)

-2 0 2-2-1012

Real

Imag

4

Z-plane

0 1 2 3 4 5 6 7-4-2024

Frequency

Mag

nitu

de

I Q Mag

-2 0 2-2-1012

Real

Imag

15

Z-plane

0 1 2 3 4 5 6 7-2-1012

Frequency

Mag

nitu

de

I Q Mag

-2 0 2-2-1012

Real

Imag

9

Z-plane

0 1 2 3 4 5 6 7-1-0.5

00.51

Frequency

Mag

nitu

de

I Q Mag

I

Q

I

-50 -40 -30 -20 -10 0 10 20 30 40 50-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

f

Results of Systems - Overview

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

MU

X 4:

1M

UX

4:1

S00

S04

p00

p01

p02

p03

S08

S12

S01

S05

S09

S13

S02

S06

S10

S14

S03

S07

S11

S15

d00

d01

d02

d03

0 2 4 6 8 10 1 210 -7

10 -6

10 -5

10 -4

10 -3

10 -2

10 -1

10 0

r(n)

y(n)

e(n)

a

0 500 1000 1500 2000 250010-5

10-4

10-3

10-2

10-1

100

Residuum

0 0.02 0.04 0.060

0.02

0.04

0.06

I

Q

Coefficients - e(n)

e(n),e(n+1)

0 0.01 0.02 0.03 0.040

0.01

0.02

0.03

I

Q

Coefficients - e(n)

e(n),e(n+1)

0 0.05 0.10

0.02

0.04

0.06

0.08

I

Q

Coefficients - e(n)

e(n),e(n+1)

0 0.1 0.2 0.3 0.40.7

0.8

0.9

1

1.1

I

Q

Coefficients - e(n)

e(n),e(n+1)

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5Qam-sym

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

IFFT Tx

RxFFT

MapPrc

Data

Sync

Sync

Par/Ser

Ser/Par

RAM-1 RAM-2

IOa IOb

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 110

-4

10-3

10-2

10-1

100

Normalized frequency

Rel

ative

pow

er d

ensi

ty [d

B]

EqualizerFFT/IFFTPOLY-PHASE-FILTEROFDM-Tx/RxDigital-Rx


Communication SystemsRadix-2/4 Viterbi Codec

BMU

ModulationSymbols

DecodedSignal

BranchSelector

Best StateSelector

Soft-Decisions ACSU

OPSU

BSSU

RXCH

0 2 4 6 8 10 1210

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

BMU2

BMU2Metricnx5bitBMU4

Soft-Decisions

Soft-Decisions

l 0000

l 0100

l 1000

l 1100

l 0001

l 0101

l 1001

l 1101

l 0010

l 0110

l 1010

l 1110

l 0011

l 0111

l 1011

l 1111

l m00 l m01 l m10 l m11

l n00

l n01

l n10

l n11

00

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

00

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

n n+1 n+200

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

00

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

n n+2

MUX

4:1

MU

X 4:

1M

UX

4:1

MUX

4:1

MUX

4:1

MU

X 4:

1M

UX

4:1

MUX

4:1

MUX

4:1

MU

X 4:

1M

UX

4:1

MUX

4:1

MUX

4:1

MU

X 4 :

1M

UX

4 :1

MUX

4:1

S00

S04

p00

p01

p02

p03

S08

S12

S01

S05

S09

S13

S02

S06

S10

S14

S03

S07

S11

S15

d00

d01

d02

d03

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Communication SystemsRadix-2/4 Viterbi Codec

Branch and path metric calculationArbitrary coding schemes


Communication SystemsElectromagnetic FieldVisualization

-10 -5 0 5 10

-10

-5

0

5

10

X-axis

-10 -5 0 5 10

-10

-5

0

5

10

X-axis

Y-axis

-10 -5 0 5 10

-10

-5

0

5

10

X-axis

Y-axis

Iso-Surface / Intensity - f(x,y)

11


Digital Signal ProcessingZ-domain - IIR-band-pass filter

Impulse responseMagnitude spectraz-plane

-4 -2 0 2 4-4

-3

-2

-1

0

1

2

3

4

Real Part

Imag

inar

y P

art

-4 -2 0 2 4-4

-3

-2

-1

0

1

2

3

4

Real Part

Imag

inar

y P

art

-150 -100 -50 0 50 100 150-0.5

0

0.5

1

-150 -100 -50 0 50 100 150-4

-2

0

2

4

-150 -100 -50 0 50 100 150-4

-2

0

2

4

0 50 100 150 200 250 3000

0.5

1Tsig

Gai

n

Time

0 50 100 150 200 250 300-0.5

0

0.5

1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3-0.5

0

0.5

1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3-2

-1

0

1


Digital Signal ProcessingZ-domain

IIR-band-pass3-dim plot

12


0 50 100 150 200 250 3000

0.5

1Tsig

Gai

n

Time

0 50 100 150 200 250 300-0.5

0

0.5

1

1 2 3 4 5 6 7 8 9-2

-1

0

1

1 2 3 4 5 6 7 8 9-1

0

1

Digital Signal ProcessingZ-domain - FIR- Averaging Filter

Impulse responseMagnitude spectraz-plane

-150 -100 -50 0 50 100 150-10

0

10

-150 -100 -50 0 50 100 150-5

0

5

-150 -100 -50 0 50 100 150-10

0

10

-4 -2 0 2 4-4

-2

0

2

4

Real P art

Imag

inar

y P

art

7

-4 -2 0 2 4-4

-2

0

2

4

Real Part

Imag

inar

y P

art

7


Digital Signal ProcessingZ-domain

3-dim plot

13


Digital Signal ProcessingBase-band QAM-Modulator

4..256 – QAMEye- / Scatter-PlotQAM-Phasor - Plot


Some MATlab SolutionsMatLab Script Programming

Vector- / Matrix - multiplexer function (switch)• RESULTab=[((SELseq==0).*DATAa + (SELseq>0).*DATAb);

Vector- / Matrix - comparator function� re=(mod(hi,128)-128*(hi>127)); im=(mod(lo,128)-128*(lo>127));

Compact FSK-modulator & up-converter function� Fnyq=0.5/Ssym;Wcar=Eta*(2*pi*Fnyq);Nco=cumsum(real(DatFil)); DatMod=exp(j*Wcar*Nco);

Structure based parameter lists - e.g. complex plot function� TX.For=struct('Typ',{'Time'},'Sty',{'Stem','ReIm','ReIm','Cplx'});

TX.Dat=struct('Dat',{BinSrc,DatMap,DatFil},'Lab',{'Bsrc','Dmap’,'Dfil'}); CplxPlot(TX);

Decimation Filter Core� CoefRAM_ptr=COFidx+[1:1:COlen]; %Calc final index pointer vector Cram

PRODvec=DataDLYLIN.*CoefRAM(CoefRAM_ptr);%Multiply DlyLine Cvec, do for p0..pnSUMpart=sum(PRODvec,2); SUMsca=SUMpart; %Accumulate all partial products p0..pnDatInt(Ridx)=SUMsca; Ridx=Ridx+1; %Copy to filter result vector

Adaptive Filter Core� for k=1:LOPlen; FilRes(k)=PolyIntp(DatInp(k:k+15).',

LPcof(PPcof(1+NCOmu(k),:))); end;

14


Some MATlab SolutionsReal-time Hardware Interface

MEX - file programming// ------- MEX gateway function ------------------------------------------------------void mexFunction( int nlhs, mxArray *plhs[], int nrhs, const mxArray *prhs[]){

double Sps; //Samples per second from Patgendouble SplsRd; //Samples to read ...if(nrhs!=3) mexErrMsgTxt("usage: DataOut=PATio.... ");if(!mxIsNumeric(prhs[0])||!mxIsDouble(prhs[0])||... !=1) {mexErrMsgTxt("Input..");}Sps = mxGetScalar(prhs[0]); /* get the scalar input x */SplsRd = mxGetScalar(prhs[1]); /* get the scalar input x */DataInp = mxGetPr(prhs[2]); /* create a pointer to the input matrix y */NoCol = mxGetN(prhs[2]); /* get the dimensions of the matrix input y */plhs[0] = mxCreateDoubleMatrix(1, (int)SplsRd, mxREAL); /* set the output pointer */DataOut = mxGetPr(plhs[0]); /* create a C pointer to copy of output matrix */PATio...(Sps,SplsRd,DataInp,NoCol,DataOut); /* call the C subroutine */mxSetPr(plhs[0], DataOut); /* Load the new matrix data into plhs[0]. */

}


Conclusion

MATlab based Design of Digital Systems for Applications in the Communications and Signal Processing Area

E.g. Channel coding, Synchronization units, Equalization� High speed data transmission, typical system rate 50 ..100 Msps� M-QAM, OFDM, FHSS, DSSS, … ;

Typical application in 3G/4G Systems� WLAN, UMTS, HIPERLAN, SET-TOP-BOX, xDSL, HFC, HOME-NETworks

HW/SW- co-design and prototyping of complex data path arithmeticRe-programmability and re-use of standardized hardware proofed

Programmable array system simulator - P.A.S.S.Digital modem / frequency synthesis / signal processing in general

Questions ???

Documents

System Design & Modeling with MATlab / Simulinkread.pudn.com/downloads152/doc/comm/662135/system design and... · System Design & Modeling with MATlab / Simulink ... Real-time analysis