System-On-a-Chip: A case study based on the ELIET Chip

Infineon Technologies, Sophia-Antipolis, FRANCE [email protected] 1

System-On-a-Chip: A case study based on the ELIET ChipSystem-On-a-Chip: A case study based on the ELIET Chip


ContentsContents

ELIET Architecture SoC trade-offs Design methodology Specification Problem General information about ELIET Designed to last System Integration Verification Conclusion References


ELIET ArchitectureELIET Architecture

ELIET stands for Electronic ISDN Echo Canceller Transceiver Mixed analog/digital chip integrating all the functions required to

implement an LT (line termination) system ELIET building blocks are:

- custom DSP- 8 bit harvard micro-controller - embedded memories (ROMs and SRAMs)- different internal and external bus protocols-A/D and D/A converters-PLL- ...


ELIET ArchitectureELIET Architecture

echocance lle r

D S P

IS D Nprotoco l

contro lle r

linecontro lle r

A /D

D /A

iom

/pcm

arb

iter

un iversa l exte rna l bus in terface

filte r

fram er

defram er filte r

C oeffic ientsR AM s

m icro codeR O M s


SoC trade-offsSoC trade-offs

Cost reduction Cost reduction Shortening time to marketShortening time to market

- attack productivity bottlenecks (verification)attack productivity bottlenecks (verification)- good design methodologygood design methodology

Increase of complexityIncrease of complexity Design methodology and the right verification strategy Design methodology and the right verification strategy

become criticalbecome critical

ADVANTAGES:

DISADVANTAGES:


Design MethodologyDesign Methodology

State of the art toolsState of the art tools robust and proven design flowrobust and proven design flow rigorous project managementrigorous project management

- definition phasedefinition phase- guidelinesguidelines- checklistschecklists- design specificationdesign specification

- design phasedesign phase- VHDL coding, DFT, synthesis, floorplan, wireload model VHDL coding, DFT, synthesis, floorplan, wireload model

generation, P&Rgeneration, P&R

- verification phaseverification phase- behavioural models, RTL simulation, code coverage, behavioural models, RTL simulation, code coverage,

GL simulation, formal verification GL simulation, formal verification

- documentation phasedocumentation phase- functional doc.functional doc.- implementaion doc.implementaion doc.- verification doc. verification doc.


The Specification ProblemThe Specification Problem

specification detailed enough to allow RTL codingspecification detailed enough to allow RTL coding save time and unpleasant surprises on siliconsave time and unpleasant surprises on silicon serve as feasability studyserve as feasability study

functionality, timing, performance, interfaces, physical functionality, timing, performance, interfaces, physical issues (area, power, …)issues (area, power, …)

continuously updatedcontinuously updated

paper specificationpaper specification formal specificationformal specification executable specification (C, C++, matlab, Cossap, …)executable specification (C, C++, matlab, Cossap, …)


The Specification ProblemThe Specification Problem

- OverviewOverview- Functional requirementsFunctional requirements- Physical requirementsPhysical requirements- Verification requirementsVerification requirements- Design guidelinesDesign guidelines- Block diagramBlock diagram- InterfacesInterfaces

- signal names and meaningssignal names and meanings- transaction protocols (timing diagram)transaction protocols (timing diagram)- timing specificationstiming specifications- set-up and hold time on inputsset-up and hold time on inputs- clock to Q time for outputsclock to Q time for outputs- special signals (test, analog, …)special signals (test, analog, …)- asynchronous signalsasynchronous signals- clocks, resets, interrupts and their timingclocks, resets, interrupts and their timing- legal values for input and output dataslegal values for input and output datas

- checklists (paper, scripts, …)checklists (paper, scripts, …)


General information about ELIETGeneral information about ELIET

Block name Cell Area (mm2) Count Area (mm2) %Analog Macro 2.00 4 8.00 32.04PLLs 1.10 1 1.10 4.41Microprocessor 6.09 1 6.09 24.39DSP 3.07 1 3.07 12.29Line controller 1.60 1 1.60 6.41Interface 1.60 1 1.60 6.41Microprocessor Memories 1.76 1 1.76 7.05DSP Memories 1.75 1 1.75 7.01

Total (ELIET) 11 24.97 100


Some number about ELIETSome number about ELIET

ELIET AREA DISTRIBUTION

Microprocessor

DSP

Line controller

Interface

Microprocessor Memories

Analog Macro

PLLs


Designed to lastDesigned to last

Chip design constrained by what can be verified, rather Chip design constrained by what can be verified, rather than by the functionsthan by the functions

design style driven by verification (clock synchronous design style driven by verification (clock synchronous synthesizable RTL) synthesizable RTL)

As the complexity of the chip increases “Pray to God As the complexity of the chip increases “Pray to God approach” is not an option approach” is not an option

No magic rule to getting first-time-right siliconNo magic rule to getting first-time-right silicon maximum level of quality in each step of the development maximum level of quality in each step of the development

processprocess no separation between front end and back endno separation between front end and back end

- too many macros with the wrong aspect ratio can make the too many macros with the wrong aspect ratio can make the chip unroutable or too big or can create unacceptable chip unroutable or too big or can create unacceptable delays on critical netsdelays on critical nets

- accurate wire load models for DSMaccurate wire load models for DSM bottom up synthesis approach recommendedbottom up synthesis approach recommended


Designed to lastDesigned to last

clock distribution accurately studiedclock distribution accurately studied- balanced clock tree with low skewsbalanced clock tree with low skews

test strategy decided at an early stage of the designtest strategy decided at an early stage of the design- BIST for memoriesBIST for memories- full scan flops full scan flops - max 1000 flops per scan chainmax 1000 flops per scan chain- boundary scanboundary scan- insulation and ad hoc testing for analog macrosinsulation and ad hoc testing for analog macros

Guidelines and ChecklistsGuidelines and Checklists- RTL coding guidelinesRTL coding guidelines- coding for portability (ieee standard types, too many coding for portability (ieee standard types, too many

subtypes, …)subtypes, …)- guidelines for clock and resetguidelines for clock and reset- coding for synthesiscoding for synthesis- check code quality (profiling tools, synthesis results, ...)check code quality (profiling tools, synthesis results, ...)- no unexplained warningno unexplained warning


System IntegrationSystem Integration

Reduce the number of new gates introducedReduce the number of new gates introduced Massive reuse of existing proven designsMassive reuse of existing proven designs reused parts need to be pre-verified with high degree of reused parts need to be pre-verified with high degree of

quality to allow SOC verification to complete within a quality to allow SOC verification to complete within a reasonable time framereasonable time frame

not all core configurations have been tested togethernot all core configurations have been tested together Focus of system level simulation is on errors at macro Focus of system level simulation is on errors at macro

interconnections levelinterconnections level misunderstanding of the bus protocolsmisunderstanding of the bus protocols

- different bridges to communicate between the different different bridges to communicate between the different bussesbusses

- standardize on a single common bus architecture standardize on a single common bus architecture


VerificationVerification

Main bottleneck of the development process Main bottleneck of the development process Right verification strategy at each step of the designRight verification strategy at each step of the design It is verification that drives the selection of tools and It is verification that drives the selection of tools and

design styledesign style Define the verification plan as soon as possibleDefine the verification plan as soon as possible

- a list of all test bench componentsa list of all test bench components- a list of required verification toolsa list of required verification tools- a list of specific testsa list of specific tests- what functionality will be verifiedwhat functionality will be verified- target code coveragetarget code coverage- description of the regression test environment and description of the regression test environment and

regression proceduresregression procedures Test bench design takes more time than the circuit designTest bench design takes more time than the circuit design The entire set of test benches and test suites must be The entire set of test benches and test suites must be

reusable (different design teams) and portable (different reusable (different design teams) and portable (different simulators)simulators)



Test bench must be one of the deliverablesTest bench must be one of the deliverables Bus functional models & bus monitorsBus functional models & bus monitors single test bench command filesingle test bench command file VHDL test bench guidelinesVHDL test bench guidelines

- use a clock to synchronize stimuli generationuse a clock to synchronize stimuli generationuse built in textio packagesuse built in textio packages- partition the test bench code in synthesizable and partition the test bench code in synthesizable and

behaviouralbehavioural- do not generate data , clocks and resets from the same do not generate data , clocks and resets from the same

processprocess- common strategy for the test bench for both sub-modules common strategy for the test bench for both sub-modules

and top leveland top level- the test bench has to be self-checking (no waveform the test bench has to be self-checking (no waveform

inspection required) and issue a clear error message in inspection required) and issue a clear error message in case of failure (what occured, at what time, what was the case of failure (what occured, at what time, what was the expectation, what is the result, …)expectation, what is the result, …)



Toggle coverage greater than 98%Toggle coverage greater than 98% Timing analysisTiming analysis

- static timing analysis and formal verificationstatic timing analysis and formal verification- gate level simulation in case of asynchronous partsgate level simulation in case of asynchronous parts


ConclusionConclusion

Mixed analog/digital 4 channel ASIC for ISDNMixed analog/digital 4 channel ASIC for ISDN 0.35 0.35 m, 3.3 V technologym, 3.3 V technology 4 analog macros (about 2 mm4 analog macros (about 2 mm2 2 each)each) 2 PLLs (about 1.10 mm2 PLLs (about 1.10 mm2 2 )) microprogrammed 8 bit Harvard processor for the ISDN data microprogrammed 8 bit Harvard processor for the ISDN data

processing control (about 6.09 mmprocessing control (about 6.09 mm2 2 )) custom DSP implementing the echo cancellation algorithm custom DSP implementing the echo cancellation algorithm

(about 3.07 mm(about 3.07 mm2 2 )) line controller (about 1.60 mmline controller (about 1.60 mm2 2 )) universal external interface and iom/PCM interface universal external interface and iom/PCM interface

(about 1.60 mm(about 1.60 mm2 2 )) 6 ROMs for the microprogrammed processor 6 ROMs for the microprogrammed processor

(about 1.76 mm(about 1.76 mm2 2 )) 1 ROM and 4 SRAMs for the DSP (about 1.75 mm1 ROM and 4 SRAMs for the DSP (about 1.75 mm2 2 )) Total Area of the chip ~ 51 mmTotal Area of the chip ~ 51 mm2 2



ELIET AREA DISTRIBUTION

0.005.00

10.0015.00

20.0025.0030.0035.00

Analog

Mac

roPLL

s

Micr

opro

cess

orDSP

Line co

ntro

ller

Inte

rface

Micr

opro

cess

or Memo...




ReferencesReferences

M.Keating, P. BricaudM.Keating, P. BricaudReuse methodology manual for system-on-a-chip DesignsReuse methodology manual for system-on-a-chip DesignsKluwer Academic Publishers, 1998Kluwer Academic Publishers, 1998

A.M. Rincon, W.R. Lee, M. SlatteryA.M. Rincon, W.R. Lee, M. SlatteryThe Changing Landscape of System-on-a-Chip DesignThe Changing Landscape of System-on-a-Chip DesignCustom Integrated Circuits Conference, 1999Custom Integrated Circuits Conference, 1999

R.D. AdamsR.D. AdamsSystem on a chip TestingSystem on a chip TestingCustom Integrated Circuits Conference Educational Sessions, 1999Custom Integrated Circuits Conference Educational Sessions, 1999

D.D. WarmkeD.D. WarmkeFour white papers on VHDL designFour white papers on VHDL designIntegrated System Design, 1993Integrated System Design, 1993

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System-On-a-Chip: A case study based on the ELIET Chip