Examples of SoC and SiP

System-on-Chip

Pietro AndreaniDept. of Electrical and Information Technology

Lund University, Sweden

Overview

• Ericsson’s Bluetooth radio (2001)

• TI’s quad-band GSM (2007)

• Infineon’s quad-band GSM (2007)

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• Intel processors (2007)

Ericsson’s CMOS Bluetooth radio (2001)

Low-IF receiver

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Direct-conversion transmitter (with double-freq. LO)

Floorplan and photo

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Analog part = 4mm2

excluding pads

Issues

• Cross-coupling at 1) PCB level, 2) bond wires and package, 3) ground and supply lines, 3) silicon substrate

• The large digital cells were simulated via equivalent huge inverters. Example: the CPU (75k gates, 10MHz, 5mA from 1.5V) was emulated by an inverter with width 70,000x the minimum width

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the minimum width

• Foorplan available from start substrate RC network extracted with dedicated software, impact simulated

• A specially designed P-type trench separates analog from digital trench width = 300μm (!), area = 1.4mm2 (!!!), “which will be lowered significantly in future versions”

Issues –II

• Buried N-layer for isolating nMOS from substrate

• Trench contacted to ball grid array (BGA) through 13 bumps 25dB of improved isolation at 2.5GH (product is flip-chip mounted on a BGA, unlike the one shown here, which was bonded for testing purposes)

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• All sensitive analog circuits are differential with low common-mode to differential-mode conversion

• 5 supply domains in the digital section, plus 5 more in the analog section

• Voltage regulators for most analog blocks (LNA, VCO, etc)

TI’s single-chip quad-band GSM radio (90nm CMOS)

• The cell phone growth is fantastic– 1.2 billion phones sold in 2007– unprecedented in the history of electronics

• Mature markets are saturated– Over 100% cell phone saturation in some countries

• e.g., Finland, Taiwan, Hong Kong– US is 75%

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– US is 75%

• Continued growth from the emerging market– i.e., India and China

• Population in those countries desire cell phones but most cannot afford $100 phones– “$20 phones” will gain billions of new subscribers

This and following 6 slides courtesy of B. Staszewski, TI, Dallas

TI’s single-chip – II

• Digital baseband (DBB) and application processor need to be in the most advanced CMOS– e.g. low-voltage nanoscale digital CMOS

• True “phone-on-a-chip” has not been yet realized– 2-watt PA

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– Battery power management with 20-volt chargers– RX bandpass SAW filters

• Single-chip radio that integrates RF with digital baseband is the most cost-effective solution– Digitized RF functions can scale with Moore’s Law

Digital base-band (DBB)

• C54x DSP– Modem functions

• ARM7 MPU– Protocol layer stack– Light application

processor

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– MP3/AAC player– VGA camera I/F

• 2.5Mb SRAM– Externally extensible

• RF ADPLL can generate DBB clocks

Digital RF processor (DRP)

• Transforms RF functionality into:– All-digital PLL– All-digital polar

TX – Digitally-

intensive RX

Front-endModule

2-watt PAT/R switchRX SAW filters

eban

d Pr

oces

sor

SRA

M

DPA

Digital logic

DCO

TX

LO clock

Amplitude modulationDCXO

Xtal

TDC

FREF

DR

P Pr

oces

sor

Dither

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intensive RX• 26MHz digitally-

controlled crystal oscillator (DCXO)– FREF dither

• DBB clocks synchronous with RF clock

Discretetime

Digital logic

LNA+TA RF in

RX

A/DCurrent sampler

Dig

ital B

ase

Power Management (PM) RF Built-in Self Test (RF-BIST)

S

VBATBattery Management

Inte

rnal

D Processor clock Dividers

CH

iRF

Coexistence of RF and Digital

• Core RF circuits still experience conventional RF system issues– Device parameter spread and mismatch– Performance variability due to environmental conditions– Parasitic coupling

• On-die digital processors brings tremendous benefits

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• On-die digital processors brings tremendous benefits– Digital logic and memory are powerful yet inexpensive– Digital assistance with calibration, compensation,

predistortion , linearization, built-in self-test

• However, clocking creates noise injection issues– Millions of digital gates on the same die

Digital clock coupling to RF

• Digital clock activity is a strong aggressor• DCO LC tank is the most sensitive victim

• DBB clocks synchronous with the RF clock create

LDOIC

Package

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less injection pulling Variable caps

DCO

EM coupling

RF out

Pre PA

MUX

Clock

Chip photo

• Single-chip GSM radio• 90m digital CMOS with

no analog extensions• Package: 10x10mm2

BGA w/ 0.5mm ball pitch

• ITX: 47mA @ 1.4V

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TX

• IRX: 56mA @ 1.4V• NF = 1.9dB (!)• No TX bandpass SAW

filter• SoC: 24mm2

• DRP: 3.8mm2

• DRP consumes only 16% of SoC area

Infineon’s quad-band GSM radio SiP (130nm CMOS)

• System solution including BB+RF and power-management unit (PMU)

– reduction of PCB size– due to RF integration, only RX and TX interconnections

to SAW filters and PA are required– bill-of-material (BOM) reduction

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– bill-of-material (BOM) reduction

faster development and less effort for mobile phone manufacturers

This and following 6 slides courtesy of G. Li Puma, Infineon Technologies

System overview

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SiP details and photograph

• BB+RF SoC– 0.13μm CMOS– 6 Metal layers– MIM-capacitors– 20Ωcm substrate– bumps over active area– no deep trench

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– no deep trench– Triple well

• PMU– 0.25 μm CMOS– thick top metal layer– 5V capability

Details of RF subsystem

• RX– Quad-band zero-IF– 3rd order channel filter– 90dB DR CT-ΣΔ ADC– NF=2.4dB– AM suppression of 88dB

• TX

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• TX– linear polar modulator– closed loop power

control– +6dBm output power

• Two 26MHz output buffers

• Digital interface to BB

SiP challenges

• Crosstalk– PMU to RF coupling– BB to RF coupling

• Technology trends– # digital gates ↑

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– # digital gates ↑– Clock frequency ↑– I/O interface speed ↑

digital noise increases

• Thermal effects

Temperature distribution

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• PMU is the major contributor of heat temperature gradient

• Reduced thermal stress on RF part due to separation

Measured TX spectrum, GSM 914.8MHz

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Measured sensitivity

• Measured sensitivity with BB and PMU running

• No degradation due to integration

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to integration

• Performance comparable to stand-alone transceivers

SiP - conclusions

• SiP with integrated highly efficient power management-unit

• Fabricated in standard CMOS technologies

• RF performance is comparable to stand-alone CMOS transceivers

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• Careful floorplanning, package routing, supply and ground partitioning is mandatory

65nm CMOS 2-billion transistor quad-core Itanium

• ISSCC 2008-2009• Maiden PLL cleans ref.

clock (133MHz) jitter for core PLLs

• Dynamic clock frequency• Final max. clock = 2.0GHz

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• 21.5x32.5mm2

• 170W @ 110 oC• transistors:

• 1.42B cache• 430M core logic• 157M system interface• 39M I/O logic• 2.046B total

Penryn family – 45nm CMOS

• 410 million transistors for dual core, 820 million for quad core

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• World’s first working CPU in a 45nm CMOS process

Nehalem – 45nm CMOS

• ISSCC 2009• Successor of Penryn• 4 cores (each core with

own PLL and clock tree)

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own PLL and clock tree)• 731M transistor• Power from <10W to 130W

Xeon – 45nm CMOS

• ISSCC 2009 (no photo)• 8 Nehalem cores, 130W• 2.3B transistor• 16PLLs, 8DLLs• Same clock cleaning as

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• Same clock cleaning as Itanium

• 4 power domains: 1) cores; 2) cache; 3) I/O; 4) PLLs + thermal sensors

• Level shifter between domains