Upload
leslie-wright
View
234
Download
0
Embed Size (px)
Citation preview
8/20/2019 system verilog with oops concpets
1/18
CHIP DESIGN:
The chip design is the process of designing the
chip in efficient way;
Efficiency in the sense, the fabricated chip !st,
"Cons!e #ow power
"Cons!e #ess area
"The speed sho!#d be increased$
"The de#ay sho!#d be red!ced%!t of this, the first three are goa#s of VLSI
8/20/2019 system verilog with oops concpets
2/18
&'SI DESIGN ('%)Basic:
DESIGNENTRY
8/20/2019 system verilog with oops concpets
3/18
DIGIT*' DESIGN" Digita# design is #ogica##y cobining the
digita# coponents to perfor a f!nction indigita# syste$
" Since the digita# syste has high,
+e#iabi#ity
*cc!racy
" The digita# design is ro!gh#y diided in to -
.$ Syste design
/$ 'ogic design
-$ Circ!it design
8/20/2019 system verilog with oops concpets
4/18
Contd…
.$ Syste design:
It is the process of differentiating syste in to n!ber
of s!b0syste$
/$ 'ogic design: It is the process of interconnection
%f #ogic e#eent and gates to perfor a #ogic f!nction$
-$ Circ!it design: It is the process of connecting the each and eery
coponents in a chip to for a circ!it1IC2$
8/20/2019 system verilog with oops concpets
5/18
History %eriewDiode:
* diode is a seicond!ctor deice consist of
Positie1anode2 and Negatie1cathode2 terina#s$
It can be !sed as switch basica##y$
Terino#ogy :
(orward bias, +eerse bias, (orward o#tage,
+eerse o#tage, C!t in o#tage, (orward c!rrent,
+eerse c!rrent, 3ener o#tage1&+C2, C!rrentreg!#ator circ!it 14(ET with Gate2$
8/20/2019 system verilog with oops concpets
6/18
T+*NSIST%+:
8/20/2019 system verilog with oops concpets
7/18
INTEG+*TED CI+C5IT
" *n in Integrated Circ!it 1IC2 is cobination of
circ!it
e#eents that are interconnected to for a
#ogica# f!nction$
IC are c#assified according to their #ee# ofcop#e6ity,SSI
7SI'SI
&'SI
8/20/2019 system verilog with oops concpets
8/18
IC contd8" 9!t basica##y the IC are c#assified in to,
Digita# IC *na#og IC
+( 1or2 7i6ed Signa# IC$
(!rther it can be c#assified in to,
DIGITAL IC:
.$ (PG*
/$ Conentiona# Digita# IC
-$ 7eory IC
8/20/2019 system verilog with oops concpets
9/18
IC contd8
RF IC:
Conentiona# +( ICPS%C
ANALOG IC:
Conentiona# *na#og IC
'inear Integrated Circ!it$
8/20/2019 system verilog with oops concpets
10/18
POLAR DEVICE:
FET:
JFET:
DEMERIT: Need large area forintegration.
8/20/2019 system verilog with oops concpets
11/18
5NIP%'*+ DE&ICES:
" The we## nown e6ap#e of 5nipo#ar deice
are 7%S(ET$
" 7%S(ET stands for 7eta# %6ide
Seicond!ctor (ie#d Effect Transistor$
" It is genera##y c#assified in to two typesnae#y,
P07%S(ET 1P0 P channe#2$
N07%S(ET 1N0 N channe#2$
8/20/2019 system verilog with oops concpets
12/18
C7%S:C7%S(ET:
It stand for Cop#eentary 7eta# %6ideSeicond!ctor (ie#d Effect Transistor$
*d:.$ Static Power ero$
Dis*d: .$ 'atch !p prob#e$
/$ 'ow o!tp!t c!rrent$
8/20/2019 system verilog with oops concpets
13/18
Design Oerie!:
8/20/2019 system verilog with oops concpets
14/18
E'ECT+%NIC 9*SIC:
*NCIENT '%GIC (*7I'
8/20/2019 system verilog with oops concpets
15/18
"$OGI%
Dis#d:
&. 'ig( )o!er Dissi*ation as res+lt (eat is
*rod+ced.
8/20/2019 system verilog with oops concpets
16/18
ODE"TR#NSISTOR $OGI%
Dis#d:
&.)ro*ogation dela,.
8/20/2019 system verilog with oops concpets
17/18
"$OGI%:
Dis#d:
&. $o! n+-er of Fano+t.
/. 'ig( o+t*+t Resistance.
8/20/2019 system verilog with oops concpets
18/18
SEMI%OND1%TOR
Dis#d:
&. Sensitie to electrostatic c(arges.