Systematic Approach to GaN Power IC Reliability...Navitas Proprietary & Confidential Systematic Approach to GaN Power IC Reliability APEC 2019 PSMA Industry Session IS11: “Current

Navitas Proprietary & Confidential

Systematic Approach to GaN Power IC ReliabilityAPEC 2019 PSMA Industry Session IS11: “Current reliability and product qualification topics for SiC and GaN wide band gap devices", March 20th, 2019

Dr. Darshan Gandhi, Sr. Director Reliability [email protected]

mailto:[email protected]

Navitas Proprietary & Confidential 2

World’s First GaNFast™ Power ICs

Fastest, most efficientGaN Power FETs

>20x faster than silicon>5x faster than cascoded GaN- Proprietary design- Gate is fragile and sensitive to noise

First & Fastest IntegratedGaN Gate Drivers

World’s First

Power ICs

Up to 40MHz switching, 5x higher density & 20% lower system cost

>3x faster than any other gate driver- Proprietary design- 30+ patents granted- Fast, protected gate, no need for negative drive

- Simple, fast and reliable- Easy to use and package


Enabling Advanced Technologies

Reliability corners defined using reliability physics based lifetime models

Increasing Integration

Robust PDK = successful integration

Reliability corners


PDK Analysis

Device elementReliability model requirement

Capacitor Guaranteed by proprietary design, verified by characterization – reliability models not required

Resistor

Electro-migrationMature process and Foundry qualified

LV GaNFET

Reliability models required

HV GaNFET

HV GaNFET

LV GaNFET

Capacitors

Resistors

IntegratedCircuit

Reliability models need to replicate stresses seen in real application


Typical Application: Mobile Chargers

MacBook <100 kHz<6.5 W/in3, 92%

• ACF (ZVS) Topology• 300kHz – 1 MHz• 120 V – 240 V AC

Navitas ~300 kHzPower density = 39 W/in3

65W USB-PD

5


Application Profile for ACF Charger

Voltage

Current

Burst Mode (TDUT = 25°C)(No Load)

Voltage

Current

Voltage

Current

500 us/div5 us/div1 us/div

Light Load (TDUT = 50°C)Full Power (TDUT = 100°C)

6


Full Power Stress Breakdown

Voltage

Current

1 us/div

Full Power (TDUT = 100°C) Stress seen by HV GaNFET:• High Temperature• High Frequency• High Voltage (Switching)• High Current

Stress seen on LV GaNFET:• High Temperature• High Frequency

7


Burst Mode Stress Breakdown

Burst Mode (TDUT = 25°C )(No Load)

Voltage

Current

500 us/div

Stress seen on HV GaNFET:• Low Temperature• Low Frequency (~static)• High Voltage (Blocking)• Low/No Current

Stress seen on LV GaNFET:• Low Temperature• Low Frequency (~static)

8


Reliability Stresses to Model

Relevant stress to model Test method used to characterize

Static stress on HV GaNFET Drain High Temperature Reverse Bias

Static stress on Gate High Temperature Gate Bias

Switching stress on Gate Gate Switching Reliability

Switching stress on HV GaNFET Drain High Temperature Operating Life









1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

400 450 500 550 600 650 700 750 800

Tim

e to

Fai

lure

(h

rs)

Voltage (V)

HTRB Acceleration & Lifetime Models

𝐿𝑖𝑓𝑒𝑡𝑖𝑚𝑒 = 𝐴 × (𝑉−𝑛) × (𝑒𝐸𝐴𝑘𝑇)

Voltage/Temperature

100°C 125°C 150°C

650V ✓

700V ✓ ✓ ✓

750V ✓

𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 ∝1

(𝑉𝑜𝑙𝑡𝑎𝑔𝑒)𝒏=𝟏𝟖.𝟔

T=150 °C, Voltage Acceleration

11

Projected Application Condition Using Model

Lifetime in no load condition is >1E8 years, significant built-in margin

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

25 50 75 100 125 150 175

Tim

e t

o F

ail

ure

(h

rs)

Temp (°C)

V= 700 V, Temperature Acceleration

𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 ∝ 𝑒^((𝐸𝑎=0.91𝒆𝑽)/𝑘𝑇)









1.E-02

1.E+01

1.E+04

1.E+07

1.E+10

1.E+13

1.E+16

5 6 7 8 9 10 11

Tim

e to

fail

(hrs

)

Vg (V)

1.E-02

1.E+00

1.E+02

1.E+04

0 25 50 75 100 125 150

Tim

e to

fai

l (h

rs)

Temp (°C)

1.E-02

1.E+01

1.E+04

1.E+07

1.E+10

1.E+13

1.E+16

5 6 7 8 9 10 11

Tim

e to

fai

l (h

rs)

Vg (V)

1.E-02

1.E+00

1.E+02

1.E+04

0 25 50 75 100 125 150

Tim

e t

o f

ail (

hrs

)

Temp (°C)

13

Gate Reliability Acceleration Models

Static and switching stresses have same acceleration factors

Voltage/Temperature

25°C 50°C 75°C

9.5V ✓

10.0V ✓ ✓ ✓

10.5V ✓

𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 ℎ𝑟𝑠 ∝1

(𝑉𝑜𝑙𝑡𝑎𝑔𝑒)𝒏=𝟔𝟎.𝟓𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 ℎ𝑟𝑠 ∝

1

(𝑉𝑜𝑙𝑡𝑎𝑔𝑒)𝒏=𝟓𝟗.7

𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 (ℎ𝑟𝑠)∝ 𝑒^((𝐸𝑎=-0.63𝒆𝑽)/𝑘𝑇)


𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 (ℎ𝑟𝑠)∝ 𝑒^((𝐸𝑎=-0.65𝒆𝑽)/𝑘𝑇)

V= 10V, Temperature Acceleration V= 10V, Temperature Acceleration


100KHz, 50%

100KHz, 50%


1.E+00

1.E+01

1.E+02

1.E+03

0 25 50 75 100 125

Tim

e to

fai

l (se

c)

Duty cycle (%)

0

20

40

60

80

100

120

0 25,000 50,000 75,000 100,000 125,000 150,000

Tim

e t

o f

ail (

sec)

Frequency (Hz)

14

Frequency Acceleration

Frequency ↓ / Duty cycle ↑ / Pulse width ↑ Closer to static stress

Static reliability

Lifetime improves at higher frequencies

V=11V, T=25°C, 50% duty cycle

V=11V, T=25°C, 100KHz

Typical applications for GaN devices operate at >100KHz0

20

40

60

80

100

120

0.00E+00 5.00E-06 1.00E-05 1.50E-05 2.00E-05 2.50E-05

Tim

e t

o f

ail (

sec)

Pulse width (sec)


1.E-07

1.E-04

1.E-01

1.E+02

1.E+05

1.E+08

1.E+11

1.E+14

5 6 7 8 9 10 11

Tim

e t

o f

ail (

year

s)

Vg (V)

15

Gate Reliability Lifetime Estimation

Integrated regulator guarantees operation with 10+ years of estimate life

10years100KHz, 50%

Operating window – guaranteed by design

Wide design window with 10+ years life









Mission Profile Driven HTOL (ZVS)

Voltage

Current

1 us/div

Full Power (TDUT = 100°C)

VSW

Low side gate

iL

VCC

DZ

VDD

PWM

S

D

REG

dV/dt

500 kHz

VCC

DZ

VDD

PWM

S

D

REG

dV/dt

500 kHz

VDD

+-

ZVS test bench replicates stresses seen in ACF application


Failure Mode Matters

VCC

DZ

VDD

PWM

S

D

REG

dV/dt

500 kHz

VCC

DZ

VDD

PWM

S

D

REG

dV/dt

500 kHz

VDD

+-

0.94

0.96

0.98

1

1.02

1.04

1.06

No

rmai

zed

Po

we

r lo

ss p

er

cell

Stress Time

System degradation

Group 1: In-situ system power loss monitoring

1%

10%

100%

Par

amet

ric

failu

re p

rob

abili

ty

Stress Time

Group 2: Measure parameters at interim intervals

650V, 150°C HTOL


1%

10%

100%

Failu

re p

rob

abili

ty

Time

19

Failure Mode Matters

VCC

DZ

VDD

PWM

S

D

REG

dV/dt

500 kHz

VCC

DZ

VDD

PWM

S

D

REG

dV/dt

500 kHz

VDD

+-

Parametric failure = minor efficiency degradation

0.94

0.96

0.98

1

1.02

1.04

1.06

No

rmai

zed

Po

we

r lo

ss p

er

cell

Stress Time

System degradation

Group 1: In-situ system power loss monitoring

Lifetime estimation using parametric failure conservative approach Group 2: Measure parameters at interim intervals

650V, 150°C HTOL


HTOL-based Lifetime Model

Voltage/Temperature

100°C 125°C 150°C

550V ✓

575V ✓

600V ✓

625V ✓

650V ✓ ✓ ✓

𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 ℎ𝑟𝑠 ∝1

(𝑉𝑜𝑙𝑡𝑎𝑔𝑒)𝒏=𝟏𝟕.𝟐

𝑇𝑖𝑚𝑒 𝑡𝑜 𝐹𝑎𝑖𝑙 ℎ𝑟𝑠 ∝ 𝑒𝐸𝑎=𝟎.𝟕𝟏𝒆𝑽

𝑘𝑇


V= 650 V, Temperature Acceleration

20


Stress Profile in ACF

Voltage

Current

Burst Mode (No Load)

Voltage

Current

Voltage

Current

500 us/div5 us/div1 us/div

Light LoadFull Power

21

Mode Voltage DUT Tcase Typical time spent (1 charge/day)

Relevant reliability stress

Full Power 460V 100°C 8 hours (33%) HTOL

Light Load 460V 50°C 4 hours (17%) HTOL

No Load (burst) 340V 25°C 12 hours (50%) HTRB HTOL

Assuming worst case scenario at 240VACHTOL is more aggressive than HTRB


Lifetime Estimation Methodology

22

Mode Voltage DUT Tcase Typical time spent (1 charge/day)

Relevant reliability stress

Full Power 460V 100°C 8 hours (33%) HTOL

Light Load 460V 50°C 4 hours (17%) HTOL

No Load (burst) 340V 25°C 12 hours (50%) HTOL

Weighted average for each mode


1

10

100

1000

10000

0 2 4 6 8 10 12 14 16 18 20 22 24

Pro

du

ct li

fe (

year

s)

Full power charging time /day (hrs)

MTTF100ppm

Lifetime Estimation in Charger Application

Significant built-in reliability margin even at worst case conditions (exceeds 10+ year lifetime requirement)

23

100% full power (unrealistic)

100% No load (unrealistic)

10years

30years

230years

700years

90years

Typical operating regime


Reliability Qualification Release

Reliability models on IC building blocks

= Robust design

Mission profile driven reliability =

Protected Customer

Reference Test Conditions Duration Lots S.S.

JESD22-A113

J-STD-020

Preconditioning (MSL1):

Moisture Preconditioning + 3x reflow:

HAST, UHAST, TC & PC

N/A 3 308PASS

(0/308)

JESD22-A104Temperature Cycle:

-55°C / 150°C1,000cy 3 77

PASS

(0/231)

JESD22-A122Power Cycle:

Delta Tj = 100°C10,000cy 3 77

PASS

(0/231)

JESD22-A110Highly Accelerated Stress Test:

130°C / 85%RH / 100V VDS

96hrs 3 77PASS

(0/231)

JESD22-A108High Temperature Reverse Bias:

150°C / 520V VDS

1,000hrs 3 77PASS

(0/231)

JESD22-A108High Temperature Gate Bias:

150°C / 6V VGS

1,000hrs 3 77PASS

(0/231)

JESD22-A108 High Temperature Operating Life 1,000hrs 3 77PASS

(0/231)

JESD22-A108 Early Life Failure Rate 24 hrs 3 1,000PASS

(0/3,000)

JS-001-2014 Human Body Model ESD N/A 1 3PASS0/3

JS-002-2014 Charged Device Model ESD N/A 1 3PASS

0/3

Comprehensive reliability

monitoring

Metric Results

Equivalent device hours tested* 1.5 billion hours

FIT* 0.6

Quality

Speed

Efficiency

Now in high volume production!

POWER ICs

*Statistics calculated from HTOL tests


GaNFast Chargers now in production

27W24W 30W 45W

45W

FastUp to 3x more power

Up to 3x faster charging

MobileHalf the size & weightof traditional chargers

UniversalOne charger for ALL your devices

One and Done!!


Documents

Systematic Approach to GaN Power IC Reliability...Navitas Proprietary & Confidential Systematic Approach to GaN Power IC Reliability APEC 2019 PSMA Industry Session IS11: “Current