SystemVerilog · 2018. 11. 18. · SystemVerilog Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) Major extension of Verilog language (IEEE 1364)

SystemVerilog

● Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800)

● Major extension of Verilog language (IEEE 1364)

● Targeted primarily at the chip implementation and verification flow

● Improve productivity in the design of large gate-count, IP-based, bus-intensive chips

Sources and references

1. Accellera IEEE SystemVerilog pagehttp://www.systemverilog.com/home.html

2. “Using SystemVerilog for FPGA design. A tutorial based on a simple bus system”, Douloshttp://www.doulos.com/knowhow/sysverilog/FPGA/

3. “SystemVerilog for Design groups”, Slides from Doulos training course

4. Various tutorials on SystemVerilog on Doulos website

5. “SystemVerilog for VHDL Users”, Tom Fitzpatrick, Synopsys Principal Technical Specialist, Date04http://www.systemverilog.com/techpapers/date04_systemverilog.pdf

6. “SystemVerilog, a design and synthesis perspective”, K. Pieper, Synopsys R&D Manager, HDL Compilers

7. Wikipedia

http://www.systemverilog.com/home.htmlhttp://www.doulos.com/knowhow/sysverilog/FPGA/http://www.systemverilog.com/techpapers/date04_systemverilog.pdf

Extensions to Verilog

● Improvements for advanced design requirements– Data types– Higher abstraction (user defined types, struct, unions)– Interfaces

● Properties and assertions built in the language– Assertion Based Verification, Design for Verification

● New features for verification– Models and testbenches using object-oriented techniques (class)– Constrained random test generation– Transaction level modeling

● Direct Programming Interface with C/C++/SystemC – Link to system level simulations

Data types: logic

● Nets and Variables● Net type, Data type

● Variables● Data type

● New logic 4-state data type (synonym for reg)

● Ports can be variables● Variables can be assigned

in continuous statements

● Built-in: byte, shortint, int, longint

module counter (input logic clk, reset, enable, output logic q);

logic [7:0] count;

assign q = count[7];

always @(posedge clk or posedge reset)

begin

if (reset == 1'b1)

count

logic [3:0][7:0] qBytes [0:15][1:3];

...

Qbytes[0][1][3][7] = 1'b1;

Packed and unpacked arrays

● Multidimensional packed arrays unify and extend notion of registers and memories

packed unpacked

unpacked packed

logic [7:0] qBytes [0:15][1:3];

Array querying functions

1 23

$dimensions(qBytes)

3

$unpacked_dimensions(qBytes)

2

$left(qBytes)

0 $left(qBytes,2)

1

$right(qBytes,2)

3 $right(qBytes,3)

0 $low(qBytes,2)

1

$high(qBytes,2)

3

$size(qBytes,3)

8 $size(qBytes,2)

3

$increment(qBytes,1)

-1

$increment(qBytes,3)

1

$bits(qBytes)

512

logic [3:0][7:0] qBytes [0:15][1:3];

User defined types

● User defined types with typedef● Higher level

abstraction● Design intent

typedef logic [7:0] octet_t;

typedef octet_t [3:0] quadOctet_t;

typedef qBytes_t quadOctet_t [0:15][1:3];

qBytes_t qBytes ;

...

Qbytes[0][1] = 32'hFFFFFFF;

Qbytes[0][1][2] = 8'hAA;

Qbytes[0][2][3][7] = 1'b1;

SystemVerilog Struct

tcp_t mypkt;…mypkt.source_port = 16'hAAAA;mypkt.dest_port = 16'hBBBB;

31 063

Design hierarchy

● Creating a hierarchy in SystemVerilog is simpler (=less typing) than in Verilog

● Use variables, no need of wires

● Implicit port connections

module counter(input logic clk, reset, enable, output logic q);

// … CODE HERE!

endmodule: counter

module top(input logic clk, reset, enable, output logic RE, output logic WE, output types::addr_t addr, output types::rdata_t rdata, output types::wdata_t wdata); logic en_data_gen, en_data_gen_b, q; Counter INST_C0(.clk, .reset, .enable, .q(en_data_gen)); Counter INST_C1(.*); // NOT RECOMMENDED! endmodule: top

Packagespackage types;

typedef logic [7:0] wdata_t;

typedef struct packed { logic [3:0] data_h; logic [3:0] data_l; } wdata_struct_t;

endpackage: types

Allows sharing of:● nets, variables, types,● tasks, functions● classes, extern constraints, extern

methods● parameters, localparams, spec params● properties, sequences

● Unambiguous references to shared declarations

• Built-in functions and types included in std package

• Groups of files can be compiled separately

Enabling efficient coding: example

control INST_CTRLChannel INST_LEFT

Channel INST_RIGHT

Adding a signal can require editing through the full hierarchy

module top(input logic clk, reset);

logic [1:0] cfga, cfgb, cfgc, cfgd;

control INST_CTRL(.clk(clk), .cfga(cfga), .cfgb(cfgb),

.cfgc(cfgc), .cfgd(cfgd));

channel INST_LEFT(.clk(clk), .cfga(cfga[0]), .cfgb(cfgb[0]),

.cfgc(cfgc[0]), .cfgd(cfgd[0])); channel INST_RIGHT(.clk(clk), .cfga(cfga[1]), .cfgb(cfgb[1]),

.cfgc(cfgc[1]), .cfgd(cfgd[1]));

endmodule : top

SystemVerilog ports support struct typespackage types; typedef struct {logic cfga; logic cfgb; logic cfgc; logic cfgd; } configGroup_t;endpackage: types

module top(input logic clk); import types::*;

configGroup_t cfg [1:0];

control INST_CTRL(.clk, .cfg); channel INST_LEFT(.clk, .cfg(cfg[0])); channel INST_RIGHT(.clk, .cfg(cfg[1]));

endmodule : top

module control(input logic clk, output types::configGroup_t cfg [1:0]); // … endmodule: control

module channel(input logic clk, input types::configGroup_t cfg); // … endmodule: channel

Grouping signals and port with struc types enable avoiding editing through the full hierarchy

Catch design intent: always_{comb,latch,ff}

always_ff @(posedge clk or posedge reset)begin if (reset == 1'b1) count

Example basic design

Interfaces are much more than sets of grouped variables (signals)

● SystemVerilog interface can have ports and contain variables and processes (like a module)

● It can connect to a module port (unlike a module)

● An interface that represents all of the wires within an on-chip bus only requires a single port connection to each master and slave on the bus

● modports within the interface allow master ports and slave ports to have different characteristics

Conclusions on design extensions● SystemVerilog raises abstraction level

– Productivity improves– 3x to 5x code size reduction– Better and faster verification with synthesis

● Currently using Verilog for design? – clear advantages in updating to SystemVerilog – backwards compatible with all existing Verilog

● Currently using VHDL?– effort switching to SystemVerilog justified? If your designs

contain on-chip multiplexed busses with multiple masters and slaves, it probably is

● Just starting out?– it makes sense to choose SystemVerilog as first design

language to learn

Extensions to Verilog


● New features for verification– Models and testbenches using object-oriented techniques (class)– Transaction level modeling– Constrained random test generation

● Properties and assertions built in the language– Assertion Based Verification, Design for Verification



● Properties and assertions built in the language (SVA)– Assertion Based Verification, Design for Verification

● New features for verification– Models and testbenches using object-oriented techniques (class)– Transaction level modeling– Constrained random test generation


Assertions0 1 2 3 4 5 6

req

ack

read

write

read and write cannot be asserted simultaneously

read or write cannot be asserted when req is not asserted

ack must be active 1, 2 or 3 clock cycles after req

ack must change to active 1, 2 or 3 clock cycles after req changes to active

assert property ( @(posedge clk)

!(read && write) );

assert property ( @(posedge clk)

!((read || write) && !req) );

assert property ( @(posedge clk) req ##[1:3] ack );

assert property ( @(posedge clk) $rose(req) ##[1:3] $rose(ack));

Sequences, properties, assertions

read and write cannot be asserted simultaneously

read or write cannot be asserted when req is not asserted

ack must be active 1, 2 or 3 clock cycles after req

ack must change to active 1, 2 or 3 clock cycles after req changes to active

assert property ( !(read && write) );

assert property ( !((read || write) && !req) );

assert property ( @(posedge clk) req ##[1:3] ack );

assert property ( @(posedge clk) $rose(req) ##[1:3] $rose(ack));

property not_read_and_write; @(posedge clk) not (read && write);endproperty assert property (not_read_and_write);

sequence request req;endsequence

sequence acknowledge ##[1:3] Ack;endsequence

property handshake; @(posedge clk) request |> acknowledge; // property built from sequences andendproperty // implication operators |>, |=>

assert property (handshake); // instruct simulator to react on verification

cover property (handshake); // instruct simulator to count verification

Binding to existing modules

property not_read_and_write; not (read && write);endproperty assert property (not_read_and_write);

sequence request req;endsequence

sequence acknowledge ##[1:2] Ack;endsequence

property handshake; @(posedge clk) request |> acknowledge; // property built from sequences andEndproperty // implication operators |>, |=>

assert property (handshake); // instruct simulator to react on verification

cover property (handshake); // instruct simulator to count verification

module MyDevice (...); // The design is modelled hereendmodule

…program MyDevice_assertions(...); // sequences, properties, assertions for M go hereendprogram…

bind MyDevice MyDevice_assertions INST_MYDEVICE_ASSERTIONS (...);

module MyDevice (...); // The design is modelled here

program MyDevice_assertions(...); // sequences, properties, assertions for M go here Endprogram MyDevice_assertions INST_MYDEVICE_ASSERTIONS (...);endmodule

Equivalent to:

Classes

class CAN_Message;

rand struct packed { bit [10:0] ID; // 11bit identifier bit RTR; // reply required? bit [1:0] rsvd; // "reserved for expansion" bits bit [3:0] DLC; // 4bit Data Length Code byte data[]; // data payload bit [14:0] CRC; // 15bit checksum } message;

task set_RTR (bit new_value); // Set the RTR bit as requested message.RTR = new_value; if (message.RTR) begin // Messages with the RTR bit set should have no data. message.DLC = 0; clear_data(); // make the data list empty end

endtask

task clear_data; ... endtask

constraint c1 { message.DLC inside {[0:8]}; } constraint c2 { message.data.size() == DLC; }

endclass

● Classes are the foundation of the testbench automation language

● Classes are used to model data ● Data values can be created as part of

the constrained random methodology

● rand keyword for data members that can be randomized

● SystemVerilog has dynamic arrays

● Tasks to manipulate structured data are class members

● constraint keyword to describe properties of data fields

Testbench with classes

class CAN_Message;

rand struct packed { bit [10:0] ID; // 11bit identifier bit RTR; // reply required? bit [1:0] rsvd; // "reserved for expansion" bits bit [3:0] DLC; // 4bit Data Length Code byte data[]; // data payload bit [14:0] CRC; // 15bit checksum } message;

task set_RTR (bit new_value); // Set the RTR bit as requested message.RTR = new_value; if (message.RTR) begin // Messages with the RTR bit set should have no data. message.DLC = 0; clear_data(); // make the data list empty end

endtask

task clear_data; ... endtask

constraint c1 { message.DLC inside {[0:8]}; } constraint c2 { message.data.size() == DLC; }

endclass

module CAN_Message_tb; CAN_message test_message[10]; //unpacked array of 10 CAN_message objects

logic SerialIn; MyModule INST_DUT (.clk, .SerialIn);

…

initial

begin // initialize the 10 messages with random data: for (int i = 0; i = 0; msgCount) for (int i = test_message[0].message.size()1; i>=0; i) begin @(posedge clk) SerialIn

Functional coverage

enum {Red, Green, Blue} Colour;

logic [3:0] x, y;

covergroup cg_Colour @(posedge clock);

coverpoint Colour;

Endgroup

covergroup cg_xy @(posedge clock);

X : coverpoint x;

Y : coverpoint y;

XY : cross X, Y;

endgroup

● Instruct simulator to build histograms of values taken by variables

● Histogram pair (triples...) of values

● Control binning

● Histograms of transitions– State machines

Standard CERN PC, large screen and SLC5

● HP Compaq DC 7900 (2009 model)– Note: Only VGA video output is supported, the

DisplayPort connector is not functional on SLC5 as of March 2009 (even with DisplayPort to DVI adapter): Therefore dual-screen setups cannot be used.

– Update: As of December 2009 the DisplayPort adapter works on some configurations providing fully updated SLC 5.4 version is used.

● Bought ATI video card on CERN store– Installed proprietary driver downloaded from ATI site– Configured via command line tool– Using dual screen (24” HP CERN store + 19” EIZO)

● 24” driven by HDMI cable, 19” by DVI cable● Full native resolution, 60 Hz

Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34

Documents

SystemVerilog · 2018. 11. 18. · SystemVerilog Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) Major extension of Verilog language (IEEE 1364)