T T A S t a n d a r d - committee.tta.or.kr 정보통신단체표준(영문표준) T T A d 정보통신단체표준(영문표준) 제정일: 2017 년 12 월 xx일 TTAE.IE-802.3bp-2016

정보통신단체표준(영문표준)

T T

A S

t a n

d a

r d

정보통신단체표준(영문표준) 제정일: 2017 년 12 월 xx 일

TTAE.IE-802.3bp-2016

IEEE 이더넷 표준 개정 4 : 단일 트

위스티드 페어 카퍼 케이블 상의

1Gb / s 동작을 위한 물리 계층 규

격 및 관리 파라미터

(IEEE Std 802.3bpTM-2016)

IEEE Standard for Ethernet Amendment 4:

Physical Layer Specifications and

Management Parameters for 1 Gb/s

Operation over a Single Twisted-Pair Copper

Cable

(IEEE Std 802.3bpTM-2016)

표준초안

검토 위원회 이더넷 프로젝트그룹(PG218)

표준안

심의 위원회 통신망기술위원회(TC2)

성명 소 속 직위 위원회 및 직위 표준번호

표준(과제) 제안 김아정 세종대학교 교수

이더넷프로젝트그룹

산업융합네트워크포럼

운영위원

-

표준 초안 작성자 김아정 세종대학교 교수

이더넷프로젝트그룹

산업융합네트워크포럼

운영위원

TTAE.IE-

802.3bp

사무국 담당 김재웅 TTA 단장 -

이민아 TTA 선임 -

본 표준 발간 이전에 접수된 지식재산권 확약서 정보는 본 표준의 ‘부록(지식재산권 확약서 정보)’에 명시하고 있으며, 이후 접수

된 지식재산권 확약서는 TTA 웹사이트에서 확인할 수 있습니다.

본 표준과 관련하여 접수된 확약서 외의 지식재산권이 존재할 수 있습니다.

발행인 : 한국정보통신기술협회 회장

발행처 : 한국정보통신기술협회

13591, 경기도 성남시 분당구 분당로 47

Tel : 031-724-0114, Fax : 031-724-0109

발행일 : 2017.xx



i

서 문

1 표준의 목적

이 표준은 자동차에 응용되는 이더넷 전송 기술에 관한 것으로서, 단일 트위스티드

페어 카퍼 케이블 (twisted pair copper cable) 상의 1Gb/s 동작을 위한

1000BASE-T1 이더넷의 물리 계층(PHY) 규격과 관리 파라미터를 정의하는 것을

목적으로 한다.

2 주요 내용 요약

이 표준은 1000BASE-T1 이더넷을 위한 관리 데이터 입/출력 (MDIO) 인터페이스,

물리 부호화 부계층 (PCS), 물리 매체 접속 (PMA) 부계층 및 기저 대역 매체 유형

에 대해 정의한다. 또한 단일 디퍼런셜 페어 (differential pair) 매체에서의 자동

협상 (Auto-negotiation), 에너지 고효율 이더넷 (Energy-Efficient Ethernet. EEE)

기능 등도 정의한다.

3 인용 표준과의 비교

3.1 인용 표준과의 관련성

이 표준은 인용 표준인 IEEE Std 802.3bpTM-2016, Amendment 4: Physical Layer

Specifications and Management Parameters for 1 Gb/s Operation over a Single

Twisted-Pair Copper Cable 을 영문 그대로 완전 수용하는 표준이다.

본 TTA 표준은 IEEE와의 라이선스 동의 하에 IEEE Std 802.3bpTM-2016, IEEE

Standard for Ethernet - Amendment 4: Physical Layer Specifications and

Management Parameters for 1 Gb/s Operation over a Single Twisted-Pair Copper

Cable, 2016.06.30을 기반으로 재발행 되었으며, 본 문서에 대한 저작권은 IEEE,

445 Hoes Lane Piscataway, NJ, USA에 있습니다.

3.2 인용 표준과 본 표준의 비교표

TTAE.IE-802.3bp-2016 IEEE Std 802.3bpTM-2016 비고

1. 머리말 1. Introduction 동일


TTAE.IE-802.3bp-2016 ii

30. 관리 30. Management 동일

34. 1000Mb/s 기저 대역 네트워크 소개 34. Introduction to 1000 Mb/s

baseband network

동일

45. 관리 데이터 입/출력 (MDIO)

인터페이스

45. Management Data Input/Output

(MDIO) Interface

동일

78. 에너지 고효율 이더넷 (EEE) 78. Energy-Efficient Ethernet (EEE) 동일

97. 물리 부호화 부계층 (PCS), 물리

매체 접속(PMA) 부계층 및 기저 대역

매체, 유형 1000BASE-T1

97. Physical Coding Sublayer (PCS),

Physical Medium Attachment (PMA)

sublayer, and baseband medium, type

1000BASE-T1

동일

98. 단일 디퍼런셜 페어 매체에서의 자동

협상

98. Auto-Negotiation for single

differential-pair media

동일

부속서 97A (규정) 공통 모드 변환 시험

방법론

Annex 97A (normative) Common mode

conversion test methodology

동일

부속서 97B (규정) 이질 누화 시험 절차 Annex 97B (normative) Alien Crosstalk

Test Procedure

동일

부속서 98A (규정) 선택자 필드 정의 Annex 98A (normative) Selector Field

definitions

동일

부속서 98B (규정) IEEE 802.3 선택자

기본 페이지 정의

Annex 98B (normative) IEEE 802.3

Selector Base Page definition

동일

부속서 98C (규정) 넥스트 페이지 메시지

코드 필드 정의

Annex 98C (normative) Next Page

Message Code Field definitions

동일


TTAE.IE-802.3bp-2016 iii

Preface

1 Purpose

The purpose of this standard is to define 1000BASE-T1 Ethernet physical layer (PHY)

specifications and management parameters for 1 Gb/s operation on a single twisted-

pair copper cable in an automotive application.

2 Summary

This standard specifies Management Data Input/Output (MDIO) Interface, Physical

Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, baseband

medium type for 1000BASE-T1. This standard also specifies auto-negotiation for

single differential-pair media and Energy-Efficient Ethernet (EEE) function for 1 Gb/s

operation over a Single Twisted-Pair Copper Cable

3 Relationship to Reference Standards

This standard is full equivalent to IEEE Std 802.3bpTM-2016, Amendment 4:

Physical Layer Specifications and Management Parameters for 1 Gb/s Operation

over a Single Twisted-Pair Copper Cable

This TTA Adoption is based on IEEE Std 802.3bpTM-2016, IEEE Standard for

Ethernet - Amendment 4: Physical Layer Specifications and Management

Parameters for 1 Gb/s Operation over a Single Twisted-Pair Copper Cable, 30

June 2016, Copyright IEEE, All rights reserved, 445 Hoes Lane Piscataway, NJ,

USA. Reprinted pursuant to license agreement with IEEE


TTAE.IE-802.3bp-2016 iv

목 차

1. 머리말 ························································································ 24

1.3 규정 참고 문헌 ············································································ 24

1.4 정의 ························································································· 24

1.5 약어 ························································································· 24

30. 관리 ···························································································· 25

30.3 데이터 터미널 장비(DTE)를 위한 계층 관리 ········································ 25

30.5 매체 부속 장치 (MAU)를 위한 계층 관리 ··········································· 25

30.6 링크 자동 협상 관리 ···································································· 26

34. 1000 Mb/s 기저 대역 네트워크 소개 ····················································· 28

34.1 개요 ······················································································· 28

45. 관리 데이터 입/출력 (MDIO) 인터페이스 ··············································· .29

45.2 MDIO 인터페이스 레지스터 ··························································· .29

45.5 MDIO 인터페이스에 대한 프로토콜 구현 적합성 명세서 (PICS) 형식 ·········· 51

78. 에너지 고효율 이더넷 (EEE ································································ 57

78.1 개요 ······················································································· 57

78.2 LPI (Low Power Idle) 모드 타이밍 파라미터 기술 ·································· 57

78.5 통신 링크 접속 지연 ···································································· 58

97. 물리 부호화 부계층 (PCS), 물리 매체 부속(PMA) 부계층 및 기저 대역 매체, 유형

1000BASE-T1 ····················································································· 59

97.1 개요 ······················································································ .59

97.2 1000BASE-T1 서비스 프리미티브 및 인터페이스 ·································· 64

97.3 물리 부호화 부계층 (PCS)····························································· 73

97.4 물리 매체 부속 (PMA) 부계층 ······················································ 111

97.5 PMA 전기적 규격 ······································································ 128

97.6 링크 세그먼트 특성 ··································································· 136

97.7 매체 종속 인터페이스 (MDI) ························································ 146

97.8 관리 인터페이스 ······································································· 147

97.9 환경적 규격 ············································································ 148

97.10 지연 제약 ············································································· 148

97.11 97절 1000BASE-T1 PCS, PMA, 기저대역에 대한 프로토콜 구현 적합성 명세

서 (PICS) 양식 ··············································································· 150


TTAE.IE-802.3bp-2016 v

98. 단일 디퍼런셜 페어 매체에서의 자동 협상 ············································ 164

98.1 개요 ····················································································· 164

98.2 기능적 규격 ············································································ 164

98.3 상태 다이어그램 변수의 자동 협상 레지스터로의 변환 ························· 175

98.4 기술 종속 인터페이스 ································································ 175

98.5 세부 기능 및 상태 다이어그램 ······················································ 176

98.6 98절 단일 디퍼런셜 페어 매체를 위한 자동 협상에 대한 프로토콜 구현 적합성

명세서 (PICS) 양식 ·········································································· 189

부속서 97A (규정) 공통 모드 변환 시험 방법론 ··········································· 196

부속서 97B (규정) 이질 누화 시험 절차 ···················································· 200

부속서 98A (규정) 선택자 필드 정의 ························································ 205

부속서 98B (규정) IEEE 802.3 선택자 기본 페이지 정의 ································· 206

부속서 98C (규정) 넥스트 페이지 메시지 코드 필드 정의 ······························ .208

IEEE Standard for Ethernet

Amendment 4: Physical Layer Specifications and Management Parameters for 1 Gb/s Operation over a Single Twisted-Pair Copper Cable

Sponsored by the LAN/MAN Standards Committee

IEEE 3 Park Avenue New York, NY 10016-5997 USA

IEEE Computer Society

IEEE Std 802.3bp™-2016 (Amendment to

IEEE Std 802.3™-2015 as amended by

IEEE Std 802.3bw™-2015, IEEE Std 802.3by™-2016, and

IEEE Std 802.3bq™-2016)

Authorized licensed use limited to: IEEE 802 Committee. Downloaded on October 05,2016 at 01:42:17 UTC from IEEE Xplore. Restrictions apply.

IEEE Std 802.3bp™-2016(Amendment to

IEEE Std 802.3™-2015as amended by

IEEE Std 802.3bw™-2015,IEEE Std 802.3by™-2016, and

IEEE Std 802.3bq™-2016)



Sponsor

LAN/MAN Standards Committeeof theIEEE Computer Society

Approved 30 June 2016

IEEE-SA Standards Board


The Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USA

Copyright © 2016 by The Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 9 September 2016. Printed in the United States of America.

IEEE and 802 are registered trademarks in the U.S. Patent & Trademark Office, owned by The Institute of Electrical and Electronics Engineers, Incorporated.

Print: ISBN 978-1-5044-2288-8 STD21091PDF: ISBN 978-1-5044-2289-5 STDPD21091

IEEE prohibits discrimination, harassment, and bullying.For more information, visit http://www.ieee.org/web/aboutus/whatis/policies/p9-26.html.No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher.

2Copyright © 2016 IEEE. All rights reserved.

Abstract: This amendment to IEEE Std 802.3-2015 adds point-to-point 1 Gb/s Physical Layer(PHY) specifications and management parameters for operation on a single twisted-pair coppercable in an automotive application.

Keywords: 1000BASE-T1, Ethernet, IEEE 802®, IEEE 802.3™, IEEE 802.3bp™


http://www.ieee.org/web/aboutus/whatis/policies/p9-26.html


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Participants

The following individuals were officers and members of the IEEE 802.3 Working Group at the beginning ofthe IEEE P802.3bp Working Group ballot. Individuals may have not voted, voted for approval, disapproval,or abstained on this standard.

David J. Law, IEEE 802.3 Working Group ChairAdam Healey, IEEE 802.3 Working Group Vice-ChairPeter Anslow, IEEE 802.3 Working Group Secretary

Steven B. Carlson, IEEE 802.3 Working Group Executive SecretaryValerie Maguire, IEEE 802.3 Working Group Treasurer

Steven B. Carlson, IEEE P802.3bp 1000BASE-T1 Task Force ChairMarek Hajduczenia, IEEE P802.3bp 1000BASE-T1 Task Force Editor-in-Chief

Curtis Donahue, IEEE P802.3bp 1000BASE-T1 Task Force PICS Editor

John AbbottDavid AbramsonShadi AbughazalehFaisal AhmadDale AmasonJ. Michael AndrewarthaOleksandr BabenkoKwang-Hyun BaekAmrik BainsKoussalya BalasubramanianThananya BaldwinDenis BeaudoinChristian BeiaYakov BelopolskyMichael BennettVipul BhattWilliam BlissBrad BoothMartin BoudaDavid BrandtRalf-Peter BraunTheodore BrillhartPaul BrooksDavid BrownMatthew BrownThomas BrownPhillip BrownleeJuan-Carlos CalderonJ. Martin CarrollClark CartyMandeep ChadhaDavid ChalupskyJacky ChangXin ChangDavid ChenWheling ChengAhmad ChiniGolam ChoudhuryKeng Hua ChuangPeter Cibula

Christopher R. ColeKeith ConroyEugene DaiShaoan DaiJohn D’AmbrosiaMike DarlingYair DarshanPiers DaweFred DawsonIan DedicChris DiminicoThuyen DinhDan DoveMike DudekNick DuerDavid DwelleyFrank EffenbergerHesham ElbakouryDavid EstesJohn EwenJosef FallerShahar FeldmanGerman FeyhAlan FlatmanHoward FrazierRichard FroschAndrew GardnerMike GardnerAli GhiasiJoel GoergenZhigang GongSteven GorsheJames GrabaRobert GrowMark GustlinBernie HammondTakehiro HayashiDavid HessYasuo HidakaRiu Hirai

Thomas HogenmuellerBrian HoldenRita HornerBernd HorrmeyerVictor HouLiang-wei HuangYasuhiro HyakutakeScott IrwinKazuhiko IshibeHideki IsonoTom IssenhuthKenneth JacksonAndrew JimenezChad JonesPeter JonesAntony JosephManabu KagamiUpen KaretiKeisuke KawaharaYasuaki KawatsuMichael KelsenYongbum KimJonathan KingScott KippMichael KlempaCurtis KnittleShigeru KobayashiKeisuke KojimaPaul KolesarTom KolzeGlen KramerHans LacknerBrett LaneJeff LapakEfstathios LariosMark LaubachGreg Le CheminantArthur LeeDavid LewisJon Lewis



Lei LiMike Peng LiShaohua LiThomas LichteneggerRu Jian LinRobert LingleJames LiuZhenyu LiuWilliam LoMiklos LukacsKent LustedJeffery MakiJames MalkemusYonatan MalkimanEdwin MalletteArthur MarrisChris MashKirsten MatheusErdem MatogluLaurence MatolaBrett McclellanThomas McdermottJohn McDonoughRichard MeiRichard MellitzBryan MoffittLeo MontreuilPaul MooneyAndy MoorwoodThomas MuellerRon MuirDale MurrayHenry MuyshondtEdward NakamotoGary NichollPaul NikolichKevin NollRonald NordinMark NowellDavid OfeltIchiro OguraTom PalkertHui PanSujan PandeySesha PanguluriCarlos PardoMoon ParkPetar PepeljugoskiGerald PepperRuben Perez De Aranda AlonsoMichael Peters

John PetrillaRick PimpinellaNeven PischlRainer PoehmererWilliam PowellRichard ProdanRick RabinovichSaifur RahmanAdee RanRam RaoAlon RegevDuane RemeinVictor RenteriaMichael ResslPoldi (Pavlick) RimboimMartin RossbachChristopher RothSalvatore RotoloHisaya SakamotoVineet SalunkeSam SambasivanYasuo SasakiFred SchindlerStefan SchneelePeter ScrutonAlexander SeigerNaoshi SerizawaMegha ShanbhagMasood ShariffStephen ShellhammerBazhong ShenMizuki ShiraoKapil ShrikhandeJeff SlavickScott SommersYoshiaki SoneXiaolu SongTom SouvignierBryan SparrowhawkEdward SpraguePeter StassarLeonard StencelRobert StoneSteve SwansonAndre SzczepanekWilliam SzetoBharat TailorAkio TajimaTakayuki TajimaTomoo TakaharaSatoshi Takahashi

Kiyoto TakahataAlexander TanToshiki TanakaMehmet TazebayBrian TeipenGeoffrey ThompsonAlan TipperPirooz TooyserkaniNathan TracyDavid TremblayAlbert TretterStephen TrowbridgeWen-Cheng TsengYoshihiro TsukamotoMike TuAlan UgoliniEd UlrichsSterling A. VadenStefano VallePaul VanderlaanRobert WagnerRobert WangRoy WangTongtong WangXiaofeng WangXinyuan WangZhong Feng WangMarkus WeberBrian WelchYang WenMatthias WendtOded WertheimMartin WhiteNatalie WienckowskiLudwig WinkelPeter WuYu XuLennart YseboodtTing-Fa YuLiquan YuanHayato YukiGarold YurkoAndrew ZambellJin ZhangYan ZhuangGeorge ZimmermanHelge ZinnerPavel ZivnyGaoling Zou



The following members of the individual balloting committee voted on this standard. Balloters may havevoted for approval, disapproval, or abstention.

Shadi AbughazalehThomas AlexanderRichard AlfvinDale AmasonPeter AnslowButch AntonStefan AustSaman BehtashJacob Ben AryMichael BennettGennaro BoggiaChristian BoigerRalf-Peter BraunNancy BravinTheodore BrillhartWilliam BushJairo Bustos HerediaWilliam ByrdSteven B. CarlsonJuan CarreonMandeep ChadhaMinho CheongAhmad ChiniKeng Hua ChuangPeter CibulaCharles CookRodney CummingsShaoan DaiJohn D’AmbrosiaChristopher DiminicoDaniel DoveSourav DuttaLiu FangfangGerman FeyhMatthias FritscheYukihiro FujimotoJames GrabaRandall GrovesRobert GrowMarek Hajduczenia

Adam HealeyMarco HernandezDavid HessGuido HiertzWerner HoelzlRita HornerTetsushi IkegamiNoriyuki IkeuchiSergiu IordanescuAtsushi ItoMichael Johas TeenerVincent JonesAdri JovinShinkyo KakuPiotr KarockiJohn KayStuart KerryYongbum KimScott KippBruce KraemerMark LaubachDavid J. LawDavid LewisJon LewisArthur H. LightWilliam LoMichael LynchElvis MaculubaValerie MaguireJeffery MakiArthur MarrisMichael MaytumBrett McclellanRichard MellitzBryan MoffittCharles MoorwoodHenry MuyshondtMichael NewmanNick S. A. NikjooSatoshi Obara

Arumugam PaventhanRuben Perez De Aranda AlonsoMichael PetersAdee RanAlon RegevDuane RemeinMaximilian RiegelRobert RobinsonBenjamin RolfeNicola ScantamburloFrank ScheweDieter SchicketanzStefan SchneeleShusaku ShimadaKapil ShrikhandeJu-Hyung SonThomas StaraiPeter StassarEugene StoudenmireWalter StrupplerMitsutoshi SugawaraPatricia ThalerDavid ThompsonGeoffrey ThompsonMichael ThompsonSterling A. VadenDmitri VarsanofievPrabodh VarshneyGeorge VlantisStephen WebbHung-Yu WeiNatalie WienckowskiAndreas WolfPeter WuOren YuenAndrew ZambellZhen ZhouGeorge Zimmerman



When the IEEE-SA Standards Board approved this standard on 30 June 2016, it had the followingmembership:

Jean-Philippe Faure, ChairTed Burse, Vice Chair

John D. Kulick, Past ChairKonstantinos Karachalios, Secretary

*Member Emeritus

Chuck AdamsMasayuki AriyoshiStephen DukesJianbin FanRonald W. HotchkissJ. Travis Griffith

Gary HoffmanMichael Janezic Joseph L. Koepfinger*Hung LingKevin LuGary RobinsonAnnette D. Reilly

Mehmet UlemaYingli WenHoward WolfmanDon WrightYu YuanDaidi Zhong



Introduction

IEEE Std 802.3 was first published in 1985. Since the initial publication, many projects have addedfunctionality or provided maintenance updates to the specifications and text included in the standard. EachIEEE 802.3 project/amendment is identified with a suffix (e.g., IEEE Std 802.3ba™-2010).

The half-duplex Media Access Control (MAC) protocol specified in IEEE Std 802.3-1985 is Carrier SenseMultiple Access with Collision Detection (CSMA/CD). This MAC protocol was key to the experimentalEthernet developed at Xerox Palo Alto Research Center, which had a 2.94 Mb/s data rate. Ethernet at10 Mb/s was jointly released as a public specification by Digital Equipment Corporation (DEC), Intel, andXerox in 1980. Ethernet at 10 Mb/s was approved as an IEEE standard by the IEEE Standards Board in 1983and subsequently published in 1985 as IEEE Std 802.3-1985. Since 1985, new media options, new speeds ofoperation, and new capabilities have been added to IEEE Std 802.3. A full duplex MAC protocol was addedin 1997.

Some of the major additions to IEEE Std 802.3 are identified in the marketplace with their project number.This is most common for projects adding higher speeds of operation or new protocols. For example,IEEE Std 802.3u™ added 100 Mb/s operation (also called Fast Ethernet), IEEE Std 802.3z™ added1000 Mb/s operation (also called Gigabit Ethernet), IEEE Std 802.3ae™ added 10 Gb/s operation (alsocalled 10 Gigabit Ethernet), IEEE Std 802.3ah™ specified access network Ethernet (also called Ethernet inthe First Mile), and IEEE Std 802.3ba added 40 Gb/s operation (also called 40 Gigabit Ethernet) and100 Gb/s operation (also called 100 Gigabit Ethernet). These major additions are all now included in and aresuperseded by IEEE Std 802.3-2015 and are not maintained as separate documents.

At the date of IEEE Std 802.3bp-2016 publication, IEEE Std 802.3 is composed of the followingdocuments:

IEEE Std 802.3-2015

Section One—Includes Clause 1 through Clause 20 and Annex A through Annex H and Annex 4A.Section One includes the specifications for 10 Mb/s operation and the MAC, frame formats, andservice interfaces used for all speeds of operation.

Section Two—Includes Clause 21 through Clause 33 and Annex 22A through Annex 33E. SectionTwo includes management attributes for multiple protocols and speed of operation as well asspecifications for providing power over twisted-pair cabling for multiple operational speeds. It alsoincludes general information on 100 Mb/s operation as well as most of the 100 Mb/s Physical Layerspecifications.

Section Three—Includes Clause 34 through Clause 43 and Annex 36A through Annex 43C. SectionThree includes general information on 1000 Mb/s operation as well as most of the 1000 Mb/s PhysicalLayer specifications.

Section Four—Includes Clause 44 through Clause 55 and Annex 44A through Annex 55B. SectionFour includes general information on 10 Gb/s operation as well as most of the 10 Gb/s Physical Layerspecifications.

This introduction is not part of IEEE Std 802.3bp™-2016, IEEE Standard for Ethernet—Amendment 4: PhysicalLayer Specifications and Management Parameters for 1 Gb/s Operation over a Single Twisted-Pair Copper Cable.



Section Five—Includes Clause 56 through Clause 77 and Annex 57A through Annex 76A. Clause 56through Clause 67 and Clause 75 through Clause 77, as well as associated annexes, specify subscriberaccess and other Physical Layers and sublayers for operation from 512 kb/s to 10 Gb/s, and definesservices and protocol elements that enable the exchange of IEEE 802.3 format frames between stationsin a subscriber access network. Clause 68 specifies a 10 Gb/s Physical Layer specification. Clause 69through Clause 74 and associated annexes specify Ethernet operation over electrical backplanes atspeeds of 1000 Mb/s and 10 Gb/s.

Section Six—Includes Clause 78 through Clause 95 and Annex 83A through Annex 93C. Clause 78specifies Energy-Efficient Ethernet. Clause 79 specifies IEEE 802.3 Organizationally Specific LinkLayer Discovery Protocol (LLDP) type, length, and value (TLV) information elements. Clause 80through Clause 95 and associated annexes include general information on 40 Gb/s and 100 Gb/soperation as well the 40 Gb/s and 100 Gb/s Physical Layer specifications. Clause 90 specifies Ethernetsupport for time synchronization protocols.

IEEE Std 802.3bw-2015

Amendment 1—This amendment includes changes to IEEE Std 802.3-2015 and adds Clause 96. Thisamendment adds 100 Mb/s Physical Layer (PHY) specifications and management parameters foroperation on a single balanced twisted-pair copper cable.

IEEE Std 802.3by-2016

Amendment 2—This amendment includes changes to IEEE Std 802.3-2015 and adds Clause 105through Clause 112, Annex 109A, Annex 109B, Annex 109C, Annex 110A, Annex 110B, andAnnex 110C. This amendment adds MAC parameters, Physical Layers, and management parametersfor the transfer of IEEE 802.3 format frames at 25 Gb/s.

IEEE Std 802.3bq-2016

Amendment 3—This amendment includes changes to IEEE Std 802.3-2015 and adds Clause 113 andAnnex 113A. This amendment adds new Physical Layers for 25 Gb/s and 40 Gb/s operation overbalanced twisted-pair structured cabling systems.

IEEE Std 802.3bp-2016

Amendment 4—This amendment includes changes to IEEE Std 802.3-2015 and adds Clause 97 andClause 98. This amendment adds point-to-point 1 Gb/s Physical Layer (PHY) specifications andmanagement parameters for operation on a single balanced twisted-pair copper cable in automotive andother applications not utilizing the structured wiring plant.

A companion document IEEE Std 802.3.1 describes Ethernet management information base (MIB) modulesfor use with the Simple Network Management Protocol (SNMP). IEEE Std 802.3.1 is updated to addmanagement capability for enhancements to IEEE Std 802.3 after approval of the enhancements.

IEEE Std 802.3 will continue to evolve. New Ethernet capabilities are anticipated to be added within thenext few years as amendments to this standard.





Contents

1. Introduction........................................................................................................................................ 24

1.3 Normative references ............................................................................................................. 241.4 Definitions ............................................................................................................................. 241.5 Abbreviations......................................................................................................................... 24

30. Management....................................................................................................................................... 25

30.3 Layer management for DTEs................................................................................................. 2530.3.2 PHY device managed object class........................................................................... 25

30.3.2.1 PHY device attributes........................................................................... 2530.3.2.1.2 aPhyType ........................................................................ 2530.3.2.1.3 aPhyTypeList.................................................................. 25

30.5 Layer management for medium attachment units (MAUs) ................................................... 2530.5.1 MAU managed object class..................................................................................... 25

30.5.1.1 MAU attributes..................................................................................... 2530.5.1.1.2 aMAUType..................................................................... 2530.5.1.1.4 aMediaAvailable............................................................. 25

30.6 Management for link Auto-Negotiation ................................................................................ 2630.6.1 Auto-Negotiation managed object class.................................................................. 26

30.6.1.1 Auto-Negotiation attributes.................................................................. 2630.6.1.1.3 aAutoNegRemoteSignaling ............................................ 2630.6.1.1.5 aAutoNegLocalTechnologyAbility ................................ 2630.6.1.1.6 aAutoNegAdvertisedTechnologyAbility........................ 2630.6.1.1.7 aAutoNegReceivedTechnologyAbility .......................... 2630.6.1.1.8 aAutoNegLocalSelectorAbility ...................................... 2730.6.1.1.9 aAutoNegAdvertisedSelectorAbility.............................. 2730.6.1.1.10 aAutoNegReceivedSelectorAbility ................................ 27

34. Introduction to 1000 Mb/s baseband network ................................................................................... 28

34.1 Overview................................................................................................................................ 2834.1.5a Auto-Negotiation, type 1000BASE-T1................................................................... 28

45. Management Data Input/Output (MDIO) Interface........................................................................... 29

45.2 MDIO Interface Registers...................................................................................................... 2945.2.1 PMA/PMD registers ................................................................................................ 29

45.2.1.6 PMA/PMD control 2 register (Register 1.7) ........................................ 2945.2.1.6.3 PMA/PMD type selection (1.7.5:0) ................................ 29

45.2.1.14a BASE-T1 PMA/PMD extended ability register (1.18) ........................ 3045.2.1.131 BASE-T1 PMA/PMD control register (Register 1.2100) .................... 30

45.2.1.131.1 BASE-T1 MASTER-SLAVE manual config enable (1.2100.15) .......................................................... 30

45.2.1.131.1 BASE-T1 MASTER-SLAVE config value (1.2100.14)...................................................................... 31

45.2.1.131.2 BASE-T1 Type selection (1.2100.3:0) ........................... 3145.2.1.133 1000BASE-T1 PMA control register (Register 1.2304)...................... 31

45.2.1.133.1 PMA/PMD reset (1.2304.15).......................................... 3145.2.1.133.2 Transmit disable (1.2304.14).......................................... 3245.2.1.133.3 Low power (1.2304.11) .................................................. 32



45.2.1.134 1000BASE-T1 PMA status register (Register 1.2305) ........................ 3245.2.1.134.1 1000BASE-T1 OAM ability (1.2305.11) ....................... 3245.2.1.134.2 EEE ability (1.2305.10) .................................................. 3245.2.1.134.3 Receive fault ability (1.2305.9) ...................................... 3245.2.1.134.4 Low-power ability (1.2305.8)......................................... 3345.2.1.134.5 Receive polarity (1.2305.2) ............................................ 3345.2.1.134.6 Receive fault (1.2305.1) ................................................. 3345.2.1.134.7 Receive link status (1.2305.0) ........................................ 34

45.2.1.135 1000BASE-T1 training register (Register 1.2306) .............................. 3445.2.1.135.1 User field (1.2306.10:4).................................................. 3445.2.1.135.2 1000BASE-T1 OAM advertisement (1.2306.1)............. 3445.2.1.135.3 EEE advertisement (1.2306.0)........................................ 34

45.2.1.136 1000BASE-T1 link partner training register (Register 1.2307)........... 3445.2.1.136.1 Link partner user field (1.2307.10:4).............................. 3545.2.1.136.2 Link partner 1000BASE-T1 OAM advertisement

(1.2307.1)........................................................................ 3545.2.1.136.3 Link partner EEE advertisement (1.2307.0) ................... 35

45.2.1.137 1000BASE-T1 test mode control register (Register 1.2308) ............... 3545.2.1.137.1 Test mode control (1.2308.15:13) .................................. 35

45.2.3 PCS Registers .......................................................................................................... 3645.2.3.51 1000BASE-T1 PCS control register (Register 3.2304) ....................... 36

45.2.3.51.1 PCS reset (3.2304.15) ..................................................... 3745.2.3.51.2 Loopback (3.2304.14)..................................................... 37

45.2.3.52 1000BASE-T1 PCS status 1 register (Register 3.2305)....................... 3745.2.3.52.1 Tx LPI received (3.2305.11)........................................... 3845.2.3.52.2 Rx LPI received (3.2305.10) .......................................... 3845.2.3.52.3 Tx LPI indication (3.2305.9) .......................................... 3845.2.3.52.4 Rx LPI indication (3.2305.8) .......................................... 3845.2.3.52.5 Fault (3.2305.7) .............................................................. 3945.2.3.52.6 PCS receive link status (3.2305.2).................................. 39

45.2.3.53 1000BASE-T1 PCS status 2 register (Register 3.2306)....................... 3945.2.3.53.1 Receive link status (3.2306.10) ...................................... 3945.2.3.53.2 PCS high BER (3.2306.9)............................................... 3945.2.3.53.3 PCS block lock (3.2306.8).............................................. 4045.2.3.53.4 Latched high BER (3.2306.7)......................................... 4045.2.3.53.5 Latched block lock (3.2306.6) ........................................ 4045.2.3.53.6 BER count (3.2306.5:0).................................................. 40

45.2.3.54 1000BASE-T1 OAM transmit register (Register 3.2308) ................... 4045.2.3.54.1 1000BASE-T1 OAM message valid (3.2308.15)........... 4145.2.3.54.2 Toggle value (3.2308.14)................................................ 4145.2.3.54.3 1000BASE-T1 OAM message received (3.2308.13) ..... 4145.2.3.54.4 Received message toggle value (3.2308.12) .................. 4145.2.3.54.5 Message number (3.2308.11:8) ...................................... 4145.2.3.54.6 Ping received (3.2308.3)................................................. 4245.2.3.54.7 Ping transmit (3.2308.2) ................................................. 4245.2.3.54.8 Local SNR (3.2308.1:0).................................................. 42

45.2.3.55 1000BASE-T1 OAM message register (Registers 3.2309 to 3.2312) ................................................................ 42

45.2.3.56 1000BASE-T1 OAM receive register (Register 3.2313) ..................... 4245.2.3.56.1 Link partner 1000BASE-T1 OAM message

valid (3.2313.15)............................................................. 4245.2.3.56.2 Link partner toggle value (3.2313.14) ............................ 4245.2.3.56.3 Link partner message number (3.2313.11:8).................. 4345.2.3.56.4 Link partner SNR (3.2313.1:0)....................................... 43



45.2.3.57 Link partner 1000BASE-T1 OAM message register (Registers 3.2314 to 3.2317) ................................................................ 43

45.2.7 Auto-Negotiation registers ...................................................................................... 4445.2.7.14c BASE-T1 AN control register (Register 7.512)................................... 45

45.2.7.14c.1 AN reset (7.512.15) ........................................................ 4545.2.7.14c.2 Auto-Negotiation enable (7.512.12) ............................... 4545.2.7.14c.3 Restart Auto-Negotiation (7.512.9) ................................ 46

45.2.7.14d BASE-T1 AN status (Register 7.513) .................................................. 4645.2.7.14d.1 Page received (7.513.6) .................................................. 4645.2.7.14d.2 Auto-Negotiation complete (7.513.5)............................. 4745.2.7.14d.3 Remote fault (7.513.4).................................................... 4745.2.7.14d.4 Auto-Negotiation ability (7.513.3) ................................. 4745.2.7.14d.5 Link status (7.513.2) ....................................................... 47

45.2.7.14e BASE-T1 AN advertisement register (Registers 7.514, 7.515, and 7.516)...................................................... 47

45.2.7.14f BASE-T1 AN LP Base Page ability register (Registers 7.517, 7.518, and 7.519)...................................................... 48

45.2.7.14g BASE-T1 AN Next Page transmit register (Registers 7.520, 7.521, and 7.522)...................................................... 48

45.2.7.14h BASE-T1 AN LP Next Page ability register (Registers 7.523, 7.524, and 7.525)...................................................... 49

45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, Management Data Input/Output (MDIO) interface ............................................................... 5145.5.3 PICS proforma tables for the Management Data Input Output (MDIO)

interface ................................................................................................................... 5145.5.3.3 PMA/PMD management functions ...................................................... 5145.5.3.7 PCS management functions ................................................................. 5345.5.3.9 Auto-Negotiation management functions ............................................ 55

78. Energy-Efficient Ethernet (EEE) ....................................................................................................... 57

78.1 Overview................................................................................................................................ 5778.1.3 Reconciliation sublayer operation ........................................................................... 57

78.1.3.3 PHY LPI operation............................................................................... 5778.1.3.3.1 PHY LPI transmit operation ........................................... 57

78.2 LPI mode timing parameters description............................................................................... 5778.5 Communication link access latency....................................................................................... 58

97. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium, type 1000BASE-T1............................................................................................. 59

97.1 Overview................................................................................................................................ 5997.1.1 Relationship of 1000BASE-T1 to other standards .................................................. 5997.1.2 Operation of 1000BASE-T1.................................................................................... 59

97.1.2.1 Physical Coding Sublayer (PCS).......................................................... 6197.1.2.2 Physical Medium Attachment (PMA) sublayer ................................... 6197.1.2.3 EEE capability...................................................................................... 6297.1.2.4 Link Synchronization ........................................................................... 62

97.1.3 Signaling.................................................................................................................. 6497.1.4 Interfaces ................................................................................................................. 6497.1.5 Conventions in this clause ....................................................................................... 64

97.2 1000BASE-T1 Service Primitives and Interfaces ................................................................. 6497.2.1 Technology Dependent Interface ............................................................................ 65

97.2.1.1 PMA_LINK.request ............................................................................. 65



97.2.1.1.1 Semantics of the primitive .............................................. 6597.2.1.1.2 When generated .............................................................. 6597.2.1.1.3 Effect of receipt .............................................................. 65

97.2.1.2 PMA_LINK.indication......................................................................... 6597.2.1.2.1 Semantics of the primitive .............................................. 6597.2.1.2.2 When generated .............................................................. 6697.2.1.2.3 Effect of receipt .............................................................. 66

97.2.2 PMA service interface ............................................................................................. 6697.2.2.1 PMA_TXMODE.indication ................................................................. 66

97.2.2.1.1 Semantics of the primitive .............................................. 6697.2.2.1.2. When generated .............................................................. 6797.2.2.1.3 Effect of receipt .............................................................. 67

97.2.2.2 PMA_CONFIG.indication ................................................................... 6897.2.2.2.1 Semantics of the primitive .............................................. 6897.2.2.2.2 When generated .............................................................. 6897.2.2.2.3 Effect of receipt .............................................................. 68

97.2.2.3 PMA_UNITDATA.request .................................................................. 6897.2.2.3.1 Semantics of the primitive .............................................. 6897.2.2.3.2 When generated .............................................................. 6897.2.2.3.3 Effect of receipt .............................................................. 68

97.2.2.4 PMA_UNITDATA.indication.............................................................. 6997.2.2.4.1 Semantics of the primitive .............................................. 6997.2.2.4.2 When generated .............................................................. 6997.2.2.4.3 Effect of receipt .............................................................. 69

97.2.2.5 PMA_SCRSTATUS.request ................................................................ 6997.2.2.5.1 Semantics of the primitive .............................................. 6997.2.2.5.2 When generated .............................................................. 6997.2.2.5.3 Effect of receipt .............................................................. 69

97.2.2.6 PMA_PCSSTATUS.request ................................................................ 6997.2.2.6.1 Semantics of the primitive .............................................. 6997.2.2.6.2 When generated .............................................................. 7097.2.2.6.3 Effect of receipt .............................................................. 70

97.2.2.7 PMA_RXSTATUS.indication.............................................................. 7097.2.2.7.1 Semantics of the primitive .............................................. 7097.2.2.7.2 When generated .............................................................. 7097.2.2.7.3 Effect of receipt .............................................................. 70

97.2.2.8 PMA_PHYREADY.indication ............................................................ 7097.2.2.8.1 Semantics of the primitive .............................................. 7097.2.2.8.2 When generated .............................................................. 7197.2.2.8.3 Effect of receipt .............................................................. 71

97.2.2.9 PMA_REMRXSTATUS.request ......................................................... 7197.2.2.9.1 Semantics of the primitive .............................................. 7197.2.2.9.2 When generated .............................................................. 7197.2.2.9.3 Effect of receipt .............................................................. 71

97.2.2.10 PMA_REMPHYREADY.request ........................................................ 7197.2.2.10.1 Semantics of the primitive .............................................. 7197.2.2.10.2 When generated .............................................................. 7297.2.2.10.3 Effect of receipt .............................................................. 72

97.2.2.11 PMA_PCS_RX_LPI_STATUS.request............................................... 7297.2.2.11.1 Semantics of the primitive .............................................. 7297.2.2.11.2 When generated .............................................................. 7297.2.2.11.3 Effect of receipt .............................................................. 72

97.2.2.12 PMA_PCS_TX_LPI_STATUS.request ............................................... 7297.2.2.12.1 Semantics of the primitive .............................................. 72



97.2.2.12.2 When generated .............................................................. 7297.2.2.12.3 Effect of receipt .............................................................. 73

97.3 Physical Coding Sublayer (PCS) ........................................................................................... 7397.3.1 PCS service interface (GMII).................................................................................. 7397.3.2 PCS functions .......................................................................................................... 73

97.3.2.1 PCS Reset function............................................................................... 7397.3.2.2 PCS Transmit function ......................................................................... 73

97.3.2.2.1 Use of blocks .................................................................. 7597.3.2.2.2 81B-RS transmission code.............................................. 7597.3.2.2.3 Notation conventions ...................................................... 7597.3.2.2.4 Transmission order ......................................................... 7597.3.2.2.5 Block structure................................................................ 7597.3.2.2.6 Control codes .................................................................. 7897.3.2.2.7 Idle .................................................................................. 7997.3.2.2.8 LP_IDLE ........................................................................ 7997.3.2.2.9 Error................................................................................ 7997.3.2.2.10 Transmit process............................................................. 7997.3.2.2.11 RS-FEC encoder ............................................................. 8097.3.2.2.12 PCS scrambler ................................................................ 8197.3.2.2.13 3B2T to PAM3 ............................................................... 8197.3.2.2.14 81B-RS framer................................................................ 8297.3.2.2.15 EEE capability ................................................................ 82

97.3.2.3 PCS Receive function........................................................................... 8397.3.2.3.1 Frame and block synchronization................................... 8497.3.2.3.2 PCS descrambler............................................................. 8497.3.2.3.3 Valid and invalid blocks ................................................. 84

97.3.3 Test-pattern generators ............................................................................................ 8497.3.4 PMA training side-stream scrambler polynomials .................................................. 84

97.3.4.1 Generation of Sn................................................................................... 8597.3.4.2 Generation of symbol Tn ...................................................................... 8597.3.4.3 PMA training mode descrambler polynomials..................................... 85

97.3.5 LPI signaling ........................................................................................................... 8697.3.5.1 LPI Synchronization............................................................................. 8697.3.5.2 Quiet period signaling .......................................................................... 8797.3.5.3 Refresh period signaling....................................................................... 87

97.3.6 Detailed functions and state diagrams..................................................................... 8797.3.6.1 State diagram conventions ................................................................... 8797.3.6.2 State diagram parameters ..................................................................... 88

97.3.6.2.1 Constants ........................................................................ 8897.3.6.2.2 Variables ......................................................................... 8897.3.6.2.3 Functions ........................................................................ 9097.3.6.2.4 Counters.......................................................................... 90

97.3.6.3 Messages .............................................................................................. 9097.3.6.4 State diagrams ...................................................................................... 91

97.3.7 PCS management..................................................................................................... 9597.3.7.1 Status .................................................................................................... 9597.3.7.2 Counter ................................................................................................. 9597.3.7.3 Loopback.............................................................................................. 95

97.3.8 1000BASE-T1 Operations, Administration, and Maintenance (OAM).................. 9697.3.8.1 Definitions............................................................................................ 9697.3.8.2 Functional specifications...................................................................... 96

97.3.8.2.1 1000BASE-T1 OAM Frame Structure ........................... 9697.3.8.2.2 1000BASE-T1 OAM Frame Data .................................. 9797.3.8.2.3 Ping RX .......................................................................... 97



97.3.8.2.4 Ping TX........................................................................... 9797.3.8.2.5 PHY Health..................................................................... 9897.3.8.2.6 1000BASE-T1 OAM Message Valid ............................. 9897.3.8.2.7 1000BASE-T1 OAM Message Toggle........................... 9897.3.8.2.8 1000BASE-T1 OAM Message Acknowledge................ 9897.3.8.2.9 1000BASE-T1 OAM Message Toggle Acknowledge ... 9897.3.8.2.10 1000BASE-T1 OAM Message Number......................... 9997.3.8.2.11 1000BASE-T1 OAM Message Data .............................. 9997.3.8.2.12 CRC16 ............................................................................ 9997.3.8.2.13 1000BASE-T1 OAM Frame Acceptance Criteria.......... 9997.3.8.2.14 PHY Health Indicator ................................................... 10097.3.8.2.15 Ping............................................................................... 10097.3.8.2.16 1000BASE-T1 OAM Message Exchange .................... 100

97.3.8.3 State diagram variable to 1000BASE-T1 OAM register mapping .... 10197.3.8.4 Detailed functions and State Diagrams .............................................. 103

97.3.8.4.1 State diagram conventions............................................ 10397.3.8.4.2 State diagram parameters.............................................. 10397.3.8.4.3 Variables ....................................................................... 10397.3.8.4.4 Counters........................................................................ 10797.3.8.4.5 Functions ...................................................................... 10897.3.8.4.6 State Diagrams.............................................................. 109

97.4 Physical Medium Attachment (PMA) sublayer................................................................... 11197.4.1 PMA functional specifications .............................................................................. 11197.4.2 PMA functions....................................................................................................... 111

97.4.2.1 PMA Reset function ........................................................................... 11297.4.2.2 PMA Transmit function ..................................................................... 112

97.4.2.2.1 Global PMA transmit disable ....................................... 11297.4.2.3 PMA Receive function ....................................................................... 11297.4.2.4 PHY Control function ........................................................................ 113

97.4.2.4.1 InfoField notation ......................................................... 11497.4.2.4.2 Start of Frame Delimiter............................................... 11497.4.2.4.3 Partial PHY frame Count (PFC24)............................... 11497.4.2.4.4 Message Field ............................................................... 11497.4.2.4.5 PHY Capability Bits, User Configurable Register,

and Data Mode Scrambler Seed ................................... 11597.4.2.4.6 Data Switch partial PHY frame Count ......................... 11597.4.2.4.7 Reserved Fields............................................................. 11597.4.2.4.8 CRC16 .......................................................................... 11597.2.4.9 PMA MDIO function mapping..................................... 11697.4.2.4.10 Start-up sequence.......................................................... 11697.4.2.4.11 PHY Control Registers ................................................. 118

97.4.2.5 Link Monitor function........................................................................ 11897.4.2.6 PHY Link Synchronization ................................................................ 119

97.4.2.6.1 State diagram variables................................................. 12097.4.2.6.2 State diagram timers ..................................................... 12197.4.2.6.3 Messages....................................................................... 12197.4.2.6.4 State diagrams............................................................... 122

97.4.2.7 Refresh Monitor function ................................................................... 12397.4.2.8 Clock Recovery function.................................................................... 123

97.4.3 MDI ....................................................................................................................... 12397.4.3.1 MDI signals transmitted by the PHY ................................................. 12397.4.3.2 Signals received at the MDI ............................................................... 123

97.4.4 State variables........................................................................................................ 12397.4.4.1 State diagram variables ...................................................................... 123



97.4.4.2 Timers................................................................................................. 12697.4.5 State diagrams ....................................................................................................... 127

97.5 PMA electrical specifications .............................................................................................. 12897.5.1 EMC Requirements ............................................................................................... 128

97.5.1.1 Immunity—DPI test ........................................................................... 12897.5.1.2 Emission—150 W conducted emission test ....................................... 128

97.5.2 Test modes............................................................................................................. 12897.5.2.1 Test fixtures........................................................................................ 131

97.5.3 Transmitter electrical specifications...................................................................... 13297.5.3.1 Maximum output droop...................................................................... 13397.5.3.2 Transmitter distortion......................................................................... 13397.5.3.3 Transmitter timing jitter ..................................................................... 13497.5.3.4 Transmitter Power Spectral Density (PSD) and power level ............. 13597.5.3.5 Transmitter peak differential output................................................... 13697.5.3.6 Transmitter clock frequency............................................................... 136

97.5.4 Receiver electrical specifications .......................................................................... 13697.5.4.1 Receiver differential input signals...................................................... 13697.5.4.2 Alien crosstalk noise rejection ........................................................... 136

97.6 Link segment characteristics................................................................................................ 13697.6.1 Link transmission parameters for link segment type A......................................... 137

97.6.1.1 Insertion loss ...................................................................................... 13797.6.1.2 Differential characteristic impedance................................................. 13897.6.1.3 Return loss.......................................................................................... 13897.6.1.4 Differential to common mode conversion.......................................... 13897.6.1.5 Maximum link delay .......................................................................... 139

97.6.2 Link transmission parameters for link segment type B ......................................... 14097.6.2.1 Insertion loss ...................................................................................... 14097.6.2.2 Differential characteristic impedance................................................. 14097.6.2.3 Return loss.......................................................................................... 14097.6.2.4 Maximum link delay .......................................................................... 14197.6.2.5 Coupling attenuation .......................................................................... 141

97.6.3 Coupling parameters between type A link segments ............................................ 14297.6.3.1 Multiple disturber alien near-end crosstalk (MDANEXT) loss ......... 14297.6.3.2 Multiple disturber power sum alien near-end crosstalk

(PSANEXT) loss ................................................................................ 14297.6.3.3 Multiple disturber alien far-end crosstalk (MDAFEXT) loss ............ 14397.6.3.4 Multiple disturber power sum alien attenuation crosstalk ratio

far-end (PSAACRF)........................................................................... 14397.6.4 Coupling parameters between type B link segments............................................. 144

97.6.4.1 Multiple disturber alien near-end crosstalk (MDANEXT) loss ......... 14497.6.4.2 Multiple disturber power sum alien near-end crosstalk

(PSANEXT) loss ................................................................................ 14597.6.4.3 Multiple disturber alien far-end crosstalk (MDAFEXT) loss ............ 14597.6.4.4 Multiple disturber power sum alien attenuation crosstalk ratio

far-end (PSAACRF)........................................................................... 14597.7 Media Dependent Interface (MDI) ...................................................................................... 146

97.7.1 MDI connectors ..................................................................................................... 14697.7.2 MDI electrical specification .................................................................................. 146

97.7.2.1 MDI return loss .................................................................................. 14697.7.2.2 MDI mode conversion loss ................................................................ 147

97.7.3 MDI fault tolerance ............................................................................................... 14797.8 Management Interfaces........................................................................................................ 147

97.8.1 Optional Support for Auto-Negotiation................................................................. 14797.9 Environmental specifications............................................................................................... 148



97.9.1 General safety........................................................................................................ 14897.9.2 Network safety....................................................................................................... 148

97.9.2.1 Environmental safety.......................................................................... 14897.9.2.2 Electromagnetic compatibility ........................................................... 148

97.10 Delay constraints.................................................................................................................. 14897.11 Protocol implementation conformance statement (PICS) proforma for Clause 97,

Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium, type 1000BASE-T1........................................................................ 15097.11.1 Introduction ........................................................................................................... 15097.11.2 Identification.......................................................................................................... 150

97.11.2.1 Implementation identification ............................................................ 15097.11.2.2 Protocol summary .............................................................................. 150

97.11.3 Major capabilities/options ..................................................................................... 15197.11.4 General .................................................................................................................. 15197.11.5 Physical Coding Sublayer (PCS)........................................................................... 15297.11.6 PCS Receive functions .......................................................................................... 15397.11.7 PCS loopback ........................................................................................................ 15497.11.8 Physical Medium Attachment (PMA)................................................................... 15597.11.9 PMA electrical specifications................................................................................ 15797.11.10MDI electrical requirements.................................................................................. 160

97.11.10.1 Characteristics of the link segment .................................................... 16097.11.11MDI Requirements ................................................................................................ 16297.11.12EEE capability requirements ................................................................................. 16297.11.13Environmental specifications ................................................................................ 163

98. Auto-Negotiation for single differential-pair media ........................................................................ 164

98.1 Overview.............................................................................................................................. 16498.1.1 Scope ..................................................................................................................... 16498.1.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI)

reference model ..................................................................................................... 16498.2 Functional specifications ..................................................................................................... 164

98.2.1 Transmit function requirements ............................................................................ 16598.2.1.1 DME transmission.............................................................................. 165

98.2.1.1.1 DME page encoding ..................................................... 16598.2.1.1.2 DME page timing ......................................................... 16798.2.1.1.3 DME page Delimiters ................................................... 16898.2.1.1.4 Transmitter peak differential output ............................. 169

98.2.1.2 Link codeword encoding.................................................................... 16998.2.1.2.1 Selector Field ................................................................ 16998.2.1.2.2 Echoed Nonce Field...................................................... 16998.2.1.2.3 Transmitted Nonce Field .............................................. 17098.2.1.2.4 Technology Ability Field.............................................. 17098.2.1.2.5 Force MASTER-SLAVE.............................................. 17098.2.1.2.6 Pause Ability................................................................. 17198.2.1.2.7 Remote Fault................................................................. 17198.2.1.2.8 Acknowledge ................................................................ 17198.2.1.2.9 Next Page...................................................................... 171

98.2.1.3 Transmit Switch function ................................................................... 17298.2.2 Receive function requirements .............................................................................. 172

98.2.2.1 DME page reception........................................................................... 17298.2.2.2 Receive Switch function..................................................................... 17298.2.2.3 Link codeword matching.................................................................... 172

98.2.3 AN half-duplex function requirements.................................................................. 172



98.2.4 Arbitration function requirements ......................................................................... 17298.2.4.1 Renegotiation function ....................................................................... 17398.2.4.2 Priority Resolution function ............................................................... 17398.2.4.3 Next Page function ............................................................................. 173

98.2.4.3.1 Next page encodings..................................................... 17498.2.4.3.2 Use of Next Pages......................................................... 174

98.3 State diagram variable to Auto-Negotiation register mapping ............................................ 17598.4 Technology-Dependent Interface ........................................................................................ 175

98.4.1 PMA_LINK.indication.......................................................................................... 17598.4.1.1 Semantics of the service primitive ..................................................... 17598.4.1.2 When generated.................................................................................. 17698.4.1.3 Effect of receipt.................................................................................. 176

98.4.2 PMA_LINK.request .............................................................................................. 17698.4.2.1 Semantics of the service primitive ..................................................... 17698.4.2.2 When generated.................................................................................. 17698.4.2.3 Effect of receipt.................................................................................. 176

98.5 Detailed functions and state diagrams ................................................................................. 17698.5.1 State diagram variables.......................................................................................... 17698.5.2 State diagram timers .............................................................................................. 18398.5.3 State diagram counters .......................................................................................... 18498.5.4 Function................................................................................................................. 18598.5.5 State diagrams ....................................................................................................... 185

98.6 Protocol implementation conformance statement (PICS) proforma for Clause 98, Auto-Negotiation for Single Differential-Pair Media.......................................................... 18998.6.1 Introduction ........................................................................................................... 18998.6.2 Identification.......................................................................................................... 189

98.6.2.1 Implementation identification ............................................................ 18998.6.2.2 Protocol summary .............................................................................. 189

98.6.3 General .................................................................................................................. 19098.6.4 DME transmission ................................................................................................. 19098.6.5 Link codeword encoding ....................................................................................... 19198.6.6 Arbitration function requirements ......................................................................... 19398.6.7 Service primitives.................................................................................................. 19498.6.8 State diagram and variable definitions .................................................................. 194

Annex 97A (normative) Common mode conversion test methodology ...................................................... 196

97A.1 Introduction.................................................................................................................. 19697A.2 Test configuration and measurement ........................................................................... 19697A.3 Protocol implementation conformance statement (PICS) proforma for

Annex 97A, Common mode conversion test methodology......................................... 19897A.3.1 Introduction ................................................................................................. 19897A.3.2 Identification................................................................................................ 198

97A.3.2.1 Implementation identification ..................................................... 19897A.3.2.2 Protocol summary........................................................................ 198

97A.3.3 Major capabilities/options ........................................................................... 199

Annex 97B (normative) Alien Crosstalk Test Procedure ............................................................................ 200

97B.1 Introduction.................................................................................................................. 20097B.1.1 Alien crosstalk test configurations .............................................................. 200

97B.2 Alien crosstalk coupled between type A link segments .............................................. 20097B.3 Cable bundling............................................................................................................. 201



97B.4 Protocol implementation conformance statement (PICS) proforma for Annex 97B, Alien Crosstalk Test Procedure ............................................................... 20397B.4.1 Introduction ................................................................................................. 20397B.4.2 Identification................................................................................................ 203

97B.4.2.1 Implementation identification ..................................................... 20397B.4.2.2 Protocol summary........................................................................ 203

97B.4.3 Major capabilities/options ........................................................................... 204

Annex 98A (normative) Selector Field definitions...................................................................................... 205

98A.1 Introduction.................................................................................................................. 205

Annex 98B (normative) IEEE 802.3 Selector Base Page definition ........................................................... 206

98B.1 Introduction.................................................................................................................. 20698B.2 Selector field value ...................................................................................................... 20698B.3 Technology Ability Field bit assignments ................................................................... 20698B.4 Priority Resolution....................................................................................................... 20698B.5 Message Page transmission convention....................................................................... 207

Annex 98C (normative) Next Page Message Code Field definitions .......................................................... 208

98C.1 Introduction.................................................................................................................. 20898C.2 Message code 1—Null Message code ......................................................................... 20898C.3 Message code 5—Organizationally Unique Identifier (OUI) tag code ....................... 20898C.4 Message code 6—AN device identifier tag code......................................................... 209





IMPORTANT NOTICE: IEEE Standards documents are not intended to ensure safety, health, orenvironmental protection, or ensure against interference with or from other devices or networks.Implementers of IEEE Standards documents are responsible for determining and complying with allappropriate safety, security, environmental, health, and interference protection practices and allapplicable laws and regulations.

This IEEE document is made available for use subject to important notices and legal disclaimers. Thesenotices and disclaimers appear in all publications containing this document and may be found under theheading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.”They can also be obtained on request from IEEE or viewed athttp://standards.ieee.org/IPR/disclaimers.html.

(This amendment is based on IEEE Std 802.3™-2015 as amended by IEEE Std 802.3bw™-2015,IEEE Std 802.3by™-2016, and IEEE Std 802.3bq™-2016.)

NOTE—The editing instructions contained in this amendment define how to merge the material contained therein intothe existing base standard and its amendments to form the comprehensive standard.

The editing instructions are shown in bold italic. Four editing instructions are used: change, delete, insert, and replace.Change is used to make corrections in existing text or tables. The editing instruction specifies the location of the changeand describes what is being changed by using strikethrough (to remove old material) and underscore (to add newmaterial). Delete removes existing material. Insert adds new material without disturbing the existing material. Deletionsand insertions may require renumbering. If so, renumbering instructions are given in the editing instruction. Replace isused to make changes in figures or equations by removing the existing figure or equation and replacing it with a newone. Editing instructions, change markings, and this NOTE will not be carried over into future editions because thechanges will be incorporated into the base standard.1

Cross references that refer to clauses, tables, equations, or figures not covered by this amendment are highlighted ingreen.

1Notes in text, tables, and figures are given for information only, and do not contain requirements needed to implement the standard.


http://standards.ieee.org/IPR/disclaimers.html

IEEE Std 802.3bp-2016IEEE Standard for Ethernet—Amendment 4: Physical Layer Specifications and

Management Parameters for 1 Gb/s Operation over a Single Twisted-Pair Copper Cable


1. Introduction

1.3 Normative references

Insert the following references in alphanumeric order:

IEC 62153-4-14:2012, Metallic communication cable test methods—Part 4-14: Electromagneticcompatibility (EMC)—Coupling attenuation of cable assemblies (Field conditions) absorbing clampmethod.

SAE J1292, Automobile and Motor Coach Wiring.

Change CISPR 25 reference, added in IEEE Std 802.3bw-2015, as follows:

IEC CISPR 25 Edition 3.0 2008-03: Vehicles, boats and internal combustion engines—Radio disturbancecharacteristics—Limits and methods of measurement for the protection of on-board receivers.

1.4 Definitions

Insert the following new definition after 1.4.28 1000BASE-T:

1.4.28a 1000BASE-T1: IEEE 802.3 Physical Layer specification for 1000 Mb/s Ethernet using a singletwisted-pair copper cable. (See IEEE Std 802.3, Clause 97.)

Insert the following new definition after 1.4.99 anomaly:

1.4.99a AN half-duplex function: The ability to exchange Auto-Negotiation DME pages over a singledifferential-pair medium. (See IEEE Std 802.3, Clause 98.)

Insert the following new definition after 1.4.107 BASE-R:

1.4.107a BASE-T1: PHYs that belong to the set of specific Ethernet PCS/PMA/PMDs that operate on asingle twisted-pair copper cable, including 100BASE-T1 and 1000BASE-T1. (See IEEE Std 802.3,Clause 96 and Clause 97.)

Insert the following new definition after 1.4.381 single-port device:

1.4.381a single twisted-pair copper cable: Two insulated conductors twisted together in a regular fashionto form a balanced transmission line.

1.5 Abbreviations

Insert the following new abbreviations into the list, in alphanumeric order:

MDAFEXT multiple disturber alien far-end crosstalkMDANEXT multiple disturber alien near-end crosstalk





30. Management

30.3 Layer management for DTEs

30.3.2 PHY device managed object class

30.3.2.1 PHY device attributes

30.3.2.1.2 aPhyType

Insert the following new entry in APPROPRIATE SYNTAX (as modified by IEEE Std 802.3bw-2015,IEEE Std 802.3by-2016, and IEEE Std 802.3bq-2016) after the entry for 1000BASE-T:

1000BASE-T1 Clause 97 1000 Mb/s PAM3

30.3.2.1.3 aPhyTypeList

Insert the following new entry in APPROPRIATE SYNTAX (as modified by IEEE Std 802.3bw-2015,IEEE Std 802.3by-2016, and IEEE Std 802.3bq-2016) after the entry for 1000BASE-T:

1000BASE-T1 Clause 97 1000 Mb/s PAM3

30.5 Layer management for medium attachment units (MAUs)

30.5.1 MAU managed object class

30.5.1.1 MAU attributes

30.5.1.1.2 aMAUType

Insert the following new entry in APPROPRIATE SYNTAX (as modified by IEEE Std 802.3bw-2015,IEEE Std 802.3by-2016. and IEEE Std 802.3bq-2016) after the entry for 1000BASE-TFD:

1000BASE-T1 single twisted-pair copper cable PHY as specified in Clause 97

30.5.1.1.4 aMediaAvailable

Insert the following new text into the third paragraph of BEHAVIOUR DEFINED AS (as modified byIEEE Std 802.3bw-2015, IEEE Std 802.3by-2016, and IEEE Std 802.3bq-2016) after the third sentenceinserted by IEEE Std 802.3bw:

For 1000BASE-T1, a link_status of OK maps to the enumeration “available”. All other states of link_status map to the enumeration “not available”.;

Change the fourth sentence of the third paragraph of BEHAVIOUR DEFINED AS (as modified byIEEE Std 802.3bw-2015, IEEE Std 802.3by-2016, and IEEE Std 802.3bq-2016) as follows:

Any MAU that implements management of Clause 28, or Clause 73, or Clause 98 Auto-Negotiation willmap remote fault indication to MediaAvailable “remote fault.”





30.6 Management for link Auto-Negotiation

30.6.1 Auto-Negotiation managed object class

30.6.1.1 Auto-Negotiation attributes

30.6.1.1.3 aAutoNegRemoteSignaling

Change the BEHAVIOUR DEFINED AS for the attribute as follows:

BEHAVIOUR DEFINED AS:The value indicates whether the remote end of the link is operating Auto-Negotiation signalingor not. It shall take the value detected if, during the previous link negotiation, FLP Bursts, /C/ordered sets (see 36.2.4.10) or DME signals (see 73.5 and 98.2.1.1) were received from theremote end.;

30.6.1.1.5 aAutoNegLocalTechnologyAbility

Insert the following new entry in APPROPRIATE SYNTAX (as modified by IEEE Std 802.3by-2016)after the entry for 1000BASE-TFD:

1000BASE-T1 1000BASE-T1 as specified in Clause 97

Change the following entry in APPROPRIATE SYNTAX (as modified by IEEE Std 802.3by-2016) asfollows:

Rem Fault Remote fault bit (RF) as specified in Clause 73 and Clause 98

Insert the following new entry in APPROPRIATE SYNTAX (as modified by IEEE Std 802.3by-2016) afterthe entry for BASE-RFEC25G Req inserted by IEEE Std 802.3by-2016:

Force MS Force MASTER-SLAVE as specified in Clause 98 (see 98.2.1.2.5)


BEHAVIOUR DEFINED AS:This indicates the technology ability of the local device, as defined in Clause 28, Clause 37,and Clause 73, and Clause 98.;

30.6.1.1.6 aAutoNegAdvertisedTechnologyAbility


BEHAVIOUR DEFINED AS:This GET-SET attribute maps to the technology ability of the local device, as defined inClause 28, and Clause 37, and Clause 98.

30.6.1.1.7 aAutoNegReceivedTechnologyAbility


BEHAVIOUR DEFINED AS:Indicates the advertised technology ability of the remote hardware. For Clause 28Auto-Negotiation, this attribute maps to the Technology Ability Field of the last received





Auto- Negotiation link codeword(s). For Clause 37 Auto-Negotiation, this attribute maps tobits D0-D13 of the received Config_Reg Base Page (see 37.2.1). For Clause 73 Auto-Negotiation, this attribute maps to bits D10-D13 and D21-D47 of the last received linkcodeword Base Page (see 73.6). For Clause 98 Auto-Negotiation, this attribute maps to bitsD10-D13 and D21-D47 of the last received link codeword Base Page (see 98.2.1.2).;

30.6.1.1.8 aAutoNegLocalSelectorAbility


BEHAVIOUR DEFINED AS:This indicates the value of the selector field of the local hardware. The Selector Field isdefined in 28.2.1.2.1 for Clause 28 Auto-Negotiation, in and 73.6.1 for Clause 73Auto-Negotiation, and in 98.2.1.2.1 for Clause 98 Auto-Negotiation. The enumeration of theSelector Field indicates the standard that defines the remaining encodings for Auto-Negotiation using that value of enumeration. For Clause 37 Auto-Negotiation devices, a SETof this attribute will have no effect, and a GET will return the enumeration “ethernet”.;

30.6.1.1.9 aAutoNegAdvertisedSelectorAbility


BEHAVIOUR DEFINED AS:In the case of Clause 28 Auto-Negotiation, this GET-SET attribute maps to the MessageSelector Field of the Auto-Negotiation link codeword. For Clause 73 Auto-Negotiation, thisattribute maps to the Selector Field of the Clause 73 Auto-Negotiation link codeword (see73.6.1). For Clause 98 Auto-Negotiation, this attribute maps to the Selector Field of theClause 98 Auto-Negotiation link codeword (see 98.2.1.2.1). A SET operation to a value notavailable in aAutoNegLocalSelectorAbility will be rejected. A successful SET operation willresult in immediate link renegotiation if aAutoNegAdminState is enabled. For Clause 37 Auto-Negotiation devices, a SET of this attribute will have no effect, and a GET will return theenumeration “ethernet”.

30.6.1.1.10 aAutoNegReceivedSelectorAbility


BEHAVIOUR DEFINED AS:In the case of Clause 28 Auto-Negotiation, this attribute indicates the advertised messagetransmission ability of the remote hardware. It maps to the Message Selector Field of the lastreceived Auto-Negotiation link codeword. For Clause 73 Auto-Negotiation, this attributeindicates the advertised message transmission ability of the remote hardware and maps to theSelector Field of the last received Clause 73 Auto-Negotiation link codeword (see 73.6.1). ForClause 98 Auto-Negotiation, this attribute indicates the advertised message transmissionability of the remote hardware and maps to the Selector Field of the last received Clause 98Auto-Negotiation link codeword (see 98.2.1.2.1). For Clause 37 Auto- Negotiation devices, aSET of this attribute will have no effect, and a GET will return the enumeration “ethernet”.;





34. Introduction to 1000 Mb/s baseband network

34.1 Overview

Insert a new subclause 34.1.5a after 34.1.5, with text on the support of Auto-Negotiation capability in1000BASE-T1 PHY:

34.1.5a Auto-Negotiation, type 1000BASE-T1

Auto-Negotiation (Clause 98) may be used by 1000BASE-T1 devices to detect the abilities (modes ofoperation) supported by the device at the other end of a link segment, determine common abilities, andconfigure for joint operation. Auto-Negotiation is performed upon link start-up through the use of half-duplex differential Manchester encoding.

The use of Clause 98 Auto-Negotiation is optional for a 1000BASE-T1 PHY.





45. Management Data Input/Output (MDIO) Interface

45.2 MDIO Interface Registers

45.2.1 PMA/PMD registers

Change the row for 1.2103 through 1.32767 (as modified by IEEE Std 802.3by-2016 andIEEE Std 802.3bw-2015) in Table 45-3 as follows (unchanged rows not shown)

45.2.1.6 PMA/PMD control 2 register (Register 1.7)

45.2.1.6.3 PMA/PMD type selection (1.7.5:0)

Change definition of value 1 1 1 1 0 1 for bits 1.7.5:0 in Table 45–7 (as added by IEEE Std 802.3bw-2015)as follows (unchanged rows not shown):

Table 45–3—PMA/PMD registers

Register address Register name Subclause

1.2103 through 1.327672303

Reserved

1.2304 1000BASE-T1 PMA control 45.2.1.133

1.2305 1000BASE-T1 PMA status 45.2.1.134

1.2306 1000BASE-T1 training 45.2.1.135

1.2307 1000BASE-T1 link partner training 45.2.1.136

1.2308 1000BASE-T1 test mode control 45.2.1.137

1.2309 through 32767 Reserved

Table 45–7—PMA/PMD control 2 register bit definitions

Bit(s) Name Description R/Wa

aR/W = Read/Write, RO = Read only

1.7.5:0 PMA/PMD type selection 5 4 3 2 1 01 1 1 1 0 1 = 100BASE-T1 PMA/PMDb

bIf BASE-T1 is selected, bits 1.2100.3:0 are used to differentiate which BASE-T1 PMA/PMD is selected.

R/W





45.2.1.14a BASE-T1 PMA/PMD extended ability register (1.18)

Change Table 45–17a (as added by IEEE Std 802.3bw-2015) as follows:

45.2.1.131 BASE-T1 PMA/PMD control register (Register 1.2100)

Change 45.2.1.131 (added by IEEE Std 802.3bw-2015) as follows:

The assignment of bits in the BASE-T1 PMA/PMD control register is shown in Table 45–98a.

Delete 45.2.1.131.1 and renumber 45.2.1.131.2 and 45.2.1.131.3 to 45.2.1.131.1 and 45.2.1.131.2. Changerenumbered 45.2.1.131.1 and 45.2.1.131.2 (as added by IEEE Std 802.3bw-2015) as follows:

45.2.1.131.1 BASE-T1 MASTER-SLAVE manual config enable (1.2100.15)

Bit 1.2100.15 returns a one to indicate that MASTER or SLAVE configuration is set manually.

Table 45–17a—BASE-T1 PMA/PMD extended ability register bit definitions


aRO = Read only

1.18.15:12 Reserved Value always 0 RO

1.18.1 1000BASE-T1 ability 1 = PMA/PMD is able to perform 1000BASE-T10 = PMA/PMD is not able to perform 1000BASE-T1

RO

1.18.0 100BASE-T1 ability 1 = PMA/PMD is able to perform 100BASE-T10 = PMA/PMD is not able to perform 100BASE-T1

RO

Table 45–98a—BASE-T1 PMA/PMD control register bit definitions


aRO = Read only, R/W = Read/Write

1.2100.15 MASTER-SLAVE manual config enableReserved

Value always 1 RO

1.2100.14 MASTER-SLAVEconfig value

1 = Configure PHY as MASTER0 = Configure PHY as SLAVE

R/W


1.2100.3:0 Type sSelection 3 2 1 01 x x x = Reserved for future use0 1 x x = Reserved for future use0 0 1 x = Reserved for future use0 0 0 1 = Reserved for future use1000BASE-T10 0 0 0 = 100BASE-T1

R/W





45.2.1.131.1 BASE-T1 MASTER-SLAVE config value (1.2100.14)

Bit 1.2100.14 is used to select MASTER or SLAVE operation when MASTER-SLAVE manual configenable bit 1.2100.15 is set to oneAuto-Negotiation enable bit 7.512.12 is set to zero, or if Auto-Negotiationis not implemented. If bit 1.2100.14 is set to one the PHY shall operate as MASTER. If bit 1.2100.14 is setto zero the PHY shall operate as SLAVE. This bit shall be ignored when the Auto-Negotiation enable bit7.512.12 is set to one.

45.2.1.131.2 BASE-T1 tType selection (1.2100.3:0)

Bits 1.2100.3:0 are used to set the mode of operation when Auto-Negotiation enable bit 7.512.12 is set tozero, or if Auto-Negotiation is not implemented. When these bits are set to 0000, the mode of operation is100BASE-T1. When these bits are set to 0001, the mode of operation is 1000BASE-T1. These bits shall beignored when the Auto-Negotiation enable bit 7.512.12 is set to one.

Insert 45.2.1.133 through 45.2.1.137 after 45.2.1.132 (as inserted by IEEE Std 802.3bw-2015) as follows:

45.2.1.133 1000BASE-T1 PMA control register (Register 1.2304)

The assignment of bits in the 1000BASE-T1 PMA control register is shown in Table 45–98c.

45.2.1.133.1 PMA/PMD reset (1.2304.15)

Resetting the 1000BASE-T1 PMA/PMD is accomplished by setting bit 1.2304.15 to a one. This action shallset all 1000BASE-T1 PMA/PMD registers to their default states. As a consequence, this action may changethe internal state of the 1000BASE-T1 PMA/PMD and the state of the physical link. This action may alsoinitiate a reset in any other MMDs that are instantiated in the same package. This bit is self-clearing, and the1000BASE-T1 PMA/PMD shall return a value of one in bit 1.2304.15 when a reset is in progress; otherwise,it shall return a value of zero. The 1000BASE-T1 PMA/PMD is not required to accept a write transaction toany of its registers until the reset process is completed. The control and management interface shall berestored to operation within 0.5 s from the setting of bit 1.2304.15.

During a reset, the 1000BASE-T1 PMD/PMA shall respond to reads from register bits 1.2304.15, 1.8.15:14,and 1.0.15. All other register bits shall be ignored.

NOTE—This operation may interrupt data communication.

Table 45–98c—1000BASE-T1 PMA control register bit definitions


aRO = Read only, R/W = Read/Write, SC = Self-clearing

1.2304.15 PMA/PMD reset 1 = PMA/PMD reset0 = Normal operation

R/W, SC

1.2304.14 Transmit disable 1 = Transmit disable 0 = Normal operation

R/W


1.2304.11 Low-power 1 = Low-power mode0 = Normal operation

R/W






Bit 1.2304.15 is a copy of 1.0.15 and setting or clearing either bit shall set or clear the other bit. Settingeither bit shall reset the 1000BASE-T1 PMA/PMD.

45.2.1.133.2 Transmit disable (1.2304.14)

When bit 1.2304.14 is set to a one, the PMA shall disable output on the transmit path. When bit 1.2304.14 isset to a zero, the PMA shall enable output on the transmit path.

Bit 1.2304.14 is a copy of 1.9.0 and setting or clearing either bit shall set or clear the other bit. Setting eitherbit shall disable the transmitter.

45.2.1.133.3 Low power (1.2304.11)

When the low-power ability is supported, the 1000BASE-T1 PMA/PMD may be placed into a low-powermode by setting bit 1.2304.11 to one. This action may also initiate a low-power mode in any other MMDsthat are instantiated in the same package. The low-power mode is exited by resetting the 1000BASE-T1PMA/PMD. The behavior of the 1000BASE-T1 PMA/PMD in transition to and from the low-power mode isimplementation specific and any interface signals should not be relied upon. While in the low-power mode,the device shall, as a minimum, respond to management transactions necessary to exit the low-power mode.The default value of bit 1.2304.11 is zero.

This operation interrupts data communication. The data path of the 1000BASE-T1 PMD, depending on typeand temperature, may take many seconds to run at optimum error ratio after exiting from reset or low-powermode.

Bit 1.2304.11 is a copy of 1.0.11 and setting or clearing either bit shall set or clear the other bit. Settingeither bit shall put the 1000BASE-T1 PMA/PMD in low-power mode.

45.2.1.134 1000BASE-T1 PMA status register (Register 1.2305)

The assignment of bits in the 1000BASE-T1 PMA status register is shown in Table 45–98d.

45.2.1.134.1 1000BASE-T1 OAM ability (1.2305.11)

When read as a one, this bit indicates that the 1000BASE-T1 PHY supports 1000BASE-T1 OAM (see97.3.8). When read as a zero, this bit indicates that the 1000BASE-T1 PHY does not support 1000BASE-T1OAM.

45.2.1.134.2 EEE ability (1.2305.10)

When read as a one, this bit indicates that the 1000BASE-T1 PHY supports EEE. When read as a zero, thisbit indicates that the 1000BASE-T1 PHY does not support EEE.

45.2.1.134.3 Receive fault ability (1.2305.9)

When read as a one, bit 1.2305.9 indicates that the 1000BASE-T1 PMA/PMD has the ability to detect a faultcondition on the receive path. When read as a zero, bit 1.2305.9 indicates that the 1000BASE-T1PMA/PMD does not have the ability to detect a fault condition on the receive path.





45.2.1.134.4 Low-power ability (1.2305.8)

When read as a one, bit 1.2305.8 indicates that the 1000BASE-T1 PMA/PMD supports the low-powerability. When read as a zero, bit 1.2305.8 indicates that the 1000BASE-T1 PMA/PMD does not support thelow-power feature. If the 1000BASE-T1 PMA/PMD supports the low-power feature, then it is controlledusing either bit 1.2304.11 or bit 1.0.11.

45.2.1.134.5 Receive polarity (1.2305.2)

When read as zero, bit 1.2305.2 indicates that the polarity of the receiver is not reversed. When read as one,bit 1.2305.2 indicates that the polarity of receiver is reversed.

45.2.1.134.6 Receive fault (1.2305.1)

When read as a one, bit 1.2305.1 indicates that the 1000BASE-T1 PMA/PMD has detected a fault conditionon the receive path. When read as a zero, bit 1.2305.1 indicates that the 1000BASE-T1 PMA/PMD has notdetected a fault condition on the receive path. Detection of a fault condition on the receive path is optionaland the ability to detect such a condition is advertised by bit 1.2305.9. The 1000BASE-T1 PMA/PMD that isunable to detect a fault condition on the receive path shall return a value of zero for this bit.

Table 45–98d—1000BASE-T1 PMA status register bit definitions



1.2305.11 1000BASE-T1 OAM Ability 1 = PHY has 1000BASE-T1 OAM ability0 = PHY does not have 1000BASE-T1 OAM ability

RO

1.2305.10 EEE Ability 1 = PHY has EEE ability0 = PHY does not have EEE ability

RO

1.2305.9 Receive fault ability 1 = PMA/PMD has the ability to detect a fault condition on the receive path0 = PMA/PMD does not have the ability to detect a fault condition on the receive path

RO

1.2305.8 Low-power ability 1 = PMA/PMD has low-power ability0 = PMA/PMD does not have low-power ability

RO


1.2305.2 Receive polarity 1 = Receive polarity is reversed0 = Receive polarity is not reversed

RO

1.2305.1 Receive fault 1 = Fault condition detected0 = Fault condition not detected

RO

1.2305.0 Receive link status 1 = PMA/PMD receive link up0 = PMA/PMD receive link down

RO/LL

aRO = Read only, LL = Latching Low





45.2.1.134.7 Receive link status (1.2305.0)

When read as a one, bit 1.2305.0 indicates that the 1000BASE-T1 PMA/PMD receive link is up. When readas a zero, bit 1.2305.0 indicates that the 1000BASE-T1 PMA/PMD receive link has been down one or moretimes since the register was last read. The receive link status bit shall be implemented with latching lowbehavior.

45.2.1.135 1000BASE-T1 training register (Register 1.2306)

The assignment of bits in the 1000BASE-T1 training register is shown in Table 45–98e.

45.2.1.135.1 User field (1.2306.10:4)

This register is a user defined 7-bit field that is transmitted to the link partner during training.

45.2.1.135.2 1000BASE-T1 OAM advertisement (1.2306.1)

When set as a one, this bit indicates to the link partner that the 1000BASE-T1 PHY is advertising1000BASE-T1 OAM capability. When set as a zero, this bit indicates to the link partner that the 1000BASE-T1 PHY is not advertising 1000BASE-T1 OAM capability. This bit shall be set to 0 if the 1000BASE-T1PHY does not support 1000BASE-T1 OAM.

45.2.1.135.3 EEE advertisement (1.2306.0)

When set as a one, this bit indicates to the link partner that the 1000BASE-T1 PHY is advertising EEEcapability. When set as a zero, this bit indicates to the link partner that the 1000BASE-T1 PHY is notadvertising EEE capability. This bit shall be set to 0 if the 1000BASE-T1 PHY does not support EEE.

45.2.1.136 1000BASE-T1 link partner training register (Register 1.2307)

The assignment of bits in the 1000BASE-T1 link partner training register is shown in Table 45–98f. Thevalues in this register are not valid until link is up.

Table 45–98e—1000BASE-T1 training register bit definitions




1.2306.10:4 User field 7-bit user defined field to send to the link partner

R/W


1.2306.1 1000BASE-T1 OAM advertisement

1 = 1000BASE-T1 OAM ability advertised to link partner0 = 1000BASE-T1 OAM ability not advertised to link partner

R/W

1.2306.0 EEE advertisement 1 = EEE ability advertised to link partner0 = EEE ability not advertised to link partner

R/W





45.2.1.136.1 Link partner user field (1.2307.10:4)

This register is a user defined 7-bit field that is received from the link partner during training.

45.2.1.136.2 Link partner 1000BASE-T1 OAM advertisement (1.2307.1)

When read as a one, this bit indicates the link partner is advertising 1000BASE-T1 OAM capability. Whenread as a zero, this bit indicates the link partner is not advertising 1000BASE-T1 OAM capability.1000BASE-T1 OAM capability shall be enabled only when both the local device and its link partner areadvertising 1000BASE-T1 OAM capability.

45.2.1.136.3 Link partner EEE advertisement (1.2307.0)

When read as a one, this bit indicates the link partner is advertising EEE capability. When read as a zero, thisbit indicates the link partner is not advertising EEE capability. EEE capability shall be enabled only whenboth the local device and its link partner are advertising EEE capability.

45.2.1.137 1000BASE-T1 test mode control register (Register 1.2308)

The assignment of bits in the 1000BASE-T1 test mode control register is shown in Table 45–98g. Thedefault values for each bit should be chosen so that the initial state of the device upon power up or reset is anormal operational state without management intervention.

45.2.1.137.1 Test mode control (1.2308.15:13)

Transmitter test mode operations defined by bits 1.2307.15:13, are described in 97.5.2 and Table 97–12. Thedefault value for bits 1.2308.15:13 is zero.

Table 45–98f—1000BASE-T1 link partner training register bit definitions



1.2307.10:4 Link partner user field 7-bit user defined field received from the link partner

RO


1.2307.1 Link partner 1000BASE-T1 OAM advertisement

1 = Link partner has 1000BASE-T1 OAM ability0 = Link partner does not have 1000BASE-T1 OAM ability

RO

1.2307.0 Link partner EEE advertisement 1 = Link partner has EEE ability0 = Link partner does not have EEE ability

RO

aRO = Read only





45.2.3 PCS Registers

Change reserved register space (3.1809 through 3.32767) in Table 45–119 as follows:

Insert new subclauses 45.2.3.51 through 45.2.3.57 after 45.2.3.50 as follows:

45.2.3.51 1000BASE-T1 PCS control register (Register 3.2304)

The assignment of bits in the 1000BASE-T1 PCS control register is shown in Table 45–163a. The defaultvalue for each bit of the 1000BASE-T1 PCS control register should be chosen so that the initial state of thedevice upon power up or reset is a normal operational state without management intervention.

Table 45–98g—1000BASE-T1 test mode control register bit definitions


1.2308.15:13 Test mode control 15 14 131 1 1 = Test mode 71 1 0 = Test mode 61 0 1 = Test mode 51 0 0 = Test mode 40 1 1 = Reserved0 1 0 = Test mode 20 0 1 = Test mode 10 0 0 = Normal (non-test) operation

RO


aRO = Read only

Table 45–119—PCS registers


3.1809 through 3.327672303 Reserved

3.2304 1000BASE-T1 PCS control 45.2.3.51

3.2305 1000BASE-T1 PCS status 1 45.2.3.52

3.2306 1000BASE-T1 PCS status 2 45.2.3.53

3.2307 Reserved

3.3208 1000BASE-T1 OAM transmit 45.2.3.54

3.2309 through 3.2312 1000BASE-T1 OAM message 45.2.3.55

3.2313 1000BASE-T1 OAM receive 45.2.3.56

3.2314 through 3.2317 Link partner 1000BASE-T1 OAM message 45.2.3.57






45.2.3.51.1 PCS reset (3.2304.15)

Resetting the 1000BASE-T1 PCS is accomplished by setting bit 3.2304.15 to a one. This action shall set all1000BASE-T1 PCS registers to their default states. As a consequence, this action may change the internalstate of the 1000BASE-T1 PCS and the state of the physical link. This action may also initiate a reset in anyother MMDs that are instantiated in the same package. This bit is self-clearing, and the 1000BASE-T1 PCSshall return a value of one in bit 3.2304.15 when a reset is in progress; otherwise, it shall return a value ofzero. The 1000BASE-T1 PCS is not required to accept a write transaction to any of its registers until thereset process is completed. The control and management interface shall be restored to operation within 0.5 sfrom the setting of bit 3.2304.15. During a reset, a PCS shall respond to reads from register bits 3.0.15,3.8.15:14, and 3.2304.15. All other register bits shall be ignored.


Bit 3.2304.15 is a copy of 3.0.15 and setting or clearing either bit shall set or clear the other bit. Settingeither bit shall reset the 1000BASE-T1 PCS.

45.2.3.51.2 Loopback (3.2304.14)

The 1000BASE-T1 PCS shall be placed in a loopback mode of operation when bit 3.2304.14 is set to a one.When bit 3. 2304.14 is set to a one, the 1000BASE-T1 PCS shall accept data on the transmit path and returnit on the receive path.

The default value of bit 3.2304.14 is zero.

Bit 3.2304.14 is a copy of 3.0.14 and setting or clearing either bit shall set or clear the other bit. Settingeither bit shall enable loopback.

45.2.3.52 1000BASE-T1 PCS status 1 register (Register 3.2305)

The assignment of bits in the 1000BASE-T1 PCS status 1 register is shown in Table 45–163b. All the bits inthe 1000BASE-T1 PCS status 1 register are read only; a write to the 1000BASE-T1 PCS status 1 registershall have no effect.

Table 45–163a—1000BASE-T1 PCS control register bit definitions



3.2304.15 PCS reset 1 = PCS reset0 = Normal operation

R/W, SC

3.2304.14 Loopback 1 = Enable loopback mode0 = Disable loopback mode

R/W






45.2.3.52.1 Tx LPI received (3.2305.11)

When read as a one, bit 3.2305.11 indicates that the transmit 1000BASE-T1 PCS has received LPI signalingone or more times since the register was last read. When read as a zero, bit 3.2305.11 indicates that the1000BASE-T1 PCS has not received LPI signaling. This bit shall be implemented with latching highbehavior.

45.2.3.52.2 Rx LPI received (3.2305.10)

When read as a one, bit 3.2305.10 indicates that the receive 1000BASE-T1 PCS has received LPI signalingone or more times since the register was last read. When read as a zero, bit 3.2305.10 indicates that the1000BASE-T1 PCS has not received LPI signaling. This bit shall be implemented with latching highbehavior.

45.2.3.52.3 Tx LPI indication (3.2305.9)

When read as a one, bit 3.2305.9 indicates that the transmit 1000BASE-T1 PCS is currently receiving LPIsignals. When read as a zero, bit 3.2305.9 indicates that the 1000BASE-T1 PCS is not currently receivingLPI signals. The behavior if read during a state transition is undefined.

45.2.3.52.4 Rx LPI indication (3.2305.8)

When read as a one, bit 3.2305.8 indicates that the receive 1000BASE-T1 PCS is currently receiving LPIsignals. When read as a zero, bit 3.2305.8 indicates that the 1000BASE-T1 PCS is not currently receivingLPI signals. The behavior if read during a state transition is undefined.

Table 45–163b—1000BASE-T1 PCS status 1 register bit definitions



3.2305.11 Tx LPI received 1 = Tx PCS has received LPI0 = LPI not received

RO/LH

3.2305.10 Rx LPI received 1 = Rx PCS has received LPI0 = LPI not received

RO/LH

3.2305.9 Tx LPI indication 1 = Tx PCS is currently receiving LPI0 = PCS is not currently receiving LPI

RO

3.2305.8 Rx LPI indication 1 = Rx PCS is currently receiving LPI0 = PCS is not currently receiving LPI

RO

3.2305.7 Fault 1 = Fault condition detected0 = No fault condition detected

RO


3.2305.2 PCS receive link status 1 = PCS receive link up0 = PCS receive link down

RO/LL


aRO = Read only, LH = Latching high, LL = Latching low





45.2.3.52.5 Fault (3.2305.7)

When read as a one, bit 3.2305.7 indicates that the 1000BASE-T1 PCS has detected a fault condition oneither the transmit or receive paths. When read as a zero, bit 3.2305.7 indicates that the 1000BASE-T1 PCShas not detected a fault condition.

45.2.3.52.6 PCS receive link status (3.2305.2)

When read as a one, bit 3.2305.2 indicates that the 1000BASE-T1 PCS receive link is up. When read as azero, bit 3.2305.2 indicates that the 1000BASE-T1 PCS receive link was down since the last read from thisregister. This bit is a latching low version of bit 3.2306.10. The PCS receive link status bit shall beimplemented with latching low behavior.

45.2.3.53 1000BASE-T1 PCS status 2 register (Register 3.2306)

The assignment of bits in the 1000BASE-T1 PCS status 2 register is shown in Table 45–163c. All the bits inthe 1000BASE-T1 PCS status 2 register are read only; a write to the 1000BASE-T1 PCS status 2 registershall have no effect.

45.2.3.53.1 Receive link status (3.2306.10)

When read as a one, bit 3.2306.10 indicates that the 1000BASE-T1 PCS is in a fully operational state. Whenread as a zero, bit 3.2306.10 indicates that the 1000BASE-T1 PCS is not fully operational. This bit is areflection of the PCS_status variable defined in 97.3.7.1.

45.2.3.53.2 PCS high BER (3.2306.9)

When read as a one, bit 3.2306.9 indicates that the 1000BASE-T1 PCS receiver is detecting a BER of> 4 × 10–4. When read as a zero, bit 3.2306.9 indicates that the 1000BASE-T1 PCS is not detecting a BER of> 4 × 10–4. This bit is a reflection of the state of the hi_rfer variable defined in 97.3.7.1.

Table 45–163c—1000BASE-T1 PCS status 2 register bit definitions


aRO = Read only, LH = Latching High, LL = Latching Low, NR = Non Roll-over


3.2306.10 Receive link status 1 = PCS receive link up0 = PCS receive link down

RO

3.2306.9 PCS high BER 1 = PCS reporting a high BER0 = PCS not reporting a high BER

RO

3.2306.8 PCS block lock 1 = PCS locked to received blocks0 = PCS not locked to received blocks

RO

3.2306.7 Latched high BER 1 = PCS has reported a high BER0 = PCS has not reported a high BER

RO/LH

3.2306.6 Latched block lock 1 = PCS has block lock0 = PCS does not have block lock

RO/LL

3.2306.5:0 BER count BER counter RO/NR





45.2.3.53.3 PCS block lock (3.2306.8)

When read as a one, bit 3.2306.8 indicates that the 1000BASE-T1 PCS receiver has block lock. When readas a zero, bit 3.2306.8 indicates that the 1000BASE-T1 PCS receiver has not achieved block lock. This bit isa reflection of the state of the block_lock variable defined in 97.3.7.1.

45.2.3.53.4 Latched high BER (3.2306.7)

When read as a one, bit 3.2306.7 indicates that the 1000BASE-T1 PCS has detected a high BER one or moretimes since the register was last read. When read as a zero, bit 3.2306.7 indicates that the 1000BASE-T1PCS has not detected a high BER. The latched high BER bit shall be implemented with latching highbehavior. This bit is a latching high version of the 1000BASE-T1 PCS high BER status bit (3.2306.9).

45.2.3.53.5 Latched block lock (3.2306.6)

When read as a one, bit 3.2306.6 indicates that the 1000BASE-T1 PCS has achieved block lock. When readas a zero, bit 3.2306.6 indicates that the 1000BASE-T1 PCS has lost block lock one or more times since theregister was last read. The latched block lock bit shall be implemented with latching low behavior.

This bit is a latching low version of the 1000BASE-T1 PCS block lock status bit (3.2306.8).

45.2.3.53.6 BER count (3.2306.5:0)

The BER counter formed by bits 3.2306.5:0 is a six bit count as defined by RFER_count in 97.3.7.2. Thesebits shall be reset to all zeros when the 1000BASE-T1 PCS status 2 register is read by the managementfunction or upon execution of the 1000BASE-T1 PCS reset. These bits shall be held at all ones in the case ofoverflow.

45.2.3.54 1000BASE-T1 OAM transmit register (Register 3.2308)

The assignment of bits in the 1000BASE-T1 OAM transmit register is shown in Table 45–163d.

Table 45–163d—1000BASE-T1 OAM transmit register bit definitions


3.2308.15 1000BASE-T1 OAM message valid

This bit is used to indicate message data in registers 3.2308.11:8, 3.2309, 3.2310, 3.2311, and 3.2312 are valid and ready to be loaded.This bit shall self-clear when registers are loaded by the state machine. 1 = Message data in registers are valid0 = Message data in registers are not valid

R/W, SC

3.2308.14 Toggle value Toggle value to be transmitted with message. This bit is set by the state machine and cannot be overridden by the user.

RO

3.2308.13 1000BASE-T1 OAM message received

This bit shall self clear on read.1 = 1000BASE-T1 OAM message received by link partner0 = 1000BASE-T1 OAM message not received by link partner

RO, LH

3.2308.12 Received message toggle value Toggle value of message that was received by link partner as indicated in 3.2308.13.

RO





45.2.3.54.1 1000BASE-T1 OAM message valid (3.2308.15)

Bit 3.2308.15 shall be set to 1 when the 1000BASE-T1 OAM message to be transmitted in registers 3.2309,3.2310, 3.2311, and 3.2312 and the message number in 3.2308.11:8 are properly configured to betransmitted. This register shall be cleared by the state machine to indicate whether the next 1000BASE-T1OAM message can be written into the registers.

45.2.3.54.2 Toggle value (3.2308.14)

The state machine shall assign a value alternating between 0 and 1 to associate with the 8 octet 1000BASE-T1 OAM message transmit by the 1000BASE-T1 PHY. Bit 3.2308.14 should be read and recorded prior tosetting 3.2308.15 to 1. The recorded value can be correlated with 3.2308.12 as a confirmation that the1000BASE-T1 OAM message is received by the link partner.

45.2.3.54.3 1000BASE-T1 OAM message received (3.2308.13)

Bit 3.2308.13 shall indicate whether the most recently transmitted 1000BASE-T1 OAM message with atoggle bit value in 3.2308.12 was received, read, and acknowledged by the link partner. This variable shallclear on read.

45.2.3.54.4 Received message toggle value (3.2308.12)

Bit 3.2308.12 indicates the toggle bit value of the 1000BASE-T1 OAM message that was received, read, andmost recently acknowledged by the link partner. This bit is valid only if 3.2308.13 is 1.

45.2.3.54.5 Message number (3.2308.11:8)

The 1000BASE-T1 OAM message number to be transmitted. This field is user defined but is recommendedthat it be used to indicate the meaning of the 8 octet 1000BASE-T1 OAM message. If used this way, up to16 different 8-octet messages can be exchanged. The message number is user defined and its definition isoutside the scope of this standard.

3.2308.11:8 Message number User-defined message number to send R/W


3.2308.3 Ping received Received PingTx value from latest good 1000BASE-T1 OAM frame received

RO

3.2308.2 Ping transmit Ping value to send to link partner R/W

3.2308.1:0 Local SNR 00 = PHY link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame.01 = LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPI and send idles (used only when EEE is enabled).10 = PHY SNR is marginal.11 = PHY SNR is good.

RO

aRO = Read only, R/W = Read/Write, LH = Latching High, SC = Self-clearing

Table 45–163d—1000BASE-T1 OAM transmit register bit definitions (continued)






45.2.3.54.6 Ping received (3.2308.3)

Bit 3.2308.3 represents the value of the most recent Ping RX received from the link partner (see 97.3.8.2.3).

45.2.3.54.7 Ping transmit (3.2308.2)

Bit 3.2308.2 represents the value to be sent to the link partner via the Ping TX function (see 97.3.8.2.4).

45.2.3.54.8 Local SNR (3.2308.1:0)

Bits 3.2308.1:0 are set by the 1000BASE-T1 PHY to indicate the status of the receiver. The definitions ofgood, marginal, when to request idles, and when to request retrain are implementation dependent.

45.2.3.55 1000BASE-T1 OAM message register (Registers 3.2309 to 3.2312)

The 8-octet 1000BASE-T1 OAM message data to be transmitted. The 8-octet message data is user definedand its definition is outside the scope of this standard. See Table 45–163e.

45.2.3.56 1000BASE-T1 OAM receive register (Register 3.2313)

The assignment of bits in the 1000BASE-T1 OAM receive register is shown in Table 45–163f.

45.2.3.56.1 Link partner 1000BASE-T1 OAM message valid (3.2313.15)

Bit 3.2313.15 shall be set to 1 when the 1000BASE-T1 OAM message from the link partner is stored intoregisters 3.2314, 3.2315, 3.2316, and 3.2317 and the message number in 3.2313.11:8. This register shall becleared when register 3.2317 is read.

45.2.3.56.2 Link partner toggle value (3.2313.14)

Bit 3.2313.14 indicates the toggle value associate with the 8 octet 1000BASE-T1 OAM message from thelink partner.

Table 45–163e—1000BASE-T1 OAM message register bit definitions


aR/W = Read/Write

3.2309.15:8 1000BASE-T1 OAM message 1 Message octet 1. LSB transmitted first. R/W












45.2.3.56.3 Link partner message number (3.2313.11:8)

The 1000BASE-T1 OAM message number from the link partner.

45.2.3.56.4 Link partner SNR (3.2313.1:0)

Bits 3.2313.1:0 indicate the status of the link partner receiver. The definitions of good, marginal, when torequest idles, and when to request retrain are implementation dependent.

45.2.3.57 Link partner 1000BASE-T1 OAM message register (Registers 3.2314 to 3.2317)

The 8 octet 1000BASE-T1 OAM message data from the link partner. Register 3.2313.15 shall be clearedwhen register 3.2317 is read. See Table 45–163g.

Table 45–163f—1000BASE-T1 OAM receive register bit definitions


3.2313.15 Link partner 1000BASE-T1 OAM message valid

This bit is used to indicate message data in registers 3.2313.11:8, 3.2314, 3.2315, 3.2316, and 3.2317 are stored and ready to be read.This bit shall self clear when register 3.2317 is read.1 = Message data in registers are valid0 = Message data in registers are not valid

RO, SC

3.2313.14 Link partner toggle value Toggle value received with message. RO


3.2313.11:8 Link partner message number Message number from link partner RO


3.2313.1:0 Link partner SNR 00 = Link partner link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame.01 = LPI refresh is insufficient to maintain link partner SNR. Link partner requests local device to exit LPI and send idles (used only when EEE is enabled).10 = Link partner SNR is marginal.11 = Link partner SNR is good.

RO

aRO = Read only, SC = Self-clearing





45.2.7 Auto-Negotiation registers

Change reserved register space (7.62 through 7.32767) in Table 45-200 as follows:

Table 45–163g—Link partner 1000BASE-T1 OAM message register bit definitions


3.2314.15:8 Link partner 1000BASE-T1 OAM message 1

Message octet 1. LSB transmitted first. RO















aRO = Read only

Table 45–200—Auto-Negotiation MMD registers


7.62 through 7.32 767511 Reserved

7.512 BASE-T1 AN control 45.2.7.14c

7.513 BASE-T1 AN status 45.2.7.14d

7.514 through 7.516 BASE-T1 AN advertisement 45.2.7.14e

7.517 through 7.519 BASE-T1 AN LP Base Page ability 45.2.7.14f

7.520 through 7.522 BASE-T1 AN Next Page transmit 45.2.7.14g

7.523 through 7.525 BASE-T1 AN LP Next Page ability 45.2.7.14h






Insert subclauses 45.2.7.14c through 45.2.7.14h (after 45.2.7.14b inserted by IEEE Std 802.3bq-2016) asfollows:

45.2.7.14c BASE-T1 AN control register (Register 7.512)

The assignment of bits in the BASE-T1 AN control register is shown in Table 45–211c. The default valuefor each bit of the BASE-T1 AN control register has been chosen so that the initial state of the device uponpower up or completion of reset is a normal operational state without management intervention.

45.2.7.14c.1 AN reset (7.512.15)

Resetting AN is accomplished by setting bit 7.512.15 to a one. This action shall set all BASE-T1 ANregisters to their default states. As a consequence, this action may change the internal state of AN and thestate of the physical link. This action may also initiate a reset in any other MMDs that are instantiated in thesame package. This bit is self-clearing, and AN shall return a value of one in bit 7.512.15 when a reset is inprogress and a value of zero otherwise. AN is not required to accept a write transaction to any of its registersuntil the reset process is complete. The reset process shall be completed within 0.5 s from the setting of bit7.512.15. During an AN reset, AN shall respond to reads from register bit 7.512.15. All other register bitsshall be ignored.

The default value for bit 7.512.15 is zero.


45.2.7.14c.2 Auto-Negotiation enable (7.512.12)

The Auto-Negotiation function shall be enabled by setting bit 7.512.12 to a one. If bit 7.512.12 is set to one,then type selection bits 1.2100.3:0 and MASTER-SLAVE bits 1.2100.14 shall have no effect on the linkconfiguration, and the Auto-Negotiation process determines the link configuration. If bit 7.512.12 is clearedto zero, then bits 1.2100.3:0 and bit 1.2100.14 determine the link configuration regardless of the prior stateof the link configuration and the Auto-Negotiation process.

If the BASE-T1 PHY reports via bit 7.513.3 that it lacks the ability to perform Auto-Negotiation, then thevalue of bit 7.512.12 shall be zero.

Table 45–211c—BASE-T1 AN control register bit definitions



7.512.15 AN reset 1 = AN reset0 = AN normal operation

R/W, SC


7.512.12 Auto-Negotiation enable 1 = enable Auto-Negotiation process0 = disable Auto-Negotiation process

R/W


7.512.9 Restart Auto-Negotiation 1 = Restart Auto-Negotiation process0 = Auto-Negotiation in process, disabled, or not supported

R/W, SC






45.2.7.14c.3 Restart Auto-Negotiation (7.512.9)

If the BASE-T1 PMA/PMD reports (via bit 7.513.3) that it lacks the ability to perform Auto-Negotiation, orif Auto-Negotiation is disabled, the BASE-T1 PMA/PMD shall return a value of zero in bit 7.512.9 and anyattempt to write a one to bit 7.512.9 shall be ignored.

Otherwise, the Auto-Negotiation process shall be restarted by setting bit 7.512.9 to one. This bit is self-clearing, and the BASE-T1 PMA/PMD shall return a value of one in bit 7.512.9 until the Auto-Negotiationprocess has been initiated. If Auto-Negotiation was completed prior to this bit being set, the process shall bereinitialized. The Auto-Negotiation process shall not be affected by clearing this bit to zero.

The default value for 7.512.9 is zero.

45.2.7.14d BASE-T1 AN status (Register 7.513)

The assignment of bits in the BASE-T1 AN status register is shown in Table 45–211d. All the bits in theBASE-T1 AN status register are read only; therefore, a write to the BASE-T1 AN status register shall haveno effect.

45.2.7.14d.1 Page received (7.513.6)

The Page received bit (7.513.6) shall be set to one to indicate that a new link codeword has been receivedand stored in the BASE-T1 AN LP Base Page ability registers 7.517 to 7.519 or the BASE-T1 AN LP NextPage ability registers 7.523 to 7.525. The contents of the BASE-T1 AN LP Base Page ability registers 7.517to 7.519 are valid when bit 7.513.6 is set the first time during the Auto-Negotiation. The Page received bitshall be reset to zero on a read of the BASE-T1 AN status register (Register 7.513).

Table 45–211d—BASE-T1 AN status register bit definitions


aRO = Read only, LH = Latching High, LL = Latching Low


7.513.6 Page received 1 = A page has been received0 = A page has not been received

RO, LH

7.513.5 Auto-Negotiation complete 1 = Auto-Negotiation process completed0 = Auto-Negotiation process not completed

RO

7.513.4 Remote fault 1 = remote fault condition detected0 = no remote fault condition detected

RO, LH

7.513.3 Auto-Negotiation ability 1 = PHY is able to perform Auto-Negotiation0 = PHY is not able to perform Auto-Negotiation

RO

7.513.2 Link status 1 = Link is up0 = Link is down

RO, LL






45.2.7.14d.2 Auto-Negotiation complete (7.513.5)

When read as a one, bit 7.513.5 indicates that the Auto-Negotiation process has been completed, and that thecontents of the Auto-Negotiation registers 7.514 to 7.516 and 7.517 to 7.519 are valid. When read as a zero,bit 7.513.5 indicates that the Auto-Negotiation process has not been completed, and that the contents of7.517 through 7.525 registers are as defined by the current state of the Auto-Negotiation protocol, or aswritten for manual configuration. The BASE-T1 PMA/PMD shall return a value of zero in bit 7.513.5 ifAuto-Negotiation is disabled by clearing bit 7.512.12. The BASE-T1 PMA/PMD shall also return a value ofzero in bit 7.513.5 if it lacks the ability to perform Auto-Negotiation.

45.2.7.14d.3 Remote fault (7.513.4)

When read as one, bit 7.513.4 indicates that a remote fault condition has been detected. The type of fault aswell as the criteria and method of fault detection is AN specific. The remote fault bit shall be implementedwith a latching function, such that the occurrence of a remote fault causes the bit 7.513.4 to become set andremain set until it is cleared. Bit 7.513.4 shall be cleared each time register 7.513 is read via the managementinterface, and shall also be cleared by a AN reset.

45.2.7.14d.4 Auto-Negotiation ability (7.513.3)

When read as a one, bit 7.513.3 indicates that the BASE-T1 PMA/PMD has the ability to perform BASE-T1Auto-Negotiation. When read as a zero, bit 7.513.3 indicates that the BASE-T1 PMA/PMD lacks the abilityto perform BASE-T1 Auto-Negotiation.

45.2.7.14d.5 Link status (7.513.2)

When read as a one, bit 7.513.2 indicates that the BASE-T1 PMA/PMD has determined that a valid link hasbeen established. When read as a zero, bit 7.513.2 indicates that the link has been invalid after this bit waslast read. Bit 7.513.2 is set to one when the variable link_status equals OK and is cleared to zero when thevariable link_status equals FAIL. The link status bit shall be implemented with a latching function, such thatthe occurrence of a link_status equals FAIL condition causes the link status bit to become cleared andremain cleared until it is read via the management interface. Bit 7.513.2 shall be cleared upon AN reset. Thisstatus indication is intended to support the management attribute defined in 30.5.1.1.4, aMediaAvailable.

45.2.7.14e BASE-T1 AN advertisement register (Registers 7.514, 7.515, and 7.516)

The assignment of bits in the BASE-T1 AN advertisement register is shown in Table 45–211e.

The Selector field (7.514.4:0) shall be set to the IEEE 802.3 code as specified in Annex 98A. TheAcknowledge bit (7.514.14) is set to zero.

The technology ability field, as defined in 98.2.1.2, represents the technologies supported by the localdevice. Only bits representing supported technologies may be set. Management may clear bits in thetechnology ability field and restart Auto-Negotiation to negotiate an alternate common mode.

The management entity initiates renegotiation with the link partner using alternate abilities by setting theRestart Auto-Negotiation bit (7.512.9) in the AN control register to one.

Any writes to this register prior to completion of Auto-Negotiation, as indicated by bit 7.513.5, should befollowed by a renegotiation for the new values to take effect. Once Auto-Negotiation has completed,software may examine this register along with the LP Base Page ability register to determine the highestcommon denominator technology.





The Base Page value is transferred to mr_adv_ability when register 7.514 is written. Therefore, registers7.515 and 7.516 should be written before 7.514.

45.2.7.14f BASE-T1 AN LP Base Page ability register (Registers 7.517, 7.518, and 7.519)

The assignment of bits in the BASE-T1 AN LP Base Page ability register is shown in Table 45–211f.

All of the bits in the BASE-T1 AN LP Base Page ability register are read only. A write to the BASE-T1 ANLP Base Page ability register shall have no effect.

The value of the registers 7.518 and 7.519 is latched when register 7.517 is read and reads of registers 7.518and 7.519 return the latched value rather than the current value.

45.2.7.14g BASE-T1 AN Next Page transmit register (Registers 7.520, 7.521, and 7.522)

The assignment of bits in the BASE-T1 AN Next Page transmit register is shown in Table 45–211g.

The register contains the BASE-T1 AN Next Page link codeword as defined in 98.2.4.3.

On power-up or AN reset, this register shall contain the default value, which represents a Message Page withthe message code set to Null Message. This value may be replaced by any valid Next Page Message Code

Table 45–211e—BASE-T1 AN advertisement register bit definitions



7.514.15 Next Page See 98.2.1.2.9 R/W

7.514.14 Acknowledge Value always 0 RO

7.514.13 Remote fault See 98.2.1.2.7 R/W

7.514.12:5 D12:D5 See 98.2.1.2 R/W

7.514.4:0 Selector field See Annex 98A R/W

7.515.15:0 D31:D16 See 98.2.1.2 R/W

7.516.15:0 D47:D32 See 98.2.1.2 R/W

Table 45–211f—BASE-T1 AN LP Base Page ability register bit definitions


aRO = Read only

7.517.15:0 D15:D0 See 98.2.1.2 RO

7.518.15:0 D31:D16 See 98.2.1.2 RO

7.519.15:0 D47:D32 See 98.2.1.2 RO





that the device intends to transmit. The BASE-T1 AN shall use Next Page Message Codes as defined inAnnex 98C.

A write to register 7.521 or 7.522 does not set mr_next_page_loaded. Only a write to register 7.520 setsmr_next_page_loaded true as described in 98.5.1. Therefore registers 7.521 and 7.522 should be writtenbefore register 7.520.

45.2.7.14h BASE-T1 AN LP Next Page ability register (Registers 7.523, 7.524, and 7.525)

BASE-T1 AN LP Next Page ability register (registers 7.523, 7.524, and 7.525) store BASE-T1 link partnerNext Pages as shown in Table 45–211h. All of the bits in the BASE-T1 AN LP Next Page ability register areread only. A write to the BASE-T1 AN LP Next Page ability register shall have no effect.

Table 45–211g—BASE-T1 AN Next Page transmit register bit definitions



7.520.15 Next page See 98.2.4.3 R/W

7.520.14 Reserved Value always 0 RO

7.520.13 Message page See 98.2.4.3 R/W

7.520.12 Acknowledge 2 See 98.2.4.3 R/W

7.520.11 Toggle See 98.2.4.3 RO

7.520.10:0 Message/Unformatted code field See 98.2.4.3 R/W

7.521.15:0 Unformatted code field 1 See 98.2.4.3 R/W

7.522.15:0 Unformatted code field 2 See 98.2.4.3 R/W

Table 45–211h—BASE-T1 AN LP Next Page ability register bit definitions


aRO = Read only

7.523.15 Next Page See 98.2.4.3 RO

7.523.14 Acknowledge See 98.2.4.3 RO

7.523.13 Message page See 98.2.4.3 RO

7.523.12 Acknowledge 2 See 98.2.4.3 RO

7.523.11 Toggle See 98.2.4.3 RO

7.523.10:0 Message/Unformatted code field See 98.2.4.3 RO

7.524.15:0 Unformatted code field 1 See 98.2.4.3 RO

7.525.15:0 Unformatted code field 2 See 98.2.4.3 RO





The value of registers 7.524 and 7.525 is latched when register 7.523 is read and reads of registers 7.524 and7.525 return the latched value rather than the current value.

NOTE—If this register is used to store multiple link partner Next Pages, the previous value of this register is assumed tobe stored by a management entity that needs the information overwritten by subsequent link partner Next Pages.





45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, Management Data Input/Output (MDIO) interface2

45.5.3 PICS proforma tables for the Management Data Input Output (MDIO) interface

45.5.3.3 PMA/PMD management functions

Insert PICS items MM130 through MM149 at the bottom of the table in 45.5.3.3 (as modified byIEEE Std 802.3bw-2015 and IEEE Std 802.3by-2016) as follows:

2Copyright release for PICS proformas: Users of this standard may freely reproduce the PICS proforma in this subclause so that it can be used for its intended purpose and may further publish the completed PICS.

Item Feature Subclause Value/Comment Status Support

MM130 A reset sets all 1000BASE-T1 PMA/PMD registers to their default states

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM131 1000BASE-T1 PMA/PMD returns a one in bit 1.2304.15 when a reset is in progress

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM132 1000BASE-T1 PMA/PMD returns a zero in bit 1.2304.15 when a reset is complete

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM133 The control and management interface is restored to operation within 0.5 s from the setting of bit 1.2304.15

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM134 During a reset, the 1000BASE-T1 PMD/PMA responds to reads from register bits 1.2304.15, 1.8.15:14, and 1.0.15.

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM135 During a reset, the 1000BASE-T1 PMD/PMA register bits are ignored.

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM136 Setting either 1.2304.15 or 1.0.15 resets the 1000BASE-T1 PMA/PMD.

45.2.1.133.1 PMA:M Yes [ ]N/A [ ]

MM137 When bit 1.2304.14 is set to a one, the PMA disables output on the transmit path.

45.2.1.133.2 PMA:M Yes [ ]N/A [ ]

MM138 When bit 1.2304.14 is set to a zero, the PMA enables output on the transmit path.

45.2.1.133.2 PMA:M Yes [ ]N/A [ ]

MM139 Setting either bit 1.2304.14 or 1.9.0 disables the 1000BASE-T1 PMA transmit path.

45.2.1.133.2 PMA:M Yes [ ]N/A [ ]






MM140 While in the low-power mode, the device, as a minimum, responds to management transactions necessary to exit the low-power mode.

45.2.1.133.3 PMA:M Yes [ ]N/A [ ]

MM141 Setting either 1.2304.11 or 1.0.11 puts the 1000BASE-T1 PMA/PMD in low-power mode.

45.2.1.133.3 PMA:M Yes [ ]N/A [ ]

MM142 The 1000BASE-T1 PMA/PMD that is unable to detect a fault condition on the receive path returns a value of zero for bit 1.2305.1.

45.2.1.134.6 PMA:M Yes [ ]N/A [ ]

MM143 Bit 1.2305.0 is implemented with latching low behavior.

45.2.1.134.6 PMA:M Yes [ ]N/A [ ]

MM144 Bit 1.2306.1 is set to 0 if the 1000BASE-T1 PHY does not support OAM.

45.2.1.135.2 PMA:M Yes [ ]N/A [ ]

MM145 Bit 1.2306.0 is set to 0 if the 1000BASE-T1 PHY does not support EEE.

45.2.1.135.3 PMA:M Yes [ ]N/A [ ]

MM146 OAM capability is enabled only when both the 1000BASE-T1 PHY and link partner are advertising OAM capability.

45.2.1.136.2 PMA:M Yes [ ]N/A [ ]

MM147 EEE capability is enabled only when both the 1000BASE-T1 PHY and link partner are advertising EEE capability

45.2.1.136.3 PMA:M Yes [ ]N/A [ ]

MM148 Bit 1.2100.14 is ignored when the Auto-Negotiation enable bit 7.512.12 is set to one.

45.2.1.131.1 PMA:M Yes [ ]N/A [ ]

MM149 Bits 1.2100.3:0 is ignored when the Auto-Negotiation enable bit 7.512.12 is set to one.

45.2.1.131.2 PMA:M Yes [ ]N/A [ ]





45.5.3.7 PCS management functions

Insert PICS items RM107 through RM136, as follows, at the bottom of the table:


RM107 This action sets all 1000BASE-T1 PCS registers to their default states.

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM108 Bit 3.2304.15 is self-clearing, and the 1000BASE-T1 PCS returns a value of one in bit 3.2304.15 when a reset is in progress.

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM109 Otherwise, bit 3.2304.15 returns a value of zero

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM110 The control and management interface is restored to operation within 0.5 s from the setting of bit 3.2304.15.

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM111 During a reset, the 1000BASE-T1 PCS responds to reads from register bits 3.0.15, 3.8.15:14, and 3.2304.15.

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM112 All other register bits are ignored during a reset.

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM113 Setting either bit 3.2304.15 or 3.0.15 resets the 1000BASE-T1 PCS.

45.2.3.51.1 PCS:M Yes [ ]N/A [ ]

RM114 The 1000BASE-T1 PCS is placed in a loopback mode of operation when bit 3.2304.14 is set to a one.

45.2.3.51.2 PCS:M Yes [ ]N/A [ ]

RM115 When bit 3. 2304.14 is set to a one, the 1000BASE-T1 PCS accepts data on the transmit path and returnit on the receive path.

45.2.3.51.2 PCS:M Yes [ ]N/A [ ]

RM116 Setting either bit 3.2304.14 or 3.0.14 enables loopback.

45.2.3.51.2 PCS:M Yes [ ]N/A [ ]

RM117 All the bits in the 1000BASE-T1 PCS status 1 register are read only; a write to the 1000BASE-T1 PCS status 1 register has no effect.

45.2.3.52 PCS:M Yes [ ]N/A [ ]

RM118 Bit 3.2305.11 is implemented with latching high behavior.

45.2.3.52.1 PCS:M Yes [ ]N/A [ ]


45.2.3.52.2 PCS:M Yes [ ]N/A [ ]

RM120 All the bits in the 1000BASE-T1 PCS status 2 register are read only; a write to the 1000BASE-T1 PCS status 2 register has no effect.

45.2.3.53 PCS:M Yes [ ]N/A [ ]


45.2.3.53.4 PCS:M Yes [ ]N/A [ ]

RM122 Bit 3.2306.6 is implemented with latching low behavior.

45.2.3.53.5 PCS:M Yes [ ]N/A [ ]





RM123 Bits 3.2306.5:0 are reset to all zeros when the 1000BASE-T1 PCS status 2 register is read by the management function or upon execution of the 1000BASE-T1 PCS reset.

45.2.3.53.6 PCS:M Yes [ ]N/A [ ]

RM124 Bits 3.2306.5:0 are held at all ones in the case of overflow.

45.2.3.53.6 PCS:M Yes [ ]N/A [ ]

RM125 Bit 3.2308.15 is set to 1 when the OAM message to be transmitted in registers 3.2309, 3.2310, 3.2311, and 3.2312 and the message number in 3.2308.11:8 are properly configured to be transmitted.

45.2.3.54.1 PCS:M Yes [ ]N/A [ ]

RM126 Register 3.2308 is cleared by the state machine to indicate whether the next OAM message can be written into the registers.

45.2.3.54.1 PCS:M Yes [ ]N/A [ ]

RM127 The state machine assigns a value alternating between 0 and 1 to associate with the 8 octet OAM message transmit by the 1000BASE-T1 PHY.

45.2.3.54.2 PCS:M Yes [ ]N/A [ ]

RM128 Bit 3.2308.14 is read and recorded prior to setting 3.2308.15 to 1.

45.2.3.54.2 PCS:O Yes [ ]No [ ]

RM129 Bit 3.2308.15 self clears when registers are loaded by the state machine.

45.2.3.54 PCS:M Yes [ ]N/A [ ]

RM130 Bit 3.2308.14 self clears on read. 45.2.3.54 PCS:M Yes [ ]N/A [ ]

RM131 Bit 3.2308.13 indicates whether the most recently transmitted OAM message with a toggle bit value in3.2308.12 was received, read, and acknowledged by the link partner.

45.2.3.54.3 PCS:M Yes [ ]N/A [ ]

RM132 Bit 3.2308.13 clears on read. 45.2.3.54.3 PCS:M Yes [ ]N/A [ ]

RM133 Bit 3.2313.15 is set to 1 when the OAM message from the link partner is stored into registers 3.2314, 3.2315, 3.2316, and 3.2317 and the message number in 3.2313.11:8.

45.2.3.56.1 PCS:M Yes [ ]N/A [ ]

RM134 Register 3.2313 is cleared when register 3.2317 is read.

45.2.3.56.1 PCS:M Yes [ ]N/A [ ]

RM135 Bit 3.2313.15 self clears when register 3.2317 is read.

45.2.3.56 PCS:M Yes [ ]N/A [ ]

RM136 Register 3.2313.15 is cleared when register 3.2317 is read.

45.2.3.57 PCS:M Yes [ ]N/A [ ]






45.5.3.9 Auto-Negotiation management functions

Insert PICS items AM65 through AM89 at the bottom of the table in 45.5.3.9 (as modified byIEEE Std 802.3bq-2016) as follows:


AM65 Setting bit 7.512.15 to a one sets all BASE-T1 AN registers to their default states.

45.2.7.14c.1 AN:M Yes [ ]N/A [ ]

AM66 Bit 7.512.15 is self-clearing, and AN shall return a value of one in bit 7.512.15 when a reset is in progress and a value of zero otherwise.

45.2.7.14c.1 AN:M Yes [ ]N/A [ ]

AM67 The reset process is completed within 0.5 s from the setting of bit7.512.15.

45.2.7.14c.1 AN:M Yes [ ]N/A [ ]

AM68 During an AN reset, AN responds to reads from register bit 7.512.15.

45.2.7.14c.1 AN:M Yes [ ]N/A [ ]

AM69 All other register bits are ignored. 45.2.7.14c.1 AN:M Yes [ ]N/A [ ]

AM70 The Auto-Negotiation function is enabled by setting bit 7.512.12 to a one.

45.2.7.14c.2 AN:M Yes [ ]N/A [ ]

AM71 If bit 7.512.12 is set to one, then PHY type bits 1.2100.3:0 and MASTER-SLAVE bits 1.2100.14 has no effect on the link configuration, and the Auto-Negotiation process determines the link configuration.

45.2.7.14c.2 AN:M Yes [ ]N/A [ ]

AM72 If the BASE-T1 PHY reports via bit 7.513.3 that it lacks the ability to perform Auto-Negotiation, then the value of bit 7.512.12 is zero.

45.2.7.14c.2 AN:M Yes [ ]N/A [ ]

AM73 If the BASE-T1 PMA/PMD reports (via bit 7.513.3) that it lacks the ability to perform Auto-Negotiation, or if Auto-Negotiation is disabled, the BASE-T1 PMA/PMD returns a value of zero in bit 7.512.9 and any attempt to write a one to bit 7.512.9 are ignored.

45.2.7.14c.3 AN:M Yes [ ]N/A [ ]

AM74 Otherwise, the Auto-Negotiation process is restarted by setting bit 7.512.9 to one.

45.2.7.14c.3 AN:M Yes [ ]N/A [ ]

AM75 Bit 7.512.9 is self-clearing, and the BASE-T1 PMA/PMD shall return a value of one in bit 7.512.9 until the Auto-Negotiation process has been initiated.

45.2.7.14c.3 AN:M Yes [ ]N/A [ ]

AM76 If Auto-Negotiation was completed prior to this bit being set, the process is reinitialized.

45.2.7.14c.3 AN:M Yes [ ]N/A [ ]





AM77 The Auto-Negotiation process is affected by clearing this bit to zero.

45.2.7.14c.3 AN:M Yes [ ]N/A [ ]

AM78 All the bits in the BASE-T1 AN status register are read only; therefore, a write to the BASE-T1 AN status register has no effect.

45.2.7.14d AN:M Yes [ ]N/A [ ]

AM79 The Page received bit (7.513.6) is set to one to indicate that a new link codeword has been received and stored in the BASE-T1 AN LP Base Page ability registers 7.517 to 7.519 or the BASE-T1 AN LP Next Page ability registers 7.523 to 7.525.

45.2.7.14d.1 AN:M Yes [ ]N/A [ ]

AM80 The Page received bit is reset to zero on a read of the BASE-T1 AN status register (Register 7.513).

45.2.7.14d.1 AN:M Yes [ ]N/A [ ]

AM81 The BASE-T1 PMA/PMD returns a value of zero in bit 7.513.5 if Auto-Negotiation is disabled by clearing bit 7.512.12.

45.2.7.14d.2 AN:M Yes [ ]N/A [ ]

AM82 The BASE-T1 PMA/PMD also returns a value of zero in bit 7.513.5 if it lacks the ability to perform Auto-Negotiation.

45.2.7.14d.2 AN:M Yes [ ]N/A [ ]

AM83 The remote fault bit is implemented with a latching function, such that the occurrence of a remote fault causes the bit 7.513.4 to become set and remain set until it is cleared.

45.2.7.14d.3 AN:M Yes [ ]N/A [ ]

AM84 Bit 7.513.4 is cleared each time register 7.513 is read via the management interface, and is also cleared by a AN reset.

45.2.7.14d.3 AN:M Yes [ ]N/A [ ]

AM85 The link status bit is implemented with a latching function, such that the occurrence of a link_status equals FAIL condition causes the link status bit to become cleared and remain cleared until it is read via the management interface.

45.2.7.14d.5 AN:M Yes [ ]N/A [ ]

AM86 Bit 7.513.2 is cleared upon AN reset. 45.2.7.14d.5 AN:M Yes [ ]N/A [ ]

AM87 A write to the BASE-T1 AN LP Base Page ability register has no effect.

45.2.7.14f AN:M Yes [ ]N/A [ ]

AM88 On power-up or AN reset, registers 7.520, 7.521, and 7.522 contain the default value, which represents a Message Page with the message code set to Null Message.

45.2.7.14g AN:M Yes [ ]N/A [ ]

AM89 A write to the BASE-T1 AN LP Next Page ability register has no effect.

45.2.7.14h AN:M Yes [ ]N/A [ ]






78. Energy-Efficient Ethernet (EEE)

78.1 Overview

78.1.3 Reconciliation sublayer operation

78.1.3.3 PHY LPI operation

78.1.3.3.1 PHY LPI transmit operation

Change the second paragraph of 78.1.3.3.1, adding references to 1000BASE-T1 PHY, as follows:

The EEE capability in most PHYs (for example, 100BASE-TX, 1000BASE-T, 10GBASE-T, 1000BASE-KX, 10GBASE-KR, and 10GBASE-KX4) requires the local PHY transmitter to go quiet after sleep issignalled.

Insert a row for 1000BASE-T1 between 1000BASE-T and XGXS (XAUI) in Table 78–1 as follows(unchanged rows not shown):

78.2 LPI mode timing parameters description

Insert a row for 1000BASE-T1 between 1000BASE-T and XGXS (XAUI) in Table 78–2 as follows(unchanged rows not shown):

Table 78–1—Clauses associated with each PHY or interface type

PHY or interface type Clause

... ...

1000BASE-T1 97

... ...

Table 78–2—Summary of the key EEE parameters for supported PHYsor interfaces

PHY or interface type

Ts s)

Tqs)

Tr s)

Min Max Min Max Min Max

... ... ... ... ... ... ...

1000BASE-T1 3.6 3.6 84.95 84.97 1.44 1.44

... ... ... ... ... ... ...





78.5 Communication link access latency

Insert a row (and footnote) for 1000BASE-T1 after 1000BASE-T in Table 78–4 (as modified by IEEE Std802.3by-2016) as follows (unchanged rows not shown):

Table 78–4—Summary of the LPI timing parameters for supported PHYs or interfaces

PHY or interface type Case

Tw_sys_tx

(min) (s)

Tw_phy

(min) (s)

Tphy_shrink_tx

(max) (s)

Tphy_shrink_rx

(max) (s)

Tw_sys_rx

(min) (s)

... ... ... ... ... ... ...

1000BASE-T1 10.8 10.8 10.8 0a

aAll data transmission in 1000BASE-T1 PHY is synchronized to the PHY frame boundary. As such, the EEE functionin the 1000BASE-T1 PHY is expected to assert the wake signal only at specific moments of time, aligned to PHYframe boundaries, and no shrinkage or delay at the RX side is expected.

0a

... ... ... ... ... ... ...





Insert new clauses, Clause 97 and Clause 98, and corresponding Annexes 97A to 97B and 98A, 98B, and98C, as follows:

97. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium, type 1000BASE-T1

97.1 Overview

This clause defines the type 1000BASE-T1 Physical Coding Sublayer (PCS) and type 1000BASE-T1Physical Medium Attachment (PMA) sublayer. Together, the PCS and PMA sublayers comprise a1000BASE-T1 Physical Layer (PHY). Provided in this clause are fully functional and electricalspecifications for the type 1000BASE-T1 PCS and PMA.

The 1000BASE-T1 PHY is one of the Gigabit Ethernet family of high-speed full-duplex PHYspecifications, capable of operating at 1000 Mb/s. The 1000BASE-T1 PHY is intended to be operated over asingle twisted-pair copper cable, referred to as an automotive link segment (Type A) or optional link segment(Type B), defined in 97.6. The automotive link segment specifications defined in 97.6 may also be used forother applications that have similar link segment requirements. The cabling supporting the operation of the1000BASE-T1 PHY is defined in terms of performance requirements between the attachment points[Medium Dependent Interface (MDI)], allowing implementers to provide their own cabling to operate the1000BASE-T1 PHY as long as the normative requirements included in this clause are met.

This clause also specifies an optional Energy-Efficient Ethernet (EEE) capability. A 1000BASE-T1 thatsupports this capability may enter a Low Power Idle (LPI) mode of operation during periods of low linkutilization as described in Clause 78.

97.1.1 Relationship of 1000BASE-T1 to other standards

The relationship between the 1000BASE-T1 PHY, the ISO Open Systems Interconnection (OSI) ReferenceModel, and the IEEE 802.3 Ethernet Model are shown in Figure 97–1. The PHY sublayers (shown shaded)in Figure 97–1 connect one Clause 4 Media Access Control (MAC) layer to the medium. Auto-Negotiationfor 1000BASE-T1 is defined in Clause 98. GMII is defined in Clause 35.

97.1.2 Operation of 1000BASE-T1

The 1000BASE-T1 PHY operates using full-duplex communications over a single twisted-pair copper cablewith an effective rate of 1 Gb/s in each direction simultaneously while meeting the requirements (EMC,temperature, etc.) of automotive and industrial environments. The PHY supports operation on two types oflink segments:

a) An automotive link segment supporting up to four in-line connectors using a single twisted-paircopper cable for up to at least 15 m (referred to as link segment type A)

b) An optional link segment supporting up to four in-line connectors using a single twisted-pair coppercable for up to at least 40 m to support applications requiring extended physical reach, such as indus-trial and automation controls and transportation (aircraft, railway, bus and heavy trucks). This linksegment is referred to as link segment type B.

The 1000BASE-T1 PHY utilizes 3 level Pulse Amplitude Modulation (PAM3) transmitted at a 750 MBdrate. A 15-bit scrambler is used to improve the EMC performance. GMII TX_D, TX_EN, and TX_ER areencoded together using 80B/81B encoding, where 10 cycles of GMII data and control are encoded togetherin 81 bits to reduce the overhead. To maintain a bit error ratio (BER) of less than or equal to 10–10, the1000BASE-T1 PHY adds 396 bits of Reed-Solomon Forward Error Correction (RS-FEC) parity to each





group of 45 80B/81B blocks (containing 450 octets of GMII data). The PAM3 mapping, scrambler,RS-FEC, and 80B/81B encoder/decoder are all contained in the PCS (see 97.3).

Auto-Negotiation (Clause 98) may optionally be used by 1000BASE-T1 devices to detect the abilities(modes of operation) supported by the device at the other end of a link segment, determine commonabilities, and configure for normal operation. Auto-Negotiation is performed upon link start-up through theuse of half-duplex differential Manchester encoding. The implementation of the Auto-Negotiation functionis optional. If Auto-Negotiation is implemented, it shall meet the requirements of Clause 98.

A 1000BASE-T1 PHY shall be capable of operating as MASTER or SLAVE, per runtime configuration. AMASTER PHY uses a local clock to determine the timing of transmitter operations. A SLAVE PHYrecovers the clock from the received signal and uses it to determine the timing of transmitter operations.When Auto-Negotiation is used, the MASTER-SLAVE relationship between two devices sharing a linksegment is established during Auto-Negotiation (see Clause 98). If Auto-Negotiation is not used, aMASTER-SLAVE relationship shall be established by management or hardware configuration of the PHYs.The MASTER and SLAVE are synchronized by a PHY Link Synchronization function in the PHY (see97.4.2.6).

A 1000BASE-T1 PHY may optionally support Energy-Efficient Ethernet (see Clause 78) and advertise theEEE capability as described in 97.4.2.4.5. The EEE capability is a mechanism by which 1000BASE-T1PHYs are able to reduce power consumption during periods of low link utilization.

The 1000BASE-T1 PHY may optionally support the 1000BASE-T1 PCS-based Operations, Administration,and Maintenance (OAM). The 1000BASE-T1 OAM is useful for monitoring link operation by exchangingPHY link health status and messages. The 1000BASE-T1 OAM information is exchanged between two1000BASE-T1 PHYs out-of-band. The 1000BASE-T1 OAM is specified in 97.3.8, and the 1000BASE-T1PHY advertises its 1000BASE-T1 OAM capability as described in 97.4.2.4.5.

Figure 97–1—Relationship of 1000BASE-T1 PHY to the ISO/IEC OSI reference model and the IEEE 802.3 Ethernet Model

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSI

REFERENCEMODEL

LAYERS

ETHERNET

LAYERS

MAC - MEDIA ACCESS CONTROL

RECONCILIATION

HIGHER LAYERS

MDI = MEDIUM DEPENDENT INTERFACEGMII = TEN GIGABIT MEDIA INDEPENDENT INTERFACE

PCS = PHYSICAL CODING SUBLAYERPMA = PHYSICAL MEDIUM ATTACHMENT

PHY = PHYSICAL LAYER DEVICE

GMII1

MDI

1000BASE-T1

PMA

PCS

AN2

MEDIUM

LLC - LOGICAL LINK CONTROLOR OTHER MAC CLIENT

MAC CONTROL (OPTIONAL)

PHY

NOTE 1—GMII is optionalNOTE 2—Auto-Negotiation is optional AN = AUTO-NEGOTIATION





The 1000BASE-T1 PMA couples messages from the PCS to the MDI and provides clock recovery, linkmanagement, and PHY Control functions. The PMA provides full duplex communications at 750 MBd overthe single twisted-pair copper cable. PMA functionality is described in 97.4. The MDI is specified in 97.7.

97.1.2.1 Physical Coding Sublayer (PCS)

The 1000BASE-T1 PCS couples a Gigabit Media Independent Interface (GMII), as described in Clause 35,to a Physical Medium Attachment (PMA) sublayer, described in 97.4, which supports communication over asingle twisted-pair copper cable.

The PCS comprises the PCS Reset function, PCS Transmit, and PCS Receive. After completion of the Resetfunction, the Transmit and Receive functions start immediately and run simultaneously.

The PCS operates in two modes: the data mode and the training mode. In the data mode, the PCS Transmitfunction data path starts with the GMII interface, where TXD, TX_EN, and TX_ER input data to the PCSevery 8 ns (as clocked by GTX_CLK). Data and control from ten GTX_CLK cycles are 80B/81B encodedinto an 81-bit “81B block” that encodes every possible combination of data and control (control signalsinclude transmit error propagation, receive error, assert low power idle, and inter-frame signaling, as definedin 35.2.1.6). Each set of 45 80B/81B blocks along with 9 bits of 1000BASE-T1 OAM data (see 97.3.8) isprocessed by an RS-FEC encoder. The RS-FEC encoder adds 396 RS-FEC parity bits and the resulting4050 bits (45 80B/81B blocks = 3645 bits, 9 bits of 1000BASE-T1 OAM, and 396 bits of FEC parity bits)are scrambled using a 15-bit side-stream scrambler. The 4050 bits are referred to interchangeably as a PHYframe or as a Reed-Solomon frame. Each group of 3 bits of the scrambled data is converted to 2 PAM3symbols by the 3B2T mapper (the 4050 bits in the PHY frame become 2700 PAM3 symbols) and passed tothe PMA. PCS transmit functions are described in 97.3.2.2.

In the data mode, the PCS Receive function data path operates in the opposite order as the transmit path. Theincoming PAM3 symbols are synchronized to PHY frame boundaries. Within each PHY frame, each twoPAM3 symbols are demapped to 3 bits by the 3B2T demapper (the 2700 PAM3 symbols are converted to4050 bits). The data is then descrambled and passed to the RS-FEC decoder for data validation andcorrection. Finally, each of the 45 80B/81B blocks is 80B/81B decoded into GMII data or control. The PCSdata mode receive is described in 97.3.2.3.

In the training mode (see 97.4.2.4), the PCS transmits and receives PAM2 training sequences to synchronizeto the PHY frame, learns the data mode scrambler seed, and exchanges EEE and 1000BASE-T1 OAMcapabilities. The training mode uses PAM2 encoding.

97.1.2.2 Physical Medium Attachment (PMA) sublayer

The 1000BASE-T1 PMA transmits/receives symbol streams to/from the PCS onto the single balancedtwisted-pair and provides the clock recovery, link monitor, and the 1000BASE-T1 PHY Control function.The PMA provides full duplex communications at 750 MBd.

The PMA PHY Control function generates signals that control the PCS and PMA sublayer operations. PHYControl is enabled following the completion of Auto-Negotiation or PHY Link Synchronization andprovides the start-up functions required for successful 1000BASE-T1 operation. It determines whether thePHY operates in a disabled state, a training state, or a data state where MAC frames can be exchangedbetween the link partners.

The Link Monitor determines the status of the underlying link channel and communicates this status to otherfunctional blocks. A failure of the receive channel causes the data mode operation to stop and Auto-Negotiation or Link Synchronization to restart.

The minimum link segment characteristics, EMC requirements, and test modes are specified in 97.5.





97.1.2.3 EEE capability

A 1000BASE-T1 PHY may optionally support the EEE capability, as described in 78.3. The EEE capabilityis a mechanism by which 1000BASE-T1 PHYs are able to reduce power consumption during periods of lowlink utilization. PHYs can enter the LPI mode of operation after completing training. Each direction of thefull duplex link is able to enter and exit the LPI mode independently, supporting symmetric and asymmetricLPI operation. This allows power savings when only one side of the full duplex link is in a period of lowutilization. The transition to or from LPI mode shall not cause any MAC frames to be lost or corrupted.

In the transmit direction the transition to the LPI transmit mode begins when the PCS transmit functiondetects an “Assert Low Power Idle” condition on the GMII in the last 80B/81B block of a PHY frame. At thenext PHY frame aligned to the wake window the PCS transmits a sleep signal composed of an entire PHYframe containing only LP_IDLE. The sleep signal indicates to the link partner that the transmit function ofthe PHY is entering the LPI transmit mode. Immediately after the transmission of the sleep frame, thetransmit function of the local PHY enters the LPI transmit mode. While the transmit function is in the LPImode the PHY may disable data path and control logic to save additional power. Periodically the transmitfunction of the local PHY transmits refresh frames that may be used by the link partner to update adaptivefilters and timing circuits. LPI mode may begin with quiet signaling, a full refresh period, or a wake frame.The quiet-refresh cycle continues until the PCS function detects a condition that is not Assert Low PowerIdle on the GMII. This condition signals to the PHY that the LPI transmit mode should end. At the next PHYframe the PCS transmits a wake frame composed of an entire PHY frame containing only Idle. On the nextPHY frame normal power mode shall resume.

Support for EEE capability is advertised during Training. See 97.4.2.4.5 for details. Transitions to and fromthe LPI transmit mode are controlled via GMII signaling. Transitions to and from the LPI receive mode arecontrolled by the link partner using sleep and wake signaling.

When the 1000BASE-T1 OAM SNR settings indicate that LPI is insufficient to maintain PHY SNR, thePHY may temporarily be forced to exit LPI mode and send idles.

The PCS 80B/81B Transmit state diagram in Figure 97–14 includes additional states for EEE. The PCS80B/81B Receive state diagram in Figure 97–12 includes additional states for EEE.

97.1.2.4 Link Synchronization

The Link Synchronization function is used when Auto-Negotiation is disabled to synchronize between theMASTER PHY and SLAVE PHY before training starts. Link Synchronization provides a fast and reliablemechanism for the link partner to detect the presence of the other, validate link, and start the timers used bythe link monitor. Link Synchronization operates in a half-duplex fashion. Based on timers, the MASTERPHY sends a synchronization sequence for 1 µs. If there is no response from the SLAVE, the MASTERrepeats by sending a synchronization sequence every 5 µs. If the slave detects the sequence, it responds witha synchronization sequence for 1 µs (after the MASTER has stopped transmitting). If no other detectionhappens after the SLAVE response for 4 µs then Link Synchronization is successfully complete, linkmonitor timers are started, and the PHY Control state machine starts Training. Link synchronization isdefined in 97.4.2.6.





PMA

link_

sta

tus

Figure 97–2—Functional block diagram

PCS

RECEIVE

RX_CLK

RXD<7:0>

RX_DV

RX_ER

PMA_UNITDATA.request

PMA

RECEIVE

PM

A_

Lin

k.re

que

st

GTX_CLK

TX_EN

TX_ER

loc_rcvr_status

PHYCONTROL

reco

vere

d_

clo

ck

tx_mode

config

PMA_UNITDATA.indication

received_clock

TXD<7:0>

TRANSMITPCS

LINKMONITOR

pcs_status / scr_status

(lin

k_co

ntro

l)

PM

A_

Lin

k.in

dic

atio

n

(link

_sta

tus)

(rx_symb)

(tx_symb)

CLOCKRECOVERY

PMATRANSMIT

INDEPENDENTINTERFACE

(GMII)

GIGABIT MEDIA PMA SERVICEINTERFACE

MEDIUM

INTERFACEDEPENDENT

(MDI)

PCS

PHY(INCLUDES PCS AND PMA)

Technology Dependent Interface (optional)

NOTE 1—The recovered_clock arc is shown to indicate delivery of the received clock signal back the PMA TRANSMIT for looptiming.

NOTE 2—Signals and functions shown with dashed lines are optional.

rx_lpi_active

MDI +MDI -

tx_lpi_active

rem_rcvr_status / rem_phy_ready

PCS

OAM

tx_

bo

und

ary

tx_

oam

_fie

ld<

8:0

>rx

_o

am

_fie

ld<

8:0

>

rx_

bou

nda

ry

LINKSYNCHRONIZATION

syn

c_lin

k_co

ntr

ol

loc_

phy_

read

y

sync

_tx_

sym

b





97.1.3 Signaling

1000BASE-T1 signaling is performed by the PCS generating continuous symbol sequences that the PMAtransmits over the single twisted-pair copper cable. The signaling scheme achieves a number of objectivesincluding the following:

a) Algorithmic mapping from TXD<7:0> to PAM3 symbols in the transmit path

b) Algorithmic mapping from PAM3 symbols to RXD<7:0> in the receive path

c) Adding FEC coded data to transmit and validating data using FEC on receive

d) Uncorrelated symbols in the transmitted symbol stream

e) No correlation between symbol streams traveling both directions

f) Ability to signal the status of the local receiver to the remote PHY to indicate that the local receiveris not operating reliably and requires retraining

g) Optionally, ability to signal to the remote PHY that the transmitting PHY is entering the LPI modeor exiting the LPI mode and returning to normal power operation

The PHY may operate in three basic modes: the normal data mode, the training mode, or an optional LPImode.

In the normal data mode, PCS generates symbols that represent data, control, or idles for transmission by thePMA.

In the training mode, the PCS generates only a PAM2 pattern with periodic embedded data that enables thereceiver at the other end to train and synchronize timing, scrambler seeds, and capabilities. The LPI mode isenabled separately in each direction (see LPI signaling in 97.3.5). When transmitting in LPI mode, the PCSgenerates zero symbols and periodically send a REFRESH pattern to keep the two PHYs synchronized (see97.3.2.2.15).

97.1.4 Interfaces

All 1000BASE-T1 PHY implementations are compatible at the MDI and at a physically exposed GMII, ifmade available. Physical implementation of the GMII is optional. Designers are free to implement circuitrywithin the PCS and PMA in an application-dependent manner provided that the MDI and GMII (if the GMIIis implemented) specifications are met. System operation from the perspective of signals at the MDI andmanagement objects are identical whether the GMII is implemented or not.

97.1.5 Conventions in this clause

The body of this clause contains state diagrams, including definitions of variables, constants, and functions.Should there be a discrepancy between a state diagram and descriptive text, the state diagram prevails.

The notation used in the state diagrams follows the conventions of 21.5.

The values of all components in test circuits shall be accurate to within ± 1% unless otherwise stated.

Default initializations, unless specified, are left to the implementer.

97.2 1000BASE-T1 Service Primitives and Interfaces

1000BASE-T1 transfers data and control information across the following four service interfaces:

a) Gigabit Media Independent Interface (GMII)

b) Technology Dependent Interface





c) PMA service interface

d) Medium dependent interface (MDI)

The GMII is specified in Clause 35; the Technology Dependent Interface is specified in 98.4. The PMAservice interface is defined in 97.2.2, and the MDI is defined in 97.7.3.

97.2.1 Technology Dependent Interface

1000BASE-T1 uses the following service primitives to exchange status indications and control signalsacross the Technology Dependent Interface as specified in 98.4:

PMA_LINK.request(link_control)

PMA_LINK.indication(link_status)

97.2.1.1 PMA_LINK.request

This primitive allows the Auto-Negotiation or the PHY Link Synchronization algorithm to enable anddisable operation of the PMA, as specified in 98.4.2, respectively.

97.2.1.1.1 Semantics of the primitive


The link_control parameter can take on one of two values: DISABLE, or ENABLE.

DISABLE Used by the Auto-Negotiation function to disable the PHY

ENABLE Used by the Auto-Negotiation to enable the PHY

97.2.1.1.2 When generated

Auto-Negotiation generates this primitive to indicate a change in link_control as described in 98.4.

97.2.1.1.3 Effect of receipt

This primitive affects the operation of the PMA Link Monitor function as defined in 97.4.2.5, the PMA PHYControl function as defined in 97.4.2.4, and the PMA Receive function defined in 97.4.2.3.

97.2.1.2 PMA_LINK.indication

This primitive is generated by the PMA to indicate the status of the underlying medium as specified in98.4.1. This primitive informs the PCS, PMA PHY Control function, and the Auto-Negotiation functionsabout the status of the underlying link.



The link_status parameter can take on one of two values: FAIL or OK.

FAIL No valid link established

OK The Link Monitor function indicates that a valid 1000BASE-T1 link is established.Reliable reception of signals transmitted from the remote PHY is possible.






The PMA generates this primitive to indicate a change in link_status in compliance with the state diagramgiven in Figure 97–27.


The effect of receipt of this primitive is specified in 98.4.1.

97.2.2 PMA service interface

1000BASE-T1 uses the following service primitives to exchange symbol vectors, status indications, andcontrol signals across the service interfaces:

PMA_TXMODE.indication(tx_mode)PMA_CONFIG.indication(config)PMA_UNITDATA.request(tx_symb)PMA_UNITDATA.indication(rx_symb)PMA_SCRSTATUS.request(scr_status)PMA_PCSSTATUS.request(pcs_status)PMA_RXSTATUS.indication(loc_rcvr_status)PMA_PHYREADY.indication(loc_phy_ready)PMA_REMRXSTATUS.request(rem_rcvr_status)PMA_REMPHYREADY.request(rem_phy_ready)

The use of these primitives is illustrated in Figure 97–3. Connections from the management interface(signals MDC and MDIO) to the sublayers are pervasive and are not shown in Figure 97–3.

EEE-capable PHYs additionally support the following service primitives:

PMA_PCS_RX_LPI_STATUS.request(rx_lpi_active)PMA_PCS_TX_LPI_STATUS.request(tx_lpi_active)

97.2.2.1 PMA_TXMODE.indication

The transmitter in a 1000BASE-T1 link normally sends over the MDI symbols that represent a GMII datastream with framing, scrambling and encoding of data, control information, or idles.


PMA_TXMODE.indication(tx_mode)

PMA_TXMODE.indication specifies to PCS Transmit via the parameter tx_mode what sequence ofsymbols the PCS should be transmitting. The parameter tx_mode can take on one of the following fourvalues of the form:

SEND_NThis value is continuously asserted during transmission of sequences of symbols representing a GMII data stream in the data mode

SEND_IThis value is continuously asserted when transmission of sequences of idle symbols is to take place

SEND_TThis value is continuously asserted in case transmission of sequences of symbols representing the training mode is to take place

SEND_ZThis value is continuously asserted in case transmission of zeros is required





97.2.2.1.2.When generated

The PMA PHY Control function generates PMA_TXMODE.indication messages to indicate a change intx_mode.


Upon receipt of this primitive, the PCS performs its transmit function as described in 97.3.2.2.

Figure 97–3—1000BASE-T1 service interfaces

MDI +MDI -

TXD<7:0>

GTX_CLK

TX_EN

TX_ER

RX_CLK

RXD<7:0>

RX_DV

RX_ER

MDIO

MDC

PMA_TXMODE.indication

PMA_CONFIG.indication

PMA_UNITDATA.indication

PM

A_L

INK

.requ

est

PMA_RXSTATUS.indication

PM

A_L

INK

.indi

catio

n MEDIUM

INTERFACEDEPENDENT

(MDI)

PMA_UNITDATA.request

PMA_REMRXSTATUS.request

PMA_SCRSTATUS.request

PMA SERVICEINTERFACEINDEPENDENT

INTERFACE(GMII)

GIGABIT MEDIA

PHY

MANAGEMENT

PMAPCS

Technology Dependent Interface (optional)

NOTE—Service interface primitives shown with dashed lines are optional.

PMA_PCS_RX_LPI_STATUS.request

PMA_PCSSTATUS.request

PMA_PCS_TX_LPI_STATUS.request

PMA_REMPHYREADY.request

PMA_PHYREADY.indication





97.2.2.2 PMA_CONFIG.indication

Each PHY in a 1000BASE-T1 link is capable of operating as a MASTER PHY and as a SLAVE PHY. If theAuto-Negotiation process is enabled, PMA_CONFIG MASTER-SLAVE configuration is determinedduring Auto-Negotiation (Clause 98) and the result is provided to the PMA. If the Auto-Negotiation processis not implemented or not enabled, PMA_CONFIG MASTER-SLAVE configuration is predetermined to beMASTER or SLAVE via management control during initialization or via default hardware setup.


PMA_CONFIG.indication(config)

PMA_CONFIG.indication specifies to PCS and PMA Transmit via the parameter config whether the PHYoperates as a MASTER PHY or as a SLAVE PHY. The parameter config can take on one of the followingtwo values of the form:

MASTER This value is continuously asserted when the PHY operates as a MASTER PHYSLAVE This value is continuously asserted when the PHY operates as a SLAVE PHY


PMA generates PMA_CONFIG.indication messages to indicate a change in configuration.


PCS and PMA Clock Recovery perform their functions in MASTER or SLAVE configuration according tothe value assumed by the parameter configuration.

97.2.2.3 PMA_UNITDATA.request

This primitive defines the transfer of symbols in the form of the tx_symb parameter from the PCS to thePMA. The symbols are obtained in the PCS Transmit function using the encoding rules defined in 97.3.2.2to represent GMII data and control streams or other sequences.


PMA_UNITDATA.request(tx_symb)

During transmission, the PMA_UNITDATA.request simultaneously conveys to the PMA via the parametertx_symb the value of the symbols to be sent over the MDI. The tx_symb may take on one of the values in theset { –1, 0, 1 }


The PCS generates PMA_UNITDATA.request(tx_symb) synchronously with every transmit clock cycle.


Upon receipt of this primitive the PMA transmits on the MDI the signals corresponding to the indicatedsymbols after processing with optional transmit filtering and other specified PMA Transmit processing.





97.2.2.4 PMA_UNITDATA.indication

This primitive defines the transfer of symbols in the form of the rx_symb parameter from the PMA to thePCS.


PMA_UNITDATA.indication(rx_symb)

During reception the PMA_UNITDATA.indication conveys to the PCS via the parameter rx_symb the valueof symbols detected on the MDI during each cycle of the recovered clock.


The PMA generates PMA_UNITDATA.indication(rx_symb) messages synchronously for every symbolreceived at the MDI. The nominal rate of the PMA_UNITDATA.indication primitive is 750 MHz, asgoverned by the recovered clock.


The effect of receipt of this primitive is unspecified.

97.2.2.5 PMA_SCRSTATUS.request

This primitive is generated by PCS Receive to communicate the status of the descrambler for the local PHY.The parameter scr_status conveys to the PMA Receive function the information that the training modedescrambler has achieved synchronization.


PMA_SCRSTATUS.request(scr_status)

The scr_status parameter can take on one of two values of the form:

OK The training mode descrambler has achieved synchronizationNOT_OK The training mode descrambler is not synchronized


PCS Receive generates PMA_SCRSTATUS.request messages to indicate a change in scr_status.


The effect of receipt of this primitive is specified in 97.4.2.3 and 97.4.2.4.

97.2.2.6 PMA_PCSSTATUS.request

This primitive is generated by PCS Receive to indicate the fully operational state of the PCS for the localPHY. The parameter pcs_status conveys to the PMA Receive function the information that the PCS isoperating reliably in the data mode.


PMA_PCSSTATUS.request(pcs_status)





The pcs_status parameter can take on one of two values of the form:

OK The PCS is operating reliably in the data modeNOT_OK The PCS is not operating reliably in the data mode


PCS Receive generates PMA_PCSSTATUS.request messages to indicate a change in pcs_status.


The effect of receipt of this primitive is specified in 97.4.4.1.

97.2.2.7 PMA_RXSTATUS.indication

This primitive is generated by PMA Receive to indicate the status of the receive link at the local PHY. Theparameter loc_rcvr_status conveys to the PCS Transmit, PCS Receive, PMA PHY Control function, andLink Monitor the information on whether the status of the overall receive link is satisfactory or not. Notethat loc_rcvr_status is used by the PCS Receive decoding functions. The criterion for setting the parameterloc_rcvr_status is left to the implementer. It can be based, for example, on observing the mean-square errorat the decision point of the receiver and detecting errors during reception of symbol stream.


PMA_RXSTATUS.indication(loc_rcvr_status)

The loc_rcvr_status parameter can take on one of two values of the form:

OK This value is asserted and remains true during reliable operation of the receivelink for the local PHY

NOT_OK This value is asserted whenever operation of the link for the local PHY is unreliable


PMA Receive generates PMA_RXSTATUS.indication messages to indicate a change in loc_rcvr_status onthe basis of signals received at the MDI.


The effect of receipt of this primitive is specified in Figure 97–26, 97.3.2.3, 97.4.2.4, and 97.4.597.4.5.

97.2.2.8 PMA_PHYREADY.indication

This primitive is generated by PMA Receive to indicate the local PHY is ready or not ready to receive data.The parameter loc_phy_ready is conveyed to the link partner by the PCS as defined in Table 97–1.


PMA_PHYREADY.indication(loc_phy_ready)

The loc_phy_ready parameter can take on one of two values of the form:

OK The local PHY is ready to receive dataNOT_OK The local PHY is not ready to receive data






PMA Receive generates PMA_PHYREADY.indication messages to indicate a change in loc_phy_readybased on loc_rcvr_status and pcs_status values.


The effect of receipt of this primitive is specified in Figure 97–26 and Figure 97–27.

97.2.2.9 PMA_REMRXSTATUS.request

This primitive is generated by PCS Receive to indicate the status of the receive link at the remote PHY ascommunicated by the remote PHY via its encoding of its loc_rcvr_status parameter. The parameterrem_rcvr_status conveys to the PMA PHY Control function the information on whether reliable operation ofthe remote PHY is detected or not. The parameter rem_rcvr_status is set to the value received in theloc_rcvr_status bit in the InfoField from the remote PHY. The rem_rcvr_status is set to NOT_OK if the PCShas not decoded a valid InfoField from the remote PHY.


PMA_REMRXSTATUS.request(rem_rcvr_status)

The rem_rcvr_status parameter can take on one of two values of the form:

OK The receive link for the remote PHY is operating reliablyNOT_OK Reliable operation of the receive link for the remote PHY is not detected


The PCS generates PMA_REMRXSTATUS.request messages to indicate a change in rem_rcvr_status basedon the PCS decoding the loc_rcvr_status bit in InfoField messages received from the remote PHY duringtraining.


The effect of receipt of this primitive is specified in Figure 97–26.

97.2.2.10 PMA_REMPHYREADY.request

This primitive is generated by PCS Receive to indicate whether the remote PHY is ready or not ready toreceive data. Its value is received from the link partner by the PCS as defined in Table 97–1.


PMA_REMPHYREADY.request(rem_phy_ready)

The rem_phy_ready parameter can take on one of two values of the form:

OK The remote PHY is ready to receive dataNOT_OK The remote PHY is not ready to receive data






The PCS generates PMA_REMPHYREADY.request messages to indicate a change in rem_phy_readybased on the PCS decoding the control words in Table 97–1 received from the remote PHY.


The effect of receipt of this primitive is specified in Figure 97–26.

97.2.2.11 PMA_PCS_RX_LPI_STATUS.request

When the PHY supports the EEE capability this primitive is generated by the PCS receive function toindicate the status of the receive link at the local PHY. The parameterPMA_PCS_RX_LPI_STATUS.request conveys to the PCS transmit and PMA receive functionsinformation regarding whether the receive function is in the LPI receive mode.


PMA_PCS_RX_LPI_STATUS.request(rx_lpi_active)

The rx_lpi_active parameter can take on one of two values of the form:

true The receive function is in the LPI receive modefalse The receive function is not in the LPI receive mode


The PCS generates PMA_PCS_RX_LPI_STATUS.request messages to indicate a change in therx_lpi_active variable as described in 97.3.2.3 and 97.3.6.2.2.



97.2.2.12 PMA_PCS_TX_LPI_STATUS.request

When the PHY supports the EEE capability this primitive is generated by the PCS transmit function toindicate the status of the transmit link at the local PHY. The parameterPMA_PCS_TX_LPI_STATUS.request conveys to the PCS transmit and PMA receive functions informationregarding whether the transmit function is in the LPI transmit mode.


PMA_PCS_TX_LPI_STATUS.request(tx_lpi_active)

The tx_lpi_active parameter can take on one of two values of the form:

true The transmit function is in the LPI transmit modefalse The transmit function is not in the LPI transmit mode


The PCS generates PMA_PCS_TX_LPI_STATUS.request messages to indicate a change in thetx_lpi_active variable as described in 97.3.5 and 97.3.6.2.2.







97.3 Physical Coding Sublayer (PCS)

97.3.1 PCS service interface (GMII)

The PCS service interface allows the 1000BASE-T1 PCS to transfer information to and from a PCS client.The PCS Interface is defined as the Gigabit Media Independent Interface (GMII) in Clause 35.

97.3.2 PCS functions

The PCS comprises one PCS Reset function and two simultaneous and asynchronous operating functions.The PCS operating functions are: PCS Transmit and PCS Receive. All operating functions start immediatelyafter the successful completion of the PCS Reset function.

The PCS reference diagram, Figure 97–4, shows how the two operating functions relate to the messages ofthe PCS-PMA interface. Connections from the management interface (signals MDC and MDIO) to otherlayers are pervasive and are not shown in Figure 97–4.

97.3.2.1 PCS Reset function

PCS Reset initializes all PCS functions. The PCS Reset function shall be executed whenever one of thefollowing conditions occur:

a) Power for the device containing the PMA has not reached the operating state

b) The receipt of a request for reset from the management entity

PCS Reset sets pcs_reset = ON while any of the above reset conditions hold true. All state diagrams take theopen-ended pcs_reset branch upon execution of PCS Reset. The reference diagrams do not explicitly showthe PCS Reset function.

97.3.2.2 PCS Transmit function

The PCS Transmit function shall conform to the PCS 80B/81B Transmit state diagram in Figure 97–14 andthe PCS Transmit bit ordering in Figure 97–5 and Figure 97–7.

When communicating with the GMII, the PCS uses an octet-wide, synchronous data path, with packetdelimiting being provided by transmit control signals and receive control signals. Alignment to 80B/81Bblocks is performed in the PCS. The PMA sublayer operates independently of block and packet boundaries.The PCS provides the functions necessary to map packets between the GMII format and the PMA serviceinterface format.

When the transmit channel is in the data mode, the PCS Transmit process continuously generates 80B/81Bblocks based upon the TXD <7:0>, TX_EN and TX_ER signals on the GMII. The subsequent functions ofthe PCS Transmit process then pack the resulting blocks plus one 1000BASE-T1 OAM symbol, both ofwhich are then processed by a Reed-Solomon (RS-FEC) encoder and subsequently 3B2T mapped into atransmit PHY frame of PAM3 symbols. Transmit data-units are sent to the PMA service interface via thePMA_UNITDATA.request primitive. A symbol period, T, is 4/3 ns.





If a PMA_TXMODE.indication message has the value SEND_T, PCS Transmit generates sequences ofcodes defined in 97.3.4.2 to the PMA via the PMA_UNITDATA.request primitive. These codes are used fortraining mode and only transmit the values {–1, +1}.

During training mode an InfoField is transmitted at regular intervals containing messages for start-upoperation. By this mechanism, a PHY indicates the status of its own receiver to the link partner. (See97.4.2.4.)

In the data mode of operation, the PMA_TXMODE.indication message has the value SEND_N, and thePCS Transmit function uses an 81B-RS coding technique to generate at each symbol period symbols thatrepresent data or control. During transmission, 45 80B/81B blocks shall be aggregated, encoded by a PHYframe encoder, and then scrambled by a PCS scrambler. During data encoding PCS Transmit frames shall beencoded into a sequence of PAM3 symbols and transferred to the PMA.

Dashed rectangles in Figure 97–14 indicate states and state transitions in the transmit process state diagramthat are supported by PHYs with the EEE capability. PHYs without the EEE capability do not support thesetransitions.

After reaching the data mode of operation, EEE-capable PHYs may enter the LPI transmit mode under thecontrol of the MAC via the GMII. The EEE Transmit state diagram is contained within the PCS Transmitfunction. The EEE capability is described in 97.3.2.2.15.

Figure 97–4—PCS reference diagram

loc_phy_ready

RECEIVEPCS

GIGABIT MEDIA INDEPENDENTINTERFACE (GMII)

TRANSMITPCS

tx_mode

tx_symb

tx_lpi_active

TX_E

R

GTX

_CLK

TX_E

N

TXD

<7:0>

scr_status / pcs_status

rx_symb

config

rem_rcvr_status / rem

_phy_ready

loc_rcvr_status

link_status

rx_lpi_active

RX

_ER

RX

_CLK

RX

_DV

RX

D<7:0>

PMA SERVICEINTERFACE

PC

S

OAMPCS

rx_boundary

rx_oam_field<8:0>tx_boundary

tx_oam_field<8:0>





97.3.2.2.1 Use of blocks

The PCS maps GMII signals into 81-bit blocks inserted into a PHY frame, and vice versa, using an 81B-RScoding scheme. The PAM2 PMA training frame synchronization allows establishment of PHY frame and81B boundaries by the PCS Synchronization process. Blocks and PHY frames are unobservable and have nomeaning outside the PCS. The PCS functions ENCODE and DECODE generate, manipulate, and interpretblocks and PHY frames as provided by the rules in 97.3.2.2.2.

97.3.2.2.2 81B-RS transmission code

The PCS uses a transmission code to improve the transmission characteristics of information to betransferred across the link and to support transmission of control and data characters. The encoding definedby the transmission code ensures that sufficient information is present in the PHY bit stream to make clockrecovery possible at the receiver. The encoding also preserves the likelihood of detecting any PHY frameerrors that may occur during transmission and reception of information. In addition, the code enables thereceiver to achieve PCS synchronization alignment on the incoming PHY bit stream.

The relationship of block bit positions to GMII, PMA, and other PCS constructs is illustrated in Figure 97–5for transmit and Figure 97–6 for receive. These figures illustrate the processing of a multiplicity of blockscontaining 10 data octets. See 97.3.2.2.5 for information on how blocks containing control characters aremapped.

97.3.2.2.3 Notation conventions

For values shown as binary, the leftmost bit is the first transmitted bit.

97.3.2.2.4 Transmission order

The PCS Transmit bit ordering shall conform to Figure 97–5 and Figure 97–7. Note that these figures showthe mapping from GMII to 80B/81B block for a block containing ten data characters. The LSB of the1000BASE-T1 OAM symbol is transmitted first.

97.3.2.2.5 Block structure

Blocks consist of 81 bits. The first bit of a block is the data/ctrl header. Blocks are either data blocks orcontrol blocks. The data/ctrl header is 0 for data blocks and 1 for control blocks. The remainder of the blockcontains the payload.

Data blocks contain 10 data octets. Control blocks begin with a 5-bit pointer field that indicates the locationof the first control code within the block. Bits 0 to 3 of the pointer field points to the next octet that is acontrol symbol. Bit 4 of the pointer field indicates whether the next control symbol is the final controlsymbol of the block: 0 = final, 1 = more control symbols. If the first octet in the block is a control character,the pointer field is followed by a 3-bit control code. Otherwise the pointer field is followed by one or moredata octets until the position of the first control code. Then the 3-bit control code indicates type of controlcharacter. The control code is followed by a 5-bit pointer field to the next control character if the priorpointer field value was greater than 15 (i.e., bit 4 = 1). The pointer field may be followed by a data octet orcontrol code depending on the value of the pointer field. In this way any combination of ten data octets andcontrol characters may be encapsulated within an 80B/81B block.





Figure 97–5—PCS Transmit bit ordering

GMII

TX

D<

0>

1st transfer

Output of encoderD0 D1 D2 D9

0 7

PMA service

function

Data/Ctrlheader

RS-FEC frame

interface

TX

D<

7>

2nd transfer

3rd transfer

10th transfer

TXB<0> TXB<80>

LSB

Reed-Solomon FEC Encode

OAM

RSC<43>RSC<0>RSD<405>RSD<404>RSD<0>

Data mode Tx scrambler

3B2T mapper

PAM3<2699>

PAM3<1000>

PAM3<0>

PAM3<1>

PAM3<2>

Aggregate 45 x 80B/81B blocks, plus OAM

80B/81B block

80B/81B block 2

80B/81B block 1

80B/81B block 45





Figure 97–6—PCS Receive bit ordering

GMII

RX

D<

0>

1st transfer

Input to decoderD0 D1 D2 D9

0 7

PMA service

function 80B/81B block

Data/Ctrlheader

RS-FEC decoded

interface

RX

D<

7>

2nd transfer

3rd transfer

10th transfer

RXB<0> RXB<80>

Reed-Solomon FEC Decode

Data mode Rx scrambler

3B2T demapper

rx PAM3<1000>

rx PAM3<0>

rx PAM3<1>

rx PAM3<2>

Aggregate 45 x 80B/ 80B/81B blocks, extract OAM

frame

rx RSCrx RSCrx RSDrx RSDrx RSDRS-FEC receivedframe

Frame Sync

rx_data-group<0:2699>

rx PAM3<2699>

<0> <40> <40> <0> <43

OAM 80B/81B block 2

80B/81B block 1

80B/81B block 45





The 80B/81B block encoding is defined by the following pseudo-code, where N = 10.

N = number of GMII octets encoded into block. Octets numbered n = 0,1,2,…,N–1. octet 0 is the first one presented on GMII.TC[n] = 0 if octet n is data octet on GMII, 1 if octet n is control octet on GMIITC[–1] = 1 by definitionTD[n][0:7] = GMII octet n TXD[0:7] if TC[n] = 0TD[n][5:7] = 010 – IPG (loc_phy_ready = OK), 101 – LPI, 001 – TX Error, 000 – IPG (loc_phy_ready = NOT_OK) if TC[n] = 1. TD[n][0:4] is undefined.B[0:8N] is the 8N+1 block. Bit 0 transmitted first.OR(n) = Bitwise OR of TC[n:N–1]NEXT(n)[0:3] = bit position of lowest bit in TC[n:N–1] that is a 1. Bit 3 is MSB. NEXT(n)[4] = 0 if Bitwise SUM of TC[n:N–1] = 1, else 1

B[0] = OR(0)B[8n+1:8n+4] = TD[n][0:3] – if OR(n) = 0

NEXT(n)[0:3] – if OR(n) = 1 AND TC[n–1] = 1TD[n–1][3:6] – if OR(n) = 1 AND TC[n–1] = 0

B[8n+5] = TD[n][4] – if OR(n) = 0NEXT(n)[4] – if OR(n) = 1 AND TC[n–1] = 1TD[n–1][7] – if OR(n) = 1 AND TC[n–1] = 0

B[8n+6:8n+8] = TD[n][5:7] – if OR(n) = 0TD[n][5:7] – if OR(n) = 1 AND TC[n] = 1TD[n][0:2] – if OR(n) = 1 AND TC[n] = 0

97.3.2.2.6 Control codes

A subset of control characters defined at the GMII are supported by the 1000BASE-T1 PCS. When TX_ERand TX_EN are both asserted, the 1000BASE-T1 PCS conveys an Error symbol in the 80B/81B block code.When TX_EN is not asserted and no other supported control code is present at the GMII, the 1000BASE-T1PCS conveys a Normal Inter-Frame control code in the 80B/81B block code.

Figure 97–7—PCS detailed transmit bit ordering

XOR

81B block 1 81B block 2 81B block 45

RS-FEC symbol

80080

RS-FEC symbol

16181179

800 1 800 1 800 1

RS-FEC symbol

36443564404396

RS-FEC symbol

40493654449406

OAM

4053645:3653

PCS

RS ENC

output

outputsymb #

bit #

scramblerscr [0:4096]

Binary

800

Binary

16181

Binary

36443564

Binary

40493654

Binary

3645:3653

scrambleroutput

bit #

Ternary

530

Ternary

10754

Ternary

24292376

Ternary

26992436

Ternary

2430:2435





The control characters and their mappings to 1000BASE-T1 control code and GMII control code arespecified in Table 97–1. All GMII and 1000BASE-T1 control code values that do not appear in the tableshall not be transmitted and shall be treated as an error if received.

The Carrier Extend and Carrier Extend Error, and Reserved transactions, if any occurred, are assigned toNormal inter-frame in the PCS 80B/81B Encoder.

97.3.2.2.7 Idle

Idle (Normal Inter-frame) control characters are transmitted when TX_EN is not asserted and no othersupported control code is present at the GMII. Idle characters may be added or deleted by the PCS to adaptbetween clock rates. Idle characters shall not be added within a MAC frame.

97.3.2.2.8 LP_IDLE

The low power idle control characters (LP_IDLEs) are transmitted when TX_EN is not asserted, TX_ER isasserted, and TXD<7:0> = 0x1. A continuous stream of LPI control characters is used to maintain a link inthe LPI transmit mode. Idle control characters are used to transition from the LPI transmit mode to thenormal power mode. EEE compliant PHYs respond to the Assert Low Power Idle condition on the GMIIusing the procedure outlined in 97.1.2.3. LP_IDLE characters may be added or deleted by the PCS to adaptbetween clock rates. LP_IDLE characters shall not be added within a MAC frame.

Where the GMII and PMA sublayer data rates are not synchronized, the transmit process needs to insertLPI_IDLEs, or delete LPI_IDLEs to adapt between the rates.

If EEE is not supported, then LP_IDLE shall be converted to IDLE.

97.3.2.2.9 Error

The Error control code is sent when TX_ER and TX_EN are both asserted. Error allows physical sublayerssuch as the PCS to propagate received errors.

97.3.2.2.10 Transmit process

The transmit process generates blocks based upon the TXD<7:0>, TX_EN, and TX_ER signals receivedfrom the GMII. Ten GMII data transfers are encoded into each block. It takes 2700 PMA_UNITDATAtransfers to send a PHY frame of data. Where the GMII and PMA sublayer data rates are not synchronized tothat ratio, the transmit process needs to insert idles, or delete idles to adapt between the rates.

Table 97–1—GMII control code mapping

Control Code[0:2] GMII Transmit GMII Receive

000 Normal Inter-Frame with loc_phy_ready = NOT_OK

Normal Inter-Frame with rem_phy_ready = NOT_OK

001 Transmit Error Propagation

Data Reception Error

010 Normal Inter-Frame with loc_phy_ready = OK

Normal Inter-Frame with rem_phy_ready = OK

101 Assert Low Power Idle Assert Low Power Idle





The transmit process generates blocks as specified in the transmit process state diagram. The contents ofeach block are contained in a vector tx_coded<80:0>, which is aggregated with 45 80B/81B blocks and1000BASE-T1 OAM, then passed to the RS-FEC Encoder and then finally passed to the scrambler.tx_coded<0> contains the data/ctrl header and the remainder of the bits contain the block payload.

97.3.2.2.11 RS-FEC encoder

The 1000BASE-T1 PCS shall encode the transmitted data stream using Reed-Solomon code (450,406). TheRS-FEC encoder shall follow the bit order described in 97.3.2.2.3 where the LSB is the first bit into the RS-FEC encoder and the first transmitted bit.

The FEC code used for 1000BASE-T1 links is a shortened Reed-Solomon (450,406) code over the GaloisField of GF(29)—a code operating on 9-bit symbols, as shown in Figure 97–8. The code encodes406 information symbols and adds 44 parity symbols, enabling correction of up to 22 symbol errors. Thecode is systematic, meaning that the information symbols are not disturbed in any way in the encoder andthe parity symbols are added separately to each block.

The code is based on the generating polynomial shown in Equation (97–1).

(97–1)

where

is a root of the binary primitive polynomial x9 + x4 + 1 and is represented as 0x002A is a series representing the resulting polynomial coefficients of G(Z), (A44 is equal to 0x001)

Z corresponds to an 9-bit GF(29) symbol

x corresponds to a bit position in a GF(29) symbol

The parity calculation shall produce the same result as the shift register implementation shown in Figure 97–8.Before calculation begins, the shift register shall be initialized to zero. The contents of the shift register aretransmitted without inversion.

A FEC parity vector is represented by Equation (97–2).

(97–2)

where

is the data vector . is the first 9-bit data symbol and is the last

is the parity vector . is the first 9-bit parity symbol and is

the last

A data symbol (d8, d7, ...., d1, d0) is identified with the element: d88 + d7

7 + .... + d11 + d0 in GF(29), the

finite field with 29 elements.

The d0 is identified as the LSB and d8 is identified as the MSB for all symbols.

The resulting payload of scrambled 45 80B/81B blocks, followed by the 1000BASE-T1 OAM symbolresults in a total payload of 3654 bits. The resulting PHY frame size is 450 9-bit symbols, a total of4050 bits. Figure 97–7 shows the bit mapping between PCS and FEC.

G Z Z i– A44Z44 A43Z43 A0Z0+ + +=

i 0=

43

=

P Z D Z mod G Z =

D Z D Z D405Z449

D404Z448 D0Z

44+ + += D405

D0

P Z P Z P43Z43

P42Z42 P0Z

0+ += P43 P0





97.3.2.2.12 PCS scrambler

The PCS Transmit function employs side-stream scrambling. The scrambler for the MASTER shall producethe same result as the implementation shown in Figure 97–9. This implements the scrambler polynomial asshown in Equation (97–3):3

(97–3)

The scrambler for the SLAVE shall produce the same result as the implementation shown in Figure 97–9.This implements the scrambler polynomial as shown in Equation (97–4):

(97–4)

The initial seed values for the MASTER and SLAVE scramblers are left to the implementer. The seed valuesshall be non-zero and transmitted during the InfoField exchange. (See 97.4.2.4.5). The scrambler is runcontinuously on all PHY frame output bits.

97.3.2.2.13 3B2T to PAM3

The 3B2T mapper generates 2700 PAM3 symbols per PHY frame that are sent to the PMA viaPMA_UNITDATA.request. Every 9-bit symbol is divided into three 3-bit groups with the LSB bits as thefirst group. Each 3-bit group is then mapped by the 3B2T into 2 PAM3 symbols. The mapping of 3B2T toPAM3 is illustrated in Table 97–2. B[0] is the LSB and T[0] is the first PAM3 symbol transmitted..

3The convention here, which considers the most recent bit into the scrambler to be the lowest order term, is consistent with mostreferences and with other scramblers shown in this standard. Some references consider the most recent bit into the scrambler to be thehighest order term and would therefore identify this as the inverse of the polynomial in Equation (97–3). In case of doubt, note that theconformance requirement is based on the representation of the scrambler in the figure rather than the polynomial equation.

Figure 97–8—Circuit for generating FEC parity vector

*A0 *A1

GFMultiply

+

GFAdd

P0

*A2

+

P1

*A43

+

P42

*A44

+

P43

GF(29)SR

D405,D404, ... D1,D0

G x 1 x4 x15+ +=

G x 1 x11 x15+ +=

Figure 97–9—MASTER and SLAVE PCS scramblers

PCS scrambler employed by the SLAVE

PCS scrambler employed by the MASTER

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14

+

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14

+





97.3.2.2.14 81B-RS framer

The 81B-RS framer adapts between the 81-bit width of the 80B/81B blocks and the PAM3 input to thePMA. When the transmit channel is operating in the data mode, the 81B-RS sends one PAM3 symbol oftransmit data at a time via PMA_UNITDATA.request primitives. The PMA_UNITDATA.request primitivesare fully packed with bits.

97.3.2.2.15 EEE capability

The optional 1000BASE-T1 EEE capability allows compliant PHYs to transition to an LPI mode ofoperation when link utilization is low. EEE compliant PHYs shall implement the transmit state diagramincluding the EEE portion, noted by dotted lines in Figure 97–14, within the PCS.

When there is an Assert Low Power Idle while in the SEND_DATA state the PHY transmits the sleep signalto indicate to the link partner that it is transitioning to the SEND_LPI state. The sleep signal is one PHYframe composed entirely of LP_IDLE characters. If the LP_IDLE character fills the entire last 80B/81Bblock then the sleep signal is the next PHY frame. The PHY shall transmit no PHY frames partially filledwith LP_IDLES.

Following the transmission of the sleep signal, quiet-refresh signaling begins, as described in 97.3.5.

While the PMA asserts SEND_N, the lpi_tx_mode variable shall control the transmit signal through thePMA_UNITDATA.request primitive described as follows:

— When the PMA_TXMODE.indication message does not have the value of SEND_N, thelpi_tx_mode variable is ignored

— When the lpi_tx_mode variable takes the value NORMAL the PCS passes coded data to the PMAvia the PMA_UNITDATA.request primitive

— When the lpi_tx_mode variable takes the value QUIET the PCS passes zeros to the PMA through thePMA_UNITDATA.request primitive

— When the lpi_tx_mode variable takes the value REFRESH, the PCS passes zero data encodedthrough PCS data path to the PMA via the PMA_UNITDATA.request primitive

The quiet-refresh cycle is repeated until Assert Low Power Idle is not detected at the GMII (indicating thatthe local system is requesting a transition back to the normal power mode) or until an 1000BASE-T1 OAM

Table 97–2—3B2T Mapping to PAM3

B[2], B[1], B[0] T[1], T[0]

000 –1,–1

001 0,–1

010 –1,0

011 –1,+1

100 +1,0

101 +1,–1

110 +1,+1

111 0,+1





message with SNR<1:0> set to 01 is transmitted to or received from the link partner (indicating that the LPIrefresh is insufficient to maintain the SNR). At the next wake frame window the PCS transmits a wakeframe composed of an entire PHY frame containing only Idle. The wake frame shall be sent only duringalternating PHY frame counts.

The wake signal occurs at the beginning of every second PHY frame boundary, and the maximum durationof the PHY wake time is 10.8 s (lpi_wake_timer = Tw_phy as defined by Clause 78).

97.3.2.3 PCS Receive function

The PCS Receive function shall conform to the PCS 80B/81B receive state diagram in Figure 97–12 and thePCS Receive bit ordering in Figure 97–6 including compliance with the associated state variables asspecified in 97.3.6.

The PCS Receive function accepts received symbols provided by the PMA Receive function via theparameter rx_symb. The PCS receiver uses knowledge of the PMA training alignment to correctly align the81B-RS frames. The received 81B-RS frames are decoded with error correction; the framing is checked; andthe 80B/81B blocks are converted to 10 data octets to obtain the signals RXD<7:0>, RX_DV, and RX_ERfor transmission to the GMII.

During PMA training mode, PCS Receive checks the received PAM2 framing and signals the reliableacquisition of the descrambler state by setting the parameter scr_status to OK.

When the PCS Synchronization process has obtained synchronization, the PHY frame error rate (RFER)monitor process monitors the signal quality asserting hi_rfer if excessive PHY frame errors are detected (RSparity error). If 40 consecutive PHY frame errors are detected, the block_lock flag is de-asserted. Whenblock_lock is asserted and hi_rfer is de-asserted, the PCS Receive process continuously accepts blocks. ThePCS Receive process monitors these blocks and generates RXD<7:0>, RX_DV and RX_ER fortransmission to the GMII.

When the receive channel is in training mode, the PCS Synchronization process continuously monitorsPMA_RXSTATUS.indication(loc_rcvr_status). When loc_rcvr_status indicates OK, then the PCSSynchronization process accepts data-units via the PMA_UNITDATA.request primitive. It attains PHYframe and block synchronization based on the PMA training frames and conveys received blocks to the PCSReceive process. The PCS Synchronization process sets the block_lock flag to indicate whether the PCS hasobtained synchronization. The PMA training sequence includes 1 bit pattern every 180 PAM2 symbols,which is aligned with the PCS partial PHY frame boundary, as well as an InfoField, which is inserted in the15th PCS partial PHY frame. When the PCS Synchronization process is synchronized to the PHY frameboundary using this pattern, block_lock is asserted. One partial PHY frame codeword is defined to be 1/15of a PHY frame. Fifteen partial PHY frames concatenated back to back form one PHY frame. The start ofthe first partial PHY frame coincides with the start of the PHY frame.

PHYs with the EEE capability support transition to the LPI mode when the PHY has successfully completedtraining. Transitions to and from the LPI mode are allowed to occur independently in the transmit andreceive functions. The PCS receive function is responsible for detecting transitions to and from the LPIreceive mode and indicating these transitions using signals defined in 97.3.6.

The link partner signals a transition to the LPI mode of operation by transmitting one PHY frame composedentirely of 80B/81B blocks of LP_IDLES. When blocks of LP_IDLES are detected at the output of the80B/81B decoder, rx_lpi_active is asserted by the PCS receive function and the LPI character iscontinuously asserted at the receive GMII. After the sleep frame the link partner begins transmitting zeros,and it is recommended that the receiver power down receive circuits to reduce power consumption. Thereceive function uses PHY frame counters to maintain synchronization with the remote PHY and receivesperiodic refresh signals that are used to update coefficients, so that the integrity of adaptive filters and timing





loops in the PMA is maintained. LPI signaling is defined in 97.3.5. The quiet-refresh cycle continues untilthe PHY detects the wake frame. The PHY receive function sends Idles to the GMII for the remainder of thewake frame and then resumes normal power mode operation.

97.3.2.3.1 Frame and block synchronization

When operating in the data mode, the receiving PCS shall form a PAM3 stream from thePMA_UNITDATA.indication primitive by concatenating requests in order from rx_data<0> torx_data<2699> (see Figure 97–6). It obtains block lock to the PHY frames during the PAM2 training patternusing synchronization bits provided in the training sequence.

97.3.2.3.2 PCS descrambler

The descrambler processes the payload to reverse the effect of the scrambler using the same polynomial.The PCS descrambles the data stream and returns the proper sequence of symbols to the decoding processfor generation of RXD<7:0> to the GMII. For side-stream descrambling, the MASTER PHY shall employthe receiver descrambler generator polynomial per Equation (97–4) and the SLAVE PHY shall employ thereceiver descrambler generator polynomial per Equation (97–3).

97.3.2.3.3 Valid and invalid blocks

An 80B/81B block is invalid if any of the following conditions exists:

a) The block contains an invalid pointer

b) Any control character contains a value not in Table 97–1

c) The PHY frame containing this 80B/81B block is uncorrectable

Invalid blocks are replaced with Error.

97.3.3 Test-pattern generators

The test-pattern generator mode is provided for enabling joint testing of the local transmitter, the channeland remote receiver. When the transmit PCS is operating in test-pattern mode it shall transmit continuouslyas illustrated in Figure 97–5, with the input to the RS-FEC encoder set to zero and the initial condition of thescrambler set to any non-zero value. This has the same effect as setting the input to the scrambler to zero.When the receiver PCS is operating in test-pattern mode it shall receive continuously as illustrated inFigure 97–6. The output of the received descrambled values should be zero. Any nonzero values correspondto receiver bit errors. The output of the RS-FEC decoder should also be zero, however there is the possibilitythat the RS-FEC decoder may have corrected some errors. This mode is further described as test mode 7 in97.5.2.

97.3.4 PMA training side-stream scrambler polynomials

The PCS Transmit function employs side-stream scrambling. If the parameter config provided to the PCS bythe PMA PHY Control function via the PMA_CONFIG.indication message assumes the value MASTER,PCS Transmit shall employ Equation (97–5)

(97–5)

as transmitter side-stream scrambler generator polynomial. If the PMA_CONFIG.indication messageassumes the value of SLAVE, PCS Transmit shall employ Equation (97–6)

(97–6)

gM x 1 x13 x+ 33+=

gS x 1 x20 x33+ +=





as transmitter side-stream scrambler generator polynomial. An implementation of MASTER and SLAVEPHY side-stream scramblers by linear-feedback shift registers is shown in Figure 97–9. The bits stored inthe shift register delay line at time n are denoted by Scrn[32:0]. At each symbol period, the shift register isadvanced by one bit, and one new bit represented by Scrn[0] is generated. The transmitter side-streamscrambler is reset upon execution of the PCS Reset function. If PCS Reset is executed, all bits of the 33-bitvector representing the side-stream scrambler state are arbitrarily set. The initialization of the scrambler stateis left to the implementer. In no case shall the scrambler state be initialized to all zeros.

97.3.4.1 Generation of Sn

During PMA training, the training pattern is embedded with indicators to establish alignment to the RS-FECblock and the 15 partial PHY frames that comprise the block. The last partial PHY frame is embedded withan information field used to exchange messages between link partners. PMA training signal encoding isbased on the generation, at time n, of the bit Sn. The first bit is inverted in the first 14 partial PHY frames ofeach RS-FEC block. The first 96 bits of the 15th partial PHY frame is XORed with the contents of theInfoField. Each partial PHY frame is 180 bits long, beginning at Sn where (n mod 180) = 0. See Equation (97–7).

(97–7)

97.3.4.2 Generation of symbol Tn

The bit Sn is mapped to the transmit symbol Tn as follows: if Sn = 0 then Tn = +1, if Sn = 1 then Tn = –1.

97.3.4.3 PMA training mode descrambler polynomials

The PHY shall acquire descrambler state synchronization to the PAM2 training sequence and report successthrough scr_status. For side-stream descrambling, the MASTER PHY employs the receiver descramblergenerator polynomial per Equation (97–6) and the SLAVE PHY employs the receiver descrambler generatorpolynomial per Equation (97–5).

Figure 97–10—Realization of side-stream scramblers by linear feedback shift registers

T

+

Side-stream scrambler employed by the MASTER PHY Transmit

T

Scrn[0] Scrn[1]

T

Scrn[12]

T

Scrn[13]

T

Scrn[31]

T

Scrn[32]

Side-stream scrambler employed by the SLAVE PHY Transmit

T

+

T

Scrn[0] Scrn[1]

T

Scrn[19]

T

Scrn[20]

T

Scrn[31]

T

Scrn[32]

Sn

Scrn 0 InfoField n mod 180 2520 n mod 2700 2615

Scrn 0 1 else if n mod 180 0=

Scrn 0 otherwise

=





97.3.5 LPI signaling

PHYs with EEE capability have transmit and receive functions that can enter and leave the LPI modeindependently. The PHY can transition to the LPI mode when the PHY has successfully completed training.The transmit function of the PHY initiates a transition to the LPI transmit mode when it generates a sleepsignal composed of 80B/81B blocks containing only LPI control characters, as described in 97.3.2.2.15.When the transmitter begins to send the sleep signal, it asserts tx_lpi_active and the transmit function entersthe LPI transmit mode.

Within the LPI mode PHYs use a repeating quiet-refresh cycle (see Figure 97–11). The first part of thiscycle is known as the quiet period and lasts for a time lpi_quiet_time equal to 354 partial PHY frameperiods. The quiet period is defined in 97.3.5.2. The second part of this cycle is known as the refresh periodand lasts for a time lpi_refresh_time equal to 6 partial PHY frame periods. The refresh period is defined in97.3.5.3. A cycle composed of one quiet period and one refresh period is known as an LPI cycle and lasts foran lpi_qr_time equal to 24 × 15 = 360 partial PHY frame periods.

lpi_offset, lpi_quiet_time, lpi_refresh_time, and lpi_qr_time are timing parameters that are integer multiplesof the partial PHY frame period. lpi_offset is a fixed value equal to lpi_qr_time/2 + 15. It is used to ensurerefresh signals and wake start times are appropriately offset by the link partners.

PHYs begin the transition from the LPI receive mode when they detect the wake frame.

97.3.5.1 LPI Synchronization

To maximize power savings, maintain link integrity, and ensure interoperability, EEE-capable PHYs shallsynchronize refresh intervals during the LPI mode. The quiet-refresh cycle is established from the Masterpartial PHY frame Count (PFC24) during PMA Training. At the MASTER, partial PHY frame zero and allmultiples of 360 partial PHY frames thereafter denote the start of the cycle.

An EEE-capable PHY in SLAVE mode is responsible for synchronizing its partial PHY frame count to theMASTER’s partial PHY frame count during link up. The SLAVE shall ensure that its partial PHY framecount is synchronized to the MASTER’s partial PHY frames within 1 partial PHY frame. The start of theSLAVE quiet-refresh cycle is delayed from the MASTER by 13 PHY frames (195 partial PHY frames).This offset ensures that the MASTER and SLAVE wake/sense windows are offset from each other and thatthe refresh periods are nearly a half cycle offset.

Following the transition to PAM3, the PCS continues to count transmitted partial PHY frames (tx_pfc), anduses the counter to generate refresh and wake control signals for the transmit functions.

Figure 97–11—LPI signal timing

0 30 60 90 120 150 180 240 270 300 330 360210

15 45 75 105 135 165 195 225 255 285 315 345

354Master

ValidWakeStarts

Slave

Refresh

lpi_refresh_time

195

ValidWakeStarts

PHY frame boundaries occur where module (tx_pfc, 15) == 0

lpi_quiet_time

lpi_qr_time

lpi_offset





Wake frames may be sent at the beginning of every second PHY frame boundary starting at the beginning ofthe refresh PHY frame. This sets wake_period to 30 partial PHY frames. The MASTER and SLAVEallowable wake positions do not overlap. The wake frame may start in the same PHY frame as a plannedrefresh and obviate this refresh.

The MASTER and SLAVE shall derive the tx_refresh_active and tx_wake_start signals from thetransmitted partial PHY frames (tx_pfc) as shown in Table 97–3 and Table 97–4.

97.3.5.2 Quiet period signaling

During the quiet period the transmitter shall put PAM3 symbol zero on to the MDI. During the quiet periodthe transmitter may be turned off to save power.

97.3.5.3 Refresh period signaling

During the LPI mode 1000BASE-T1 PHYs use staggered, out-of-phase refresh signaling to maximizepower savings. PAM3 refresh symbols are generated from the output of the data mode PCS side-streamscrambler polynomials described in 97.3.2.2.12 with PCS transmit data masked to zero. The scramblers runcontinuously regardless of the transmit mode. The refresh occupies the last 6 partial PHY frames of wherethe PHY frame would occur if it were transmitted.

The 1000BASE-T1 OAM symbols and the RS parity symbols are XORed with the scrambler stream at thesame relative position to the RS boundaries as they occupy during normal mode. The parity is generatedusing Equation (97–2) with D405 ... D1 = 0 and D0 = OAM.

97.3.6 Detailed functions and state diagrams

97.3.6.1 State diagram conventions

The body of this subclause is comprised of state diagrams, including the associated definitions of constants,variables, functions, counters, and messages. Should there be a discrepancy between a state diagram anddescriptive text, the state diagram prevails.

The notation used in the state diagrams follows the conventions of 21.5. The notation ++ after a counter orinteger variable indicates that its value is to be incremented.

Table 97–3—Synchronization logic derived from SLAVE signal partial PHY frame count

Slave-side Variable u = tx_pfc

tx_refresh_active=true lpi_offset – lpi_refresh_time mod(u, lpi_qr_time) < lpi_offset

tx_wake_start=true mod(u, wake_period) = 0

Table 97–4—Synchronization logic derived from MASTER signal partial PHY frame count

Master-side variable v = tx_pfc

tx_refresh_active=true mod(v, lpi_qr_time) lpi_quiet_time

tx_wake_start=true mod(v, wake_period) = wake_period/2





97.3.6.2 State diagram parameters

97.3.6.2.1 Constants

EBLOCK_R<99:0>TYPE: bit vector100-bit vector to be sent to the GMII containing symbol errors in all 10 character locations.

IBLOCK_R<99:0>TYPE: bit vector100-bit vector to be sent to the GMII containing idles in all 10 character locations.

IBLOCK_T<99:0>TYPE: bit vector100-bit vector to be sent to the encoder containing idles in all 10 character locations.

LPBLOCK_R<99:0>TYPE: bit vector100-bit vector to be sent to the GMII containing LP_IDLEs in all 10 character locations.

LPBLOCK_T<99:0>TYPE: bit vector100-bit vector to be sent to the encoder containing LP_IDLEs in all 10 character locations.

RFER_CNT_LIMITTYPE: IntegerVALUE: 16Number of Reed-Solomon frames with uncorrectable errors.

RFRX_CNT_LIMITTYPE: IntegerVALUE: 88Number of Reed-Solomon frames received over bit error rate interval.

ZBLOCK_T<80:0>TYPE: bit vector81-bit vector containing all zero bits.

97.3.6.2.2 Variables

RFER_test_lfBoolean variable that is set true when a new PHY frame is available for testing and false whenRFER_TEST_LF state is entered. A new PHY frame is available for testing when the Block Syncprocess has accumulated enough symbols from the PMA to evaluate the next PHY frame.

block_lockBoolean variable that is set true when receiver acquires block delineation.

hi_rferBoolean variable that is asserted true when the rfer_cnt reaches RFER_CNT_LIMIT indicating a

bit error ratio > 4 10–4.





pcs_resetWhen this variable is set to ON, all PCS functions are reset. Otherwise, this variable holds thevalue of OFF. This variable is set by the PCS Reset function.

rx_coded<81:0>Vector containing the input to the 80B/81B decoder including a block valid flag. The format forrx_coded<80:0> is shown in Figure 97–6. The leftmost bit in the figure is rx_coded<0> and therightmost bit is rx_coded<80>. rx_coded<81> (not shown in the figure) is set to 1 if all paritychecks of the Reed-Solomon frame are satisfied, otherwise it is set to 0.

rf_valid Boolean indication that is set true if received Reed-Solomon frame is valid. The frame is valid if allparity checks of the coded bits are satisfied.

rx_lpi_activeThis variable is set true upon detection of LP_IDLE. Set false upon detection of a wake frame.

rx_raw<99:0> Vector containing 10 successive GMII output transfers. Each transfer is numbered from 0 to 9 withthe first transfer numbered as the 0th transfer. The nth GMII transfer is labeled as RX_DV[n],RX_ER[n], RXD[n]<7:0>. For n = 0 to 9, RX_DV[n] = rx_raw<10n>, RX_ER[n] = rx_raw<10n+1>, RXD[n]<7:0> = rx_raw<10n+9:10n+2>

rx_wake_frame_completeThis variable is set true at end of WAKE PHY frame, otherwise false.

tx_coded<80:0>Vector containing the output from the 80B/81B encoder. The format for this vector is shown inFigure 97–5. The leftmost bit in the figure is tx_coded<0> and the rightmost bit is tx_coded<80>.

tx_data_mode Set true when tx_mode = SEND_N, otherwise false.

tx_lpi_activeThis variable is set false at the next wake frame window if any of the following conditions is true:

— a non-LP_IDLE is detected on GMII in any block

— the PHY receives SNR<1:0> set to 01 by its link partner

— the PHY transmits SNR<1:0> set to 01 to its link partner as defined in 97.3.8.2.14

This variable is set true on next PHY frame if all of the following conditions are true:

— an LP_IDLE detected on GMII during the entire last 80B/81B block

— the PHY does not receive SNR<1:0> set to 01 by its link partner

— the PHY does not transmit SNR<1:0> set to 01 to its link partner as defined in 97.3.8.2.14

tx_raw<99:0> Vector containing 10 successive GMII transfers. Each transfer is numbered from 0 to 9 with thefirst transfer numbered as the 0th transfer. The nth GMII transfer is labeled as TX_EN[n],TX_ER[n], TXD[n]<7:0>.For n = 0 to 9, tx_raw<10n> = TX_EN[n], tx_raw<10n+1> = TX_ER[n], tx_raw<10n+9:10n+2> = TXD[n]<7:0>





tx_sleep_frame_completeThis variable is set to true when PHY is transitioning to the LPI mode and the sleep signal trans-mission is completed. This variable is set to false when the PHY is transitioning out of the LPImode.

tx_wake_frame_complete This variable is set to true at the end of a complete wake frame. This variable is set to falseotherwise.

lpi_tx_mode A variable indicating the signaling to be used from the PCS to the PMA across the PMA_UNIT-DATA.request(tx_symb) interface. lpi_tx_mode controls tx_symb only when tx_mode is set to SEND_N.The variable is set to NORMAL when !tx_lpi_active, indicating that the PCS is in the normalpower mode of operation.The variable is set to REFRESH when (tx_lpi_active * tx_refresh active).The variable is set to QUIET when (tx_lpi_active * !tx_refresh active).

97.3.6.2.3 Functions

DECODE(rx_coded<81:0>) In the PCS Receive process, this function takes as its argument 82-bit rx_coded<81:0> from theReed-Solomon decoder and descrambler. If rx_coded<81> = 1 then the decoder decodes the 81B-Reed-Solomon bit vector rx_coded<80:0> returning a vector rx_raw<99:0>, which is sent to theGMII. The DECODE function shall decode the block based on code specified in 97.3.2.2.2. Ifrx_coded<81> = 0 then the decoder returns EBLOCK_R.

ENCODE(tx_raw<99:0>) Encodes the 100-bit vector received from the GMII, returning 81-bit vector tx_coded. TheENCODE function shall encode the block as specified in 97.3.2.2.2. The ENCODE function shallonly encode LPI_IDLE while in the SEND_LPI state. Otherwise LPI_IDLE is converted to Idle inthe ENCODE function.

97.3.6.2.4 Counters

rfer_cnt Count up to a maximum of RFER_CNT_LIMIT of the number of invalid Reed-Solomon frameswithin the current RFRX_CNT_LIMIT Reed-Solomon frame period.

rfrx_cnt Count number Reed-Solomon frames received during current period.

97.3.6.3 Messages

PCS_status Indicates whether the PCS is in a fully operational state. (See 97.3.7.1.)

PMA_UNITDATA.indication(rx_symb)A signal sent by PMA Receive indicating that a PAM3 symbol is available in rx_symb.

PMA_UNITDATA.request(tx_symb)A signal sent to PMA Transmit indicating that a PAM3 symbol is available in tx_symb.





RX_AGGREGATE A signal sent to PCS Receive indicating that nine aligned 9-bit Reed-Solomon symbols areaggregated in rx_coded. This signal is asserted even when the receiver is in low power idle mode atthe time when the nine 9-bit RS-FEC symbols would be aggregated in rx_coded if the receiver wasoperating in non-lpi mode.

RX_FRAME A signal sent to PCS Receive indicating that a full Reed-Solomon frame has been decoded and thevariable rf_valid is updated.

TX_AGGREGATE A signal sent to PCS Transmit indicating that 10 GMII transfers are aggregated in tx_raw<99:0>.

97.3.6.4 State diagrams

The RFER Monitor state diagram shown in Figure 97–13 monitors the received signal for high PHY frameerror ratio. The 80B/81B Transmit state diagram shown in Figure 97–14 controls the encoding of 81Btransmitted blocks. It makes exactly one transition for each 81B transmit block processed. The 80B/81BReceive state diagram shown in Figure 97–12 controls the decoding of 81B received blocks. It makesexactly one transition for each receive block processed. The PCS shall perform the functions of PCSReceive, RFER monitor, and PCS Transmit, as specified in Figure 97–12, Figure 97–13, and Figure 97–14,respectively.





RECEIVE_DATA

rx_raw DECODE(rx_coded<81:0>)

RECEIVE_INIT

rx_raw IBLOCK_R

pcs_reset = ON+ hi_rfer

+ !block_lock

RECEIVE_LPI

rx_raw LPBLOCK_R

RECEIVE_WAKE

rx_raw IBLOCK_R

RX_AGGREGATE* !rx_lpi_active

RX

_A

GG

RE

GA

TE

* rx_lpi_active

RX

_AG

GR

EG

AT

E* !rx_

lpi_active

RX_AGGREGATE * rx_lpi_active

RX_AGGREGATE *rx_wake_frame_complete

RX_AGGREGATE

Note—Transitions inside dashed boxes are only required for the EEE capability.

Figure 97–12—PCS Receive state diagram





Figure 97–13—RFER monitor state diagram

INIT_CNT

rfer_cnt 0rfrx_cnt 0

UCT

RFER_MT_INIT

hi_rfer false

pcs_reset = ON+ !block_lock+ rx_lpi_active

WAIT

UCT

INC_CNT

rfrx_cnt++

RX_FRAME

RFER_BAD_RF

rfer_cnt++

!rf_valid

rfer_cnt =RFER_CNT_LIMIT

rfer_cnt < RFER_CNT_LIMIT *rfrx_cnt < RFRX_CNT_LIMIT

rf_valid *rfrx_cnt < RFRX_CNT_LIMIT

HI_RFER

hi_rfer true

INC_CNT2

rfrx_cnt++

RX_FRAME *rfrx_cnt < RFRX_CNT_LIMIT

GOOD_RFER

hi_rfer false

rf_valid *rfrx_cnt = RFRX_CNT_LIMIT

UCTrfrx_cnt = RFRX_CNT_LIMIT

rfer_cnt < RFER_CNT_LIMIT *rfrx_cnt = RFRX_CNT_LIMIT





Figure 97–14—PCS Transmit state diagram

SEND_IDLES

tx_coded ENCODE(IBLOCK_T)

DISABLE_TRANSMITTER

pcs_reset = ON

SEND_DATA

tx_coded ENCODE(tx_raw<99:0>)

SEND_ENTER_LPI

tx_coded ENCODE(LPBLOCK_T)

SEND_LPI

tx_coded ZBLOCK_T

SEND_WAKE

tx_coded ENCODE(IBLOCK_T)

TX_AGGREGATE *tx_data_mode

TX_AGGREGATE *tx_data_mode *tx_lpi_active

TX_AGGREGATE *tx_data_mode *tx_lpi_active * tx_sleep_frame_complete

TX_AGGREGATE *tx_data_mode *!tx_lpi_active

TX_A

GG

RE

GATE

*!tx_data_m

ode

TX_A

GG

RE

GATE

*!tx_data_m

odeTX

_AG

GR

EG

ATE *

tx_data_mode *

!txlpi_active

TX_A

GG

RE

GATE

*tx_data_m

ode * tx_lpi_active

TX_A

GG

RE

GATE

*tx_data_m

ode * !tx_lpi_active

TX_A

GG

RE

GATE

*tx_data_m

ode * tx_wake_fram

e_complete

TX_AGGREGATE *

TX_AGGREGATE

!tx_data_mode

TX_AGGREGATE *!tx_data_mode

TX_AGGREGATE *!tx_data_mode

Note—Transitions inside dashed boxes are only required for the EEE capability.





97.3.7 PCS management

The following objects apply to PCS management. If an MDIO Interface is provided (see Clause 45), they areaccessed via that interface. If not, it is recommended that an equivalent access be provided.

97.3.7.1 Status

PCS_status: Indicates whether the PCS is in a fully operational state. It is only true if block_lock is true andhi_rfer is false. This status is reflected in MDIO register 3.2306.10. A latch low view of this statusis reflected in MDIO register 3.2305.2 and the inverse of this status is reflected in MDIO register3.2305.7.

block_lock: Indicates the state of the block_lock variable. This status is reflected in MDIO register 3.2306.8. Alatch low view of this status is reflected in MDIO register 3.2306.6.

hi_rfer: Indicates the state of the hi_rfer variable. This status is reflected in MDIO register 3.2306.9. Alatch high view of this status is reflected in MDIO register 3.2306.7.

Rx LPI indication: For EEE capability, this variable indicates the current state of the receive LPI function. This flag isset to true (register bit set to one) when the PCS Receive state diagram (Figure 97–12) is in theRECEIVE_LPI or RECEIVE_WAKE states. This status is reflected in MDIO register 3.2305.8. Alatch high view of this status is reflected in MDIO register 3.2305.10 (Rx LPI received).

Tx LPI indication:For EEE capability, this variable indicates the current state of the transmit LPI function. This flagis set to true (register bit set to one) when the PCS Transmit state diagram (Figure 97–14) is in theSEND_LPI or SEND_WAKE states. This status is reflected in MDIO register 3.2305.9. A latchhigh view of this status is reflected in MDIO register 3.2305.11 (Tx LPI received).

97.3.7.2 Counter

The following counter is reset to zero upon read and upon reset of the PCS. When it reaches all ones, it stopscounting. Its purpose is to help monitor the quality of the link.

RFER_count:6-bit counter that counts each time RFER_BAD_RF of the RFER monitor state diagram (seeFigure 97–13) is entered. This counter is reflected in MDIO register bits 3.2306.5:0. The counter isreset when register 3.2306 is read by management. Note that this counter counts a maximum ofRFER_CNT_LIMIT counts per RFRX_CNT_LIMIT period since the RFER_BAD_RF state canbe entered a maximum of RFER_CNT_LIMIT times per RFRX_CNT_LIMIT window.

97.3.7.3 Loopback

The PCS shall be placed in loopback mode when the loopback bit in MDIO register 3.2304.14 is set to a one.In this mode, the PCS shall accept data on the transmit path from the GMII and return it on the receive pathto the GMII. In addition, the PCS shall transmit a continuous stream of GMII data to the 81B encoder and onfurther to the PMA sublayer and shall ignore all data presented to it by the PMA sublayer.





97.3.8 1000BASE-T1 Operations, Administration, and Maintenance (OAM)

The 1000BASE-T1 PCS level Operations, Administration, and Maintenance (OAM) provides an optionalmechanism useful for monitoring link operation such as exchanging PHY link health status and messageexchange. The 1000BASE-T1 OAM information is exchanged in-band between two PHYs using excessbandwidth available on the link. The 1000BASE-T1 OAM is strictly between two 1000BASE-T1 PHYs onthe physical layer and their associated management entities if present. Passing 1000BASE-T1 OAMinformation to other layers is outside the scope of this standard.

1000BASE-T1 OAM is operational as long as both PHYs implement this mechanism and link is up. Itcontinues to be operational during low power idle albeit the information is transferred at a slower rate duringthe refresh cycle.

The 1000BASE-T1 OAM frame data is carried in the OAM9 field described in 97.3.2.2.4 for the normalpower data mode and 97.3.5.3 for low power mode. This 9-bit field is used to exchange 1000BASE-T1OAM frames. The implementation of 1000BASE-T1 OAM frame exchange function is optional. However,if 1000BASE-T1 EEE is implemented, then the 1000BASE-T1 OAM frame exchange function isimplemented to exchange, at a minimum, the link partner health status.

For the remainder of this subclause, the term 1000BASE-T1 OAM is specific to the 1000BASE-T1 PCSlevel OAM.

97.3.8.1 Definitions

1000BASE-T1 OAM frame: A frame consisting of 12 octets of data with 12 parity bits.

1000BASE-T1 OAM symbol: A 9-bit symbol consisting of one data octet plus a parity bit. Twelve1000BASE-T1 OAM symbols make up an 1000BASE-T1 OAM frame.

1000BASE-T1 OAM field: The OAM9 field in each PHY frame as described in 97.3.2.2.11 or in eachrefresh cycle as described in 97.3.5.3.

1000BASE-T1 OAM message: A message contains a 4-bit message number plus 8 octets of message dataembedded in an 1000BASE-T1 OAM frame. The same 1000BASE-T1 OAM message can be repeated onmultiple 1000BASE-T1 OAM frames.

97.3.8.2 Functional specifications

97.3.8.2.1 1000BASE-T1 OAM Frame Structure

Each 1000BASE-T1 OAM frame is made up of 12 octets of data and 12 parity bits. Each symbol consists of8 bits of data and one parity bit. The parity bit value for symbol 0 should be such that the sum of the numberof 1s in the nine bits is even. The parity bit value for symbols 1 to 11 should be such that the sum of thenumber of 1s in the nine bits is odd.





One 1000BASE-T1 OAM symbol is placed in the 9-bit 1000BASE-T1 OAM field in each PHY frameduring normal power operation in the data mode. One 1000BASE-T1 OAM symbol is placed in the 9-bit1000BASE-T1 OAM field in each refresh cycle during low power idle. The 12 1000BASE-T1 OAMsymbols are consecutively inserted into 12 consecutive PHY frames and/or refresh cycles. Once the 12symbols of the current 1000BASE-T1 OAM frame are inserted, the 12 symbols of the next 1000BASE-T1OAM frame are inserted. This process is continuous without any break in the insertion of 1000BASE-T1OAM symbols.

Bit 0 of each 1000BASE-T1 OAM symbol is the first bit transmitted in the 9-bit 1000BASE-T1 OAM field.Symbol 0 is the first symbol transmitted in each 1000BASE-T1 OAM frame.

The 1000BASE-T1 OAM frame boundary can be found at the receiver by determining the symbol parity.Symbol 0 has even parity while all other symbols have odd parity.

If 1000BASE-T1 OAM is not implemented then the 9-bit 1000BASE-T1 OAM field shall be set to all 0s. Ifthe link partner does not implement 1000BASE-T1 OAM, the 9-bit 1000BASE-T1 OAM field will remainstatic and the symbol parity will not change.

97.3.8.2.2 1000BASE-T1 OAM Frame Data

The 1000BASE-T1 OAM frame data is shown in Figure 97–15. OAM<x><y> refers to symbol x, bit y ofthe 1000BASE-T1 OAM frame. Reserved fields shall be set to 0.

97.3.8.2.3 Ping RX

The Ping RX is indicated in OAM<0><3>.

This bit is set by the PHY to the same value as the Ping TX bit received from the link partner.

97.3.8.2.4 Ping TX

The Ping TX is indicated in OAM<0><2>.

Figure 97–15—OAM Frame

EvenParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

ParityOdd

Parity

Reserved Reserved Reserved Reserved

ToggleValid Ack TogAck Message_Number<3:0>

PingRx PingTx SNR<1> SNR<0>

Message<0><7:0>

Message<1><7:0>

Message<2><7:0>

Message<3><7:0>

Message<4><7:0>

Message<5><7:0>

Message<6><7:0>

Message<7><7:0>

CRC16

CRC16

Symbol 0

Symbol 1

Symbol 2

Symbol 3

Symbol 4

Symbol 5

Symbol 6

Symbol 7

Symbol 8

Symbol 9

Symbol 10

Symbol 11

D8 D7 D6 D5 D4 D3 D2 D1 D0

first bit

final bit





This bit is set by the PHY to for the link partner to echo on Ping RX.

97.3.8.2.5 PHY Health

The PHY Health (SNR<1:0>) is indicated in OAM<0><1:0>.

This status is set by the PHY to indicate the status of the receiver. The definitions of good, marginal, when torequest idles, and when to request retrain are implementation dependent.

— 00: PHY link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current1000BASE-T1 OAM frame

— 01: LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPI and send idles(used only when EEE is enabled)

— 10: PHY SNR is marginal

— 11: PHY SNR is good

97.3.8.2.6 1000BASE-T1 OAM Message Valid

The 1000BASE-T1 OAM message valid (Valid) is indicated in OAM<1><7>.

— 0: Current 1000BASE-T1 OAM frame does not contain a valid 1000BASE-T1 OAM message

— 1: Current 1000BASE-T1 OAM frame contains a valid 1000BASE-T1 OAM message

97.3.8.2.7 1000BASE-T1 OAM Message Toggle

The 1000BASE-T1 OAM message toggle (Toggle) is indicated in OAM<1><6>.

The toggle bit is used to ensure proper 1000BASE-T1 OAM message synchronization between the PHY andthe link partner. The toggle bit in the current 1000BASE-T1 OAM message is set to the opposite value of thetoggle bit in the previous 1000BASE-T1 OAM message only if link partner acknowledge the 1000BASE-T1OAM message is received. This allows one 1000BASE-T1 OAM message to be delineated from a second1000BASE-T1 OAM message since the same 1000BASE-T1 OAM message may be repeated over multiple1000BASE-T1 OAM frames. This bit is valid only if Valid is set to 1.

97.3.8.2.8 1000BASE-T1 OAM Message Acknowledge

The 1000BASE-T1 OAM message Acknowledge (Ack) is indicated in OAM<1><5>.

Ack is set by the PHY to let the link partner know that the 1000BASE-T1 OAM message sent by the linkpartner was successfully received as defined in 97.3.8.2.13 and the PHY is ready to accept a new1000BASE-T1 OAM message. An 1000BASE-T1 OAM message is defined to be Message_Number<3:0>and Message<7:0><7:0>.

— 0: No Acknowledge

— 1: Acknowledge

97.3.8.2.9 1000BASE-T1 OAM Message Toggle Acknowledge

The 1000BASE-T1 OAM message Toggle Acknowledge (TogAck) is indicated in OAM<1><4>.

TogAck is set by the PHY to let the link partner know which the 1000BASE-T1 OAM message is beingacknowledged. TogAck takes the value of Toggle bit of the 1000BASE-T1 OAM message beingacknowledged. This bit is valid only if Ack is set to 1.





97.3.8.2.10 1000BASE-T1 OAM Message Number

The 1000BASE-T1 OAM message number is indicated in OAM<1><3:0>.

This field is user-defined but is recommended that it be used to indicate the meaning of the 8-octet messagethat follows. If used this way, up to 16 different 8-octet messages can be exchanged.

The message number is user-defined and its definition is outside the scope of this standard.

97.3.8.2.11 1000BASE-T1 OAM Message Data

The 1000BASE-T1 OAM message data is indicated in OAM<9:2><7:0>.

The 8-octet message data is user-defined and its definition is outside the scope of this standard.

Ack is set by the PHY to let the link partner know that the 1000BASE-T1 OAM frame sent by the linkpartner is successfully received as defined The 1000BASE-T1 OAM frame octet is the lower 8 bits of the9-bit 1000BASE-T1 OAM symbol. Twelve octets form the 1000BASE-T1 OAM data.

97.3.8.2.12 CRC16

The CRC16 is indicated in OAM<11:10><7:0>.

The CRC16 implements the polynomial (x+1)(x15+x+1) of the previous 10 octets. The CRC16 shall producethe same result as the implementation shown in Figure 97–16. The 16 delay elements S0,..., S15, shall beinitialized to zero. Afterwards OEM<9:0><7:0> presented in their transmitted order as described in97.3.8.2.1 are used to compute the CRC16 with the switch connected, which is setting CRC gen in Figure 97–16.Note that the parity bit is not used in the CRC16 calculation. After all the 10 octets have been processed, theswitch is disconnected (setting CRC out) and the 16 values stored in the delay elements are transmitted inthe order illustrated, first S15, followed by S14, and so on, until the final value S0. S15 is indicated inOAM<10><0> and S0 is indicated in OAM<11><7>.

97.3.8.2.13 1000BASE-T1 OAM Frame Acceptance Criteria

All fields of the 1000BASE-T1 OAM frame shall be accepted and updated, unless any of the followingoccurs:

a) Incorrect parity on any of the 12 symbols

b) Incorrect CRC16

c) Uncorrectable PHY frame on any of the 12 symbols

Figure 97–16—1000BASE-T1 OAM CRC16

+S0 S1 S2 S14 + S15CRC16 output

+

Data In

CRC gen

CRC out





97.3.8.2.14 PHY Health Indicator

The PHY current health is sent to the link partner on a per 1000BASE-T1 OAM frame basis using theSNR<1:0> bits as described in 97.3.8.2.5. It lets the link partner have an early indication of potentialproblems that may cause the PHY to drop link or have high error rates.

If EEE is implemented, there may be a case where a PHY’s receiver can no longer maintain good SNRbased on quiet/refresh cycles. Instead of dropping the link, the PHY can attempt to recover the link byforcing the link partner to exit LPI in its egress direction so that the PHY can use normal power mode torecover. This is done by transmitting SNR<1:0> with a value of 01.

If a PHY receives SNR<1:0> set to 01 by its link partner, then it cannot enter into LPI in the egressdirection. If the PHY is already in LPI then the PHY shall immediately exit LPI.

97.3.8.2.15 Ping

The PingTx bit is set based on the value in mr_tx_ping. The PingRx bit is set based on the latest PingTxreceived from the link partner. The value in mr_rx_ping is set based on the received PingRx from the linkpartner. The user can determine that the link partner 1000BASE-T1 OAM is operating properly by toggingmr_tx_ping and observing mr_rx_ping matches after a short delay.

The Ping bits are updated on a per 1000BASE-T1 OAM frame basis.

97.3.8.2.16 1000BASE-T1 OAM Message Exchange

Unlike the PHY health indicator and the ping function that operate on a per 1000BASE-T1 OAM framebasis, the 1000BASE-T1 OAM message exchange operates on a per 1000BASE-T1 OAM message basisthat will occur over many 1000BASE-T1 OAM frames. The 1000BASE-T1 OAM message exchangemechanism allows a management entity attached to a PHY and its peer attached to the link partner toasynchronously pass 1000BASE-T1 OAM messages and verify their delivery.

The 1000BASE-T1 OAM message is first written into the 1000BASE-T1 OAM transmit registers in thePHY. The 1000BASE-T1 OAM message is then read out of the 1000BASE-T1 OAM transmit registers andtransmitted to the link partner. After the link partner receives the 1000BASE-T1 OAM message it transfersit into the link partner’s 1000BASE-T1 OAM receive registers and also sends an acknowledge back to thePHY indicating that the next 1000BASE-T1 OAM message can be transmitted. One 1000BASE-T1 OAMmessage can be loaded into the 1000BASE-T1 OAM transmit registers while another 1000BASE-T1 OAMmessage is being transmitted by the PHY to the link partner while yet another 1000BASE-T1 OAM messageis being read out at the link partner's 1000BASE-T1 OAM receive registers. The exchange of 1000BASE-T1OAM messages are occurring concurrently and bi-directionally.The transfers between the managemententities can be done asynchronously. On the transmit side mr_tx_valid = 0 indicates that the next1000BASE-T1 OAM message can be written into the 1000BASE-T1 OAM transmit registers. Once theregisters are written the management entity sets mr_tx_valid to 1 to indicate that the 1000BASE-T1 OAMtransmit registers contains a valid 1000BASE-T1 OAM message. Once the message is read out atomically,the state machine clears the mr_tx_valid to 0 to indicate that the registers are ready to accept the next1000BASE-T1 OAM message.

On the receive side mr_rx_lp_valid indicates that valid 1000BASE-T1 OAM message can be read from the1000BASE-T1 OAM receive registers. Once these registers are read, the mr_rx_lp_valid should be clearedto 0 to indicate that the registers are ready to receive the next 1000BASE-T1 OAM message. Ifmr_rx_lp_valid is not cleared then the 1000BASE-T1 OAM message transfer will eventually stall since thesender cannot send new 1000BASE-T1 OAM messages if the receiver does not acknowledge that an1000BASE-T1 OAM message has been transferred into the 1000BASE-T1 OAM receive registers.





The management entities can asynchronously read mr_tx_valid and mr_rx_lp_valid to know when1000BASE-T1 OAM messages can be transferred in and out of the 1000BASE-T1 OAM registers.

The toggle bit alternates between 0 and 1, which lets the management entity determine which 1000BASE-T1 OAM message is being referred to. The toggle bit transitioning rules between one 1000BASE-T1 OAMframe to the next 1000BASE-T1 OAM frame are shown in Table 97–5.

97.3.8.3 State diagram variable to 1000BASE-T1 OAM register mapping

The state diagrams of Figure 97–18 and Figure 97–17 generate and accept variables of the form “mr_x,”where x is an individual signal name. These variables comprise a management interface to communicate the1000BASE-T1 OAM information to and from the management entity. Clause 45 MDIO registers aredefined in MMD3 to support the 1000BASE-T1 OAM. The Clause 45 MDIO electrical interface is optional.Where no physical embodiment of the MDIO exists, provision of an equivalent mechanism to access theinformation is recommended. Table 97–6 describes the MDIO register to the state diagrams variablemapping.

Table 97–5—Toggle bit transition rules

Previous Valid

Previous Toggle

Current Valid

Current Toggle Description

0 0 0 0 No valid 1000BASE-T1 OAM message

0 0 0 1 Illegal transition (Error)

0 0 1 0 New 1000BASE-T1 OAM message starting



0 1 0 1 No valid 1000BASE-T1 OAM message


0 1 1 1 New 1000BASE-T1 OAM message starting


1 0 0 1 Received acknowledge, no new 1000BASE-T1 OAM message to send

1 0 1 0 Repeating current 1000BASE-T1 OAM message, waiting for link partner’s acknowledge

1 0 1 1 Previous 1000BASE-T1 OAM message ending, new 1000BASE-T1 OAM message starting

1 1 0 0 Received acknowledge, no new 1000BASE-T1 OAM message to send


1 1 1 0 Previous 1000BASE-T1 OAM message ending, new 1000BASE-T1 OAM message starting

1 1 1 1 Repeating current 1000BASE-T1 OAM message, waiting for link partner’s acknowledge





Table 97–6—State Variables to 1000BASE-T1 OAM Register Mapping

MDIO control/status variable PCS register nameRegister/bit

numberPCS control/status

variable

1000BASE-T1 OAM Message Valid

1000BASE-T1 OAM transmit register

3.2308.15 mr_tx_valid

Toggle Value 1000BASE-T1 OAM transmit register

3.2308.14 mr_tx_toggle

1000BASE-T1 OAM Message Received

1000BASE-T1 OAM transmit register

3.2308.13 mr_tx_received

Received Message Toggle Value 1000BASE-T1 OAM transmit register

3.2308.12 mr_tx_received_toggle

Message Number 1000BASE-T1 OAM transmit register

3.2308.11:8 mr_tx_message_num[3:0]

Ping Received 1000BASE-T1 OAM transmit register

3.2308.3 mr_rx_ping

Ping Transmit 1000BASE-T1 OAM transmit register

3.2308.2 mr_tx_ping

Local SNR 1000BASE-T1 OAM transmit register

3.2308.1:0 mr_tx_SNR[1:0]

1000BASE-T1 OAM Message 0 1000BASE-T1 OAM message register

3.2309.7:0 mr_tx_message[7:0]


3.2309.15:8 mr_tx_message[15:8]


3.2310.7:0 mr_tx_message[23:16]


3.2310.15:8 mr_tx_message[31:24]


3.2311.7:0 mr_tx_message[39:32]


3.2311.15:8 mr_tx_message[47:40]


3.2312.7:0 mr_tx_message[55:48]


3.2312.15:8 mr_tx_message[63:56]

Link Partner 1000BASE-T1 OAM Message Valid

1000BASE-T1 OAM receive register

3.2313.15 mr_rx_lp_valid

Link Partner Toggle Value 1000BASE-T1 OAM receive register

3.2313.14 mr_rx_lp_toggle





97.3.8.4 Detailed functions and State Diagrams

97.3.8.4.1 State diagram conventions

The body of this subclause is comprised of state diagrams, including the associated definitions of variables,counters, and functions. Should there be a discrepancy between a state diagram and descriptive text, the statediagram prevails.

The notation used in the state diagrams follows the conventions of 21.5.

97.3.8.4.2 State diagram parameters

97.3.8.4.3 Variables

link_statusThe link_status parameter set by PMA Link Monitor and passed to the PCS via thePMA_LINK.indication primitive. This variable takes the values of OK or FAIL.

mr_rx_lp_message[63:0]Eight octet 1000BASE-T1 OAM message from the link partner. The value in this variable is validonly when mr_rx_lp_valid is 1.

Link Partner Message Number 1000BASE-T1 OAM receive register

3.2313.11:8 mr_rx_lp_message_-num[3:0]

Link Partner SNR 1000BASE-T1 OAM receive register

3.2313.1:0 mr_rx_lp_SNR[1:0]

Link Partner 1000BASE-T1 OAM Message 0

Link partner 1000BASE-T1 OAM message register

3.2314.7:0 mr_rx_lp_message[7:0]



3.2314.15:8 mr_rx_lp_message[15:8]



3.2315.7:0 mr_rx_lp_message[23:16]



3.2315.15:8 mr_rx_lp_message[31:24]



3.2316.7:0 mr_rx_lp_message[39:32]



3.2316.15:8 mr_rx_lp_message[47:40]



3.2317.7:0 mr_rx_lp_message[55:48]



3.2317.15:8 mr_rx_lp_message[63:56]

Table 97–6—State Variables to 1000BASE-T1 OAM Register Mapping (continued)

MDIO control/status variable PCS register name Register/bit number

PCS control/status variable





mr_rx_lp_message_num[3:0]Four bit message number from the link partner. The value in this variable is valid only whenmr_rx_lp_valid is 1.

mr_rx_lp_SNR[1:0]Link partner health status.Values:

00: PHY link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame

01: LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPIand send idles (used only when EEE is enabled).

10: PHY SNR is marginal11: PHY SNR is good

The threshold for the status is implementation dependent.

mr_rx_lp_toggleThe toggle bit value associated with the eight octet 1000BASE-T1 OAM message from the linkpartner.Values:

The toggle bit alternates between 0 and 1.

mr_rx_lp_validIndicates whether 1000BASE-T1 OAM message in mr_rx_lp_message[63:0],mr_rx_lp_message_num[3:0] and the toggle bit in mr_rx_lp_toggle is valid or not. This variableshould be cleared when mr_rx_lp_message[63:48] is read and is not explicitly shown in the statemachine. The clearing of this variable indicates to the state machine that the 1000BASE-T1 OAMmessage is read by the user and the state machine can proceed to load in the next 1000BASE-T1OAM message. Values:

0: invalid1: valid

mr_rx_pingEchoed ping value from the link partner.Values:

The value can be 0 or 1.

mr_tx_message[63:0]Eight octet 1000BASE-T1 OAM message transmitted by the local PHY. The value in this variableis valid only when mr_tx_valid is 1.

mr_tx_message_num[3:0]Four bit message number transmitted by the local PHY. The value in this variable is valid onlywhen mr_tx_valid is 1.

mr_tx_pingPing value transmitted by the local PHY.Values:


mr_tx_receivedIndicates whether the most recently transmitted 1000BASE-T1 OAM message with a toggle bitvalue of mr_tx_received_toggle was received, read, and acknowledged by the link partner. Thisvariable shall clear on read.





Values:0: 1000BASE-T1 OAM message not received and read by the link partner1: 1000BASE-T1 OAM message received by the link partner

mr_tx_received_toggleToggle bit value of the 1000BASE-T1 OAM message that was received, read, and most recentlyacknowledged by the link partner. This bit is valid only if mr_tx_received is 1.Values:


mr_tx_SNR[1:0]Status register indicating PHY health status.Values:

00: PHY link is failing and will drop link and relink within 2 to 4 ms after the end ofthe current 1000BASE-T1 OAM frame

01: LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPIand send idles (used only when EEE is enabled)


The threshold for the status is implementation dependent.

mr_tx_toggleThe toggle bit value associated with the eight octet 1000BASE-T1 OAM message transmitted bythe PHY. The value is automatically set by the state machine and cannot be set by the user. This bitshould be read and recorded prior to setting mr_tx_valid to 1.Values:


mr_tx_validIndicates whether 1000BASE-T1 OAM message in mr_tx_message[63:0] andmr_rx_lp_message_num[3:0] is valid or not. This register will be cleared by the state machine toindicate whether the next 1000BASE-T1 OAM message can be written into the registers. Values:

0: invalid1: valid

resetResetValues:

false: 1000BASE-T1 OAM circuit not in resettrue: 1000BASE-T1 OAM circuit is in reset

rx_ackAcknowledge from link partner in response to PHY’s 1000BASE-T1 OAM message. Values:

0: no acknowledge1: acknowledge

rx_ack_toggleThe toggle value corresponding to the PHY’s 1000BASE-T1 OAM message that the link partner isacknowledging. This value is valid only if the rx_ack is set to 1.Values:

The toggle bit can take on values of 0 or 1.





rx_boundaryThis variable is set to true whenever the receive data stream reaches the end of a Reed-Solomonframes during normal power operation in the data mode, or at the end of a received refresh cycleduring low power idle operation. This variable is set to false at other times.Values:

false: receive stream not at a boundary endtrue: receive stream at a boundary end

rx_exp_toggleThis variable holds the expected toggle value of the next 1000BASE-T1 OAM message. This isnormally the opposite value of the current toggle value, but shall reset on error conditions wheretwo back to back 1000BASE-T1 OAM messages separated by 1000BASE-T1 OAM frames with-out a valid message have the same toggle value.Values:

The toggle bit can take on values of 0 or 1.

rx_lp_ackAcknowledge from PHY in response to link partner’s 1000BASE-T1 OAM message. Indicateswhether valid 1000BASE-T1 OAM message from the link partner has been sampled into thePHY’s registers.Values:

0: no acknowledge / not sampled1: acknowledge / sampled

rx_lp_pingPing value received from the link partner that should be looped back.Values:


rx_lp_toggleThe toggle bit value in the previous 1000BASE-T1 OAM frame received from the link partner.Values:


rx_lp_validIndicates whether 1000BASE-T1 OAM message in previous 1000BASE-T1 OAM frame receivedfrom the link partner is valid or not.Values:

0: invalid1: valid

rx_oam_field<8:0>Nine bit 1000BASE-T1 OAM symbol extracted from a received Reed-Solomon frame during nor-mal power operation in the data mode, or from a received refresh cycle during low power idleoperation.

rx_oam<11 to 0><8:0>Raw 12 symbol 1000BASE-T1 OAM frame received from the link partner.





SNR[1:0]PHY health status.Values:

00: PHY link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame

01: LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPIand send idles (used only when EEE is enabled)


Both the status threshold and condition for generating this status are implementation dependent.

tx_boundaryThis variable is set to true whenever the transmit data stream reaches the start of a PHY frameduring normal power operation in the data mode, or at the start of a transmit refresh cycle duringlow power idle operation. This variable is set to false at other times.Values:

false: transmit stream not at a boundary endtrue: transmit stream at a boundary end

tx_oam_field<8:0>Nine bit 1000BASE-T1 OAM symbol inserted into a transmitted Reed-Solomon frame during nor-mal power operation in the data mode, or into a transmitted refresh cycle during low power idleoperation.

tx_oam<11 to 0><8:0>Raw 12 symbol 1000BASE-T1 OAM frame transmitted from the PHY.

tx_lp_readyIndicates whether the link partner is ready to receive the next 1000BASE-T1 OAM message fromthe PHY. If ready, then the PHY will load the next 1000BASE-T1 OAM message from the regis-ters and begin transmitting them.Values:

0: not ready1: ready

tx_toggleThe toggle bit value being send in the current 1000BASE-T1 OAM frame transmitted by the PHY.Values:


97.3.8.4.4 Counters

rx_cntA count of received 1000BASE-T1 OAM frames.Values:

The value can be any integer from 0 to 12, inclusive.

tx_cnt1000BASE-T1 OAM frame transmit symbol count.Values:

The value can be any integer from 0 to 12, inclusive.





97.3.8.4.5 Functions

CRC16(10 octets)This function outputs a 16-bit CRC value using 10-octet input as defined in 97.3.8.2.12.

CRC16_Check(12 octets)This function checks whether the 12-octet frame has the correct CRC16 as defined in 97.3.8.2.12.Values:

BAD: CRC16 check is badGOOD: CRC16 check is good

Parity(12 octets)This function outputs 12 parity bits, one for each of the 12 input octets. An even parity bit is outputfor the first octet, and odd parity bits are output for each of the remaining 11 octets.

Parity_Check(9-bit symbol)This function calculates the bit parity of the 9-bit symbol.Values:

Even: symbol has even parityOdd: symbol has odd parity





97.3.8.4.6 State Diagrams

Figure 97–17—Receive state diagram

RECEIVE INIT

rx_lp_valid 0rx_lp_toggle 0rx_lp_ping 0rx_lp_ack 0rx_ack 0rx_ack_toggle 0rx_exp_toggle 0rx_cnt 0mr_rx_lp_valid 0mr_rx_lp_toggle 0mr_rx_ping 0mr_rx_lp_SNR[1:0] 00mr_rx_lp_message_num[3:0] 0mr_rx_lp_message[63:0] 0

reset + (link_status = FAIL)

CHECK READ

if ((rx_lp_valid = 0) + (rx_lp_ack = 0))then

rx_exp_toggle rx_lp_togglerx_lp_ack 0

LOAD RECEIVE PAYLOAD

mr_rx_lp_SNR[1:0] rx_oam<0><1:0>rx_lp_ping rx_oam<0><2>mr_rx_ping rx_oam<0><3>rx_lp_valid rx_oam<1><7>rx_lp_toggle rx_oam<1><6>rx_ack rx_oam<1><5>rx_ack_toggle rx_oam<1><4>

if ((mr_rx_lp_valid = 0) * (rx_oam<1><7> = 1) *(rx_oam<1><6> = rx_exp_toggle)) thenmr_rx_lp_message_num[3:0] rx_oam<1><3:0>mr_rx_lp_message[8n+7:8n] rx_oam<n+2><7:0>

where n = 0 to 7mr_rx_lp_toggle rx_oam<1><6>mr_rx_lp_valid 1rx_exp_toggle ~rx_oam<1><6>rx_lp_ack 1

LOAD EVEN PARITY

rx_oam<rx_cnt><7:0> rx_oam_field<7:0>rx_cnt 1

LOAD ODD PARITY

rx_oam<rx_cnt><7:0> rx_oam_field<7:0>rx_cnt rx_cnt + 1

BAD CRC16

rx_cnt 0

(rx_cnt = 12) *(CRC16_Check(rx_oam<11 to 0><7:0>) = GOOD)

Parity_Check(rx_oam_field<8:0>) = Even

Parity_Check(rx_oam_field<8:0>) = Odd

(rx_cnt = 12) *(CRC16_Check(rx_oam<11 to 0><7:0>) = BAD)

rx_boundary

rx_boundary

rx_boundary

rx_boundary





Figure 97–18—Transmit state diagram

TRANSMIT INIT

tx_toggle 0tx_lp_ready 1tx_oam<9 to 0><7:0> 0tx_oam_field<8:0> 0mr_tx_valid 0mr_tx_toggle 0mr_tx_received 0mr_tx_received_toggle 0mr_tx_ping 0mr_tx_SNR[1:0] 00

LOAD TRANSMIT PAYLOAD

mr_tx_SNR[1:0] SNR[1:0]tx_oam<0><1:0> SNR[1:0]tx_oam<0><2> mr_tx_pingtx_oam<0><3> rx_lp_pingtx_oam<1><5> rx_lp_acktx_oam<1><4> mr_rx_lp_toggletx_oam<1><6> tx_toggle

if ((mr_tx_valid = 1) * (tx_lp_ready = 1)) thentx_oam<1><7> 1tx_oam<1><3:0> mr_tx_message_num[3:0]tx_oam<n+2><7:0> mr_tx_message[8n+7:8n]

where n = 0 to 7mr_tx_valid 0mr_tx_toggle ~mr_tx_toggletx_lp_ready 0

CHECK ACK

if ((rx_ack = 1) * (rx_ack_toggle = tx_toggle)) thentx_toggle mr_tx_toggletx_lp_ready 1tx_oam<1><7> 0mr_tx_received 1mr_tx_received_toggle rx_ack_toggle

CALC CRC16

(tx_oam<11><7:0>, tx_oam<10><7:0>) CRC16(tx_oam<9 to 0><7:0>)

CALC PARITY

tx_oam<11 to 0><8> Parity(tx_oam<11 to 0><7:0>)tx_cnt 0

TRANSMIT SYMBOL

tx_oam_field<8:0> tx_oam<tx_cnt><8:0>tx_cnt tx_cnt + 1

reset + link_status = FAIL

tx_boundary

UCT

UCT

UCT

UCT

(tx_cnt < 12) * tx_boundary(tx_cnt = 12) * tx_boundary





97.4 Physical Medium Attachment (PMA) sublayer

97.4.1 PMA functional specifications

The PMA couples messages from a PMA service interface specified in 97.2.2 to the 1000BASE-T1baseband medium, specified in 97.5.

The interface between PMA and the baseband medium is the Medium Dependent Interface (MDI), which isspecified in 97.7.

97.4.2 PMA functions

The PMA sublayer comprises one PMA Reset function and five simultaneous and asynchronous operatingfunctions. The PMA operating functions are PHY Control, PMA Transmit, PMA Receive, Link Monitor,and Clock Recovery. All operating functions are started immediately after the successful completion of thePMA Reset function.

LIN

KM

ON

ITO

R

PMA_LINK.request

config

tx_mo

de

loc_

rcvr_status

rem_rcvr_

statu

s / rem

_ph

y_re

ady

recovered_clock

PM

A_

UN

ITD

ATA

.req

uest

PM

A_U

NIT

DA

TA.ind

icatio

n

link_

statu

s

(link_control)

NOTE—The recovered_clock arc is shown to indicate delivery of the recovered clock signal back to PMA TRANSMIT for loop timing.

scr_statu

s / pcs_statu

s

(tx_symb)

(rx_sym

b)

PMA_LINK.indication

(link_status)

MD

I+M

DI-

PMA

RECEIVEPMA

TRANSMIT

received_

CLOCKRECOVERY

PHYCONTROL

MEDIUM

INTERFACEDEPENDENT

(MDI)

PMA SERVICEINTERFACE

Figure 97–19—PMA reference diagram

clock

Tech

no

log

y Dep

en

den

t Inte

rface

(op

tion

al)

rx_lpi_

active

tx_lp

i_active

loc_

phy_re

ady

LIN

KS

YN

CH

RO

NIZ

AT

ION

sync_link_control

sync_tx_symb





The PMA reference diagram, Figure 97–19, shows how the operating functions relate to the messages of thePMA Service interface and the signals of the MDI. Connections from the management interface, comprisingthe signals MDC and MDIO, to other layers are pervasive and are not shown in Figure 97–19.

97.4.2.1 PMA Reset function

The PMA Reset function shall be executed whenever one of the two following conditions occur:

a) Power for the device containing the PMA has not reached the operating state

b) The receipt of a request for reset from the management entity

PMA Reset sets pma_reset = ON while any of the above reset conditions hold true. All state diagrams takethe open-ended pma_reset branch upon execution of PMA Reset. The reference diagrams do not explicitlyshow the PMA Reset function.

97.4.2.2 PMA Transmit function

The PMA Transmit function comprises a transmitter to generate a three level modulated signal on the singletwisted-pair copper cable. PMA Transmit shall continuously transmit onto the MDI pulses modulated by thesymbols given by tx_symb when sync_link_control = ENABLE, or the sync_tx_symb output by the PHYLink Synchronization function when sync_link_control = DISABLE, after processing with optional transmitfiltering, digital-to-analog conversion (DAC) and subsequent analog filtering. The signals generated byPMA Transmit shall comply with the electrical specifications given in 97.5.

When the PMA_CONFIG.indication parameter config is MASTER, the PMA Transmit function shallsource TX_TCLK from a local clock source while meeting the transmit jitter requirements of 97.5.3.3. TheMASTER-SLAVE relationship shall include loop timing. If the PMA_CONFIG.indication parameter configis SLAVE, the PMA Transmit function shall source TX_TCLK from the recovered clock of 97.4.2.8 whilemeeting the jitter requirements of 97.5.3.3.

97.4.2.2.1 Global PMA transmit disable

When the PMA_transmit_disable variable is set to true, this function shall turn off the transmitter so that thetransmitter Average Launch Power of the Transmitter is less than –53 dBm.

97.4.2.3 PMA Receive function

The PMA Receive function comprises a receiver for PAM3 signals on the twisted-pair. PMA Receivecontains the circuits necessary to both detect symbol sequences from the signals received at the MDI overreceive pair and to present these sequences to the PCS Receive function. The PMA translates the signalsreceived on the twisted-pair into the PMA_UNITDATA.indication parameter rx_symb. The quality of thesesymbols shall allow RFER of less than 3.6 10–7 after RS-FEC decoding, over a channel meeting therequirements of 97.6.

To achieve the indicated performance, it is highly recommended that PMA Receive include the functions ofsignal equalization and echo cancellation. The sequence of symbols assigned to tx_symb is needed toperform echo cancellation.

The PMA Receive function uses the scr_status parameter and the state of the equalization, cancellation, andestimation functions to determine the quality of the receiver performance, and generates the loc_rcvr_statusvariable accordingly. The loc_rcvr_status variable is expected to become NOT_OK when the link partner’stx_mode changes to SEND_Z from any other values (see PHY Control state diagram in Figure 97–26). Theprecise algorithm for generation of loc_rcvr_status is implementation dependent.





The receiver uses the sequence of symbols during the training sequence to detect and correct for pair polarityswaps.

The PMA Receive fault function is optional. The PMA Receive fault function is the logical OR of thelink_status = FAIL and any implementation specific fault. If the MDIO interface is implemented, then thisfunction shall contribute to the receive fault bit specified in 45.2.1.134.6.

97.4.2.4 PHY Control function

PHY Control generates the control actions that are needed to bring the PHY into a mode of operation duringwhich frames can be exchanged with the link partner. PHY Control shall comply with the state diagramdescription given in Figure 97–26.

During PMA training (TRAINING and COUNTDOWN states in Figure 97–26), PHY Control informationis exchanged between link partners with a 12-octet InfoField, which is XORed with the first 96 bits of the15th partial PHY frame (bits 2520 to 2615) of the PHY frame. The InfoField is also denoted IF. The linkpartner is not required to decode every IF transmitted but is required to decode IFs at a rate that enables thecorrect actions prior to the PAM2 to PAM3 transition.

The 12-octet InfoField shall include the fields in 97.4.2.4.2 through 97.4.2.4.8, also shown in the overviewFigure 97–20, and the more detailed Figure 97–21 and Figure 97–22. Each InfoField shall be transmitted atleast 256 times to ensure detection at link partner.

Figure 97–20—InfoField format

0xBB 0xA7 0x00 PFC24 Message MSG24 MSG24 MSG24 CRC16

octet 1 octet 2 octet 3 octets 4/5/6 octet 7 octets 8/9/10 octets 11/12

Figure 97–21—InfoField TRAINING format

0xBB 0xA7 0x00 PFC24 Message SeedUsrCfgCap CRC16


PMA_state = 00

Figure 97–22—InfoField COUNTDOWN format

0xBB 0xA7 0x00 PFC24 Message DataSwPFC24 CRC16


PMA_state = 01





97.4.2.4.1 InfoField notation

For all the InfoField notations in the following subclauses, Reserved<bit location> represents any unusedvalues and shall be set to zero on transmit and ignored when received by the link partner. The InfoField istransmitted following the notation described in 97.3.2.2.3 where the LSB of each octet is sent first and theoctets are sent in increasing number order (that is, the LSB of Oct1 is sent first).

97.4.2.4.2 Start of Frame Delimiter

The start of Frame Delimiter consists of 3 octets [Oct1<7:0>, Oct2<7:0>, Oct3<7:0>] and shall use thehexadecimal value 0xBBA700. 0xBB corresponds to Oct1<7:0> and so forth.

97.4.2.4.3 Partial PHY frame Count (PFC24)

The start of partial PHY frame Count consists of 3 octets [Oct4<7:0>, Oct5<7:0>, Oct6<7:0>] and indicatesthe running count of partial PHY frames sent LSB first. There are 15 partial PHY frames per PHY frame andthe InfoField is embedded within the 15th partial PHY frame. The first partial PHY frame is zero, thus thefirst partial PHY frame count field after a reset is 14.

97.4.2.4.4 Message Field

Message Field (1 octet). For the MASTER, this field is represented by Oct7{PMA_state<7:6>,loc_rcvr_status<5>, en_slave_tx<4>, reserved<3:0>}. For the SLAVE, this field is represented byOct7{PMA_state<7:6>, loc_rcvr_status<5>, timing_lock_OK<4>, reserved<3:0>}.

The two state-indicator bits PMA_state<7:6> shall communicate the state of the transmitting transceiver tothe link partner. PMA_state<7:6> = 00 indicates TRAINING, and PMA_state<7:6> = 01 indicatesCOUNTDOWN.

All possible Message Field settings are listed in Table 97–7 for the MASTER and Table 97–8 for theSLAVE. Any other value shall not be transmitted and shall be ignored at the receiver. The Message Fieldsetting for the first transmitted PMA frame shall be the first row of Table 97–7 for the MASTER and the firstor second row of Table 97–8 for the SLAVE. Moreover, for a given Message Field setting, the next MessageField setting shall be the same Message Field setting or the Message Field setting corresponding to a rowbelow the current setting. When loc_rcvr_status = OK the InfoField variable is set to loc_rcvr_status<5> = 1and set to 0 otherwise.

Table 97–7—InfoField message field valid MASTER settings

PMA_state<7:6> loc_rcvr_status en_slave_tx reserved reserved reserved reserved

00 0 0 0 0 0 0

00 0 1 0 0 0 0

00 1 1 0 0 0 0

01 1 1 0 0 0 0





97.4.2.4.5 PHY Capability Bits, User Configurable Register, and Data Mode Scrambler Seed

When PMA_state<7:6> = 00, then [0ct8<7:0>, 0ct9<7:0>, 0ct10<7:0>] contains the two PHY capabilitybits, the user configurable register bits, and the 15-bit data mode scrambler seed (Seed). Each octet is sentLSB first.

The format of PHY capability bits is Oct9<7> = EEEen and Oct10<0> = OAMen, indicating EEE and1000BASE-T1 OAM capability enable, respectively. The PHY shall indicate the support of optionalcapabilities by setting the corresponding capability bits.

The data mode scrambler seed contains bits S14 (sent first) to S0 (sent last) to indicate the initial state of thedata mode transmit scrambler of the local device upon reaching the data switch partial PHY frame count.The state of the scrambler in Figure 97–9 shall be S14:S0 at the first bit of the first PHY frame when thepartial PHY frame counter equals to the DataSwPFC24 value, see 97.4.2.4.6. The format of Seed isOct8<7:0> = S<7:14> and Oct9<6:0> = S<0:6>. Seed S<14:0> shall not be all zeros.

The remaining 7-bit Oct10<7:1> form a user-configurable register. See 97.4.2.4.11 for details.

97.4.2.4.6 Data Switch partial PHY frame Count

When PMA_state<7:6> = 01, then [Oct8<7:0>, Oct9<7:0>, Oct10<7:0>] contains the data switch partialPHY frame count (DataSwPFC24) sent LSB first. DataSwPFC24 indicates the partial PHY frame countwhen the transmitter switches from PAM2 to PAM3, which occurs at the start of an RS-FEC block. The lastvalue of PFC24 prior to the transition is DataSwPFC24 - 1. DataSwPFC24 shall be set to an integer multipleof 15. This value of DataSwPFC24 guarantees that the switch from PAM2 to PAM3 occurs on a PHY frameboundary.

97.4.2.4.7 Reserved Fields

When PMA_state<7:6> is greater than 01, then [Oct8<1:0>, Oct9<1:0>, Oct10<7:0>] contains a reservedfield. All InfoField fields denoted Reserved are reserved for future use.

97.4.2.4.8 CRC16

CRC16 (2 octets) shall implement the CRC16 polynomial (x+1)(x15+x+1) of the previous 7 octets,Oct4<7:0>, Oct5<7:0>, Oct6<7:0>, Oct7<7:0>, Oct8<7:0>, Oct9<7:0>, and Oct10<7:0>. The CRC16 shallproduce the same result as the implementation shown in Figure 97–23. In Figure 97–23 the 16 delayelements S0,..., S15, shall be initialized to zero. Afterwards Oct4 through Oct10 are used to compute theCRC16 with the switch connected, which is setting CRCgen in Figure 97–23. After all the 7 octets have

Table 97–8—InfoField message field valid SLAVE settings

PMA_state<7:6> loc_rcvr_status timing_lock_OK reserved reserved reserved reserved

00 0 0 0 0 0 0

00 0 1 0 0 0 0

00 1 1 0 0 0 0

01 1 1 0 0 0 0





been processed, the switch is disconnected (setting CRCout) and the 16 values stored in the delay elementsare transmitted in the order illustrated, first S15, followed by S14, and so on, until the final value S0.

97.2.4.9 PMA MDIO function mapping

The MDIO capability described in Clause 45 defines several variables that provide control and statusinformation for and about the PMA. Mapping of MDIO control variables to PMA control variables is shownin Table 97–9. Mapping of MDIO status variables to PMA status variables is shown in Table 97–10.

97.4.2.4.10 Start-up sequence

The start-up sequence shall comply with the state diagram description given in Figure 97–26. If the Auto-Negotiation function is not implemented, or mr_autoneg_en = false, PMA_CONFIG is predetermined to beMASTER or SLAVE via management control during initialization or via default hardware setup.

The Auto-Negotiation function is optional for 1000BASE-T1 PHYs. If the Auto-Negotiation function isused, during the Auto-Negotiation process PHY Control is in the DISABLE_TRANSMITTER state and thetransmitter is disabled. If the Auto-Negotiation function is not used, during the PHY Link Synchronizationstage the PHY Control remains in the DISABLE_TRANSMITTER state and the Link Synchronizationfunction (see 97.4.2.6) is the data source for the PMA Transmit function.

Table 97–9—MDIO/PMA control variable mapping

MDIO control variable PMA register name Register/bit number PMA control variable

Reset Control register 1 /1000BASE-T1 PMA control register

1.0.15 /1.2304.15

pma_reset

Transmit disable 1000BASE-T1 PMA control register 1.2304.14 PMA_transmit_disable

Table 97–10—MDIO/PMA status variable mapping

MDIO status variable PMA register name Register/bit number PMA status variable

Receive fault 1000BASE-T1 PMA status register 1.2305.1 PMA_receive_fault

Figure 97–23—CRC16

S0 +S1 S2 S14 + S15

+

CRC16 output

Oct4 through Oct10

Logic 0

CRCgen CRCout





When the Auto-Negotiation asserts link_control = ENABLE, or PHY Link Synchronization process assertssync_link_control = ENABLE, PHY Control enters the INIT_MAXWAIT_TIMER state. Upon entering theINIT_MAXWAIT_TIMER state, the maxwait_timer is started. PHY Control then transitions to the SILENTstate where the minwait_timer is started and the PHY transmits zeros (tx_mode = SEND_Z).

In MASTER mode PHY Control transitions to the TRAINING state once the minwait_timer expires.

Upon entering the TRAINING state, the minwait_timer is started and the PHY Control assertstx_mode = SEND_T sending PAM2 together with InfoFields. The PHY Control also sets PMA_state = 00and sends the PHY capability bits, the user configurable register bits, and the Seed value used by the localdevice for the data mode scrambler initialization, see 97.4.2.4.5.

The optional EEE capability shall be enabled only if both PHYs set the capability bit EEEen = 1. Theoptional 1000BASE-T1 OAM capability shall be enabled only if both PHYs set the capability bitOAMen = 1.

Initially the MASTER is not ready for the SLAVE to respond and sets en_slave_tx = 0, which iscommunicated to the link partner via the InfoField. After the MASTER has sufficiently converged thenecessary circuitry, the MASTER shall set en_slave_tx = 1 to allow the SLAVE to transition to TRAINING.

In SLAVE mode PHY Control transitions to the TRAINING state only after the SLAVE PHY acquirestiming, converges its equalizers, acquires its descrambler state and sets loc_SNR_margin = OK. TheSLAVE shall align its transmit 81B-RS frame to within +0/–1 partial PHY frames of the MASTER as seenat the SLAVE MDI. The SLAVE InfoField partial PHY frame Count shall match the MASTER InfoFieldpartial PHY frame Count for the aligned frame.

Upon entering TRAINING state the SLAVE initially sets timing_lock_OK = 0 until it has acquired timinglock at which point the SLAVE sets timing_lock_OK = 1.

After the PHY completes successful training and establishes proper receiver operations, PCS Transmitconveys this information to the link partner via transmission of the parameter InfoField valueloc_rcvr_status. The link partner’s value for loc_rcvr_status is stored in the local device parameterrem_rcvr_status. Upon expiration of the minwait_timer and when the condition loc_rcvr_status = OK andrem_rcvr_status = OK is satisfied, PHY control transitions to the COUNTDOWN state.

Upon entering the COUNTDOWN state, PHY Control sets PMA_state = 01 and DataSwPFC24 to the valueof the partial PHY frame count when the transmitter switches from PAM2 to PAM3.

Upon reaching DataSwPFC24 partial PHY frame count PHY Control transitions to the SEND_IDLE1 stateand forces transmission into the idle mode by asserting tx_mode = SEND_I.

Once the link partner has transitioned from PAM2 to PAM3, PHY Control transitions to the SEND_IDLE2state and starts the minwait_timer.

Upon expiration of the minwait_timer and when the condition loc_phy_ready = OK andrem_phy_ready = OK is satisfied, PHY control transitions to the SEND_DATA state.

Upon entering the SEND_DATA state, PHY Control starts the minwait_timer and enables frametransmission to the link partner by asserting tx_mode = SEND_N.

The operation of the maxwait_timer requires that the PHY complete the start-up sequence from stateINIT_MAXWAIT_TIMER to SEND_DATA in the PHY Control state diagram state diagram (Figure 97–26)in less than 97.5 ms to avoid link_status being changed to FAIL by the Link Monitor state diagram(Figure 97–27).





97.4.2.4.11 PHY Control Registers

The PHY control registers are shown in Table 97–11.

97.4.2.5 Link Monitor function

Link Monitor determines the status of the underlying receive channel and communicates it via the variablelink_status. Failure of the underlying receive channel causes the PMA to set link_status to FAIL, which inturn causes the PMA’s clients to stop exchanging frames and restart the auto-negotiation (if enabled) orsynchronization (if auto-negotiation is not enabled) process.

The Link Monitor function shall comply with the state diagram of Figure 97–27.

Upon power on, reset, or release from power down, the Auto-Negotiation function setlink_control = DISABLE, or PHY Link Synchronization algorithms set sync_link_control = DISABLE.During this period, link_status = FAIL is asserted. When the Auto-Negotiation function establishes thepresence of a remote 1000BASE-T1 PHY, link_control is set to ENABLE, or when the PHY LinkSynchronization finishes the synchronization function, sync_link_control is set to ENABLE, and the LinkMonitor state machines begins monitoring the PCS and receiver lock status. As soon as reliable transmissionis achieved, the variable link_status = OK is asserted, upon which further PHY operations can take place.

Table 97–11—PHY Control Registers

MDIO control/status variable PMA register name Register/ bit number PMA control/status

variable

MASTER-SLAVE BASE-T1 PMA/PMD control register

1.2100.14 force_config (see 97.4.2.6.1)

Type selection BASE-T1 PMA/PMD control register

1.2100.3:0 force_PHY_type (see 97.4.2.6.1)

1000BASE-T1 OAM Ability

1000BASE-T1 PMA status register

1.2305.11

EEE Ability 1000BASE-T1 PMA status register

1.2305.10

User Field 1000BASE-T1 training register

1.2306.10:4 PMA_state<7:6> = 00, Oct10<7:1>

1000BASE-T1 OAM Advertisement

1000BASE-T1 training register

1.2306.1 PMA_state<7:6> = 00, Oct10<0>

EEE Advertisement 1000BASE-T1 training register

1.2306.0 PMA_state<7:6> = 00, Oct9<7>

Link Partner User Field 1000BASE-T1 link partner training register

1.2307.10:4 LP PMA_state<7:6> = 00, Oct10<7:1>

Link Partner 1000BASE-T1 OAM Advertisement

1000BASE-T1 link partner training register

1.2307.1 LP PMA_state<7:6> = 00, Oct10<0>

Link Partner EEE Advertisement

1000BASE-T1 link partner training register

1.2307.0 LP PMA_state<7:6> = 00, Oct9<7>





97.4.2.6 PHY Link Synchronization

If the optional Clause 98 Auto-Negotiation function is disabled or not implemented, then the LinkSynchronization function is responsible for establishing the start of PHY PMA training as defined in97.4.2.4.

When operating, the Link Synchronization function is the data source for the PMA Transmit function (see97.4.2.2), and generates a signal, SEND_S, used by the MASTER and SLAVE to discover the link partnerand synchronize the start of PMA training.

Link Synchronization employs the SEND_S signal to achieve synchronization prior to link training. If thePHY is configured as MASTER, Link Synchronization shall employ Equation (97–8) as the PN sequencegenerator.

(97–8)

If the PHY is configured as SLAVE, Link Synchronization shall employ Equation (97–9) as PN sequencegenerator.

(97–9)

The period of both PN sequences is 255.

An implementation of MASTER and SLAVE PHY SEND_S PN sequence generators by linear-feedbackshift registers is shown in Figure 97–24. The bits stored in the shift register delay line at time n are denotedby Sn[7:0]. At each symbol period, the shift register is advanced by one bit, and one new bit represented bySn[0] is generated. The PN sequence generator shift registers shall be reset to a non-zero value uponentering into the TRANSMIT_DISABLE state (see Figure 97–25). The receiver may not necessarily receivea continuous PN sequence between separate periods of SEND_S.

The bit Sn[0] is mapped to the transmit symbol Tn as follows: if Sn[0] = 0 then Tn = +1, if Sn[0] = 1 thenTn = –1.

pM x x8 x4 x3 x2 1+ + + +=

pMS x x8

x6

x5

x4

1+ + + +=

Figure 97–24—SEND_S PN sequence generator by linear feedback shift registers Sn

T

MASTER PHY SEND_S PN sequence generator

T

Sn[0] Sn[1]

+

T

Sn[2]

+

T

Sn[3]

+

T

Sn[4]

T

Sn[5]

T

Sn[6]

T

Sn[7]

T T

Sn[0] Sn[1]

SLAVE PHY SEND_S PN sequence generator

T

Sn[2]

T

Sn[3]

+

T

Sn[4]

+

T

Sn[5]

+

T

Sn[6]

T

Sn[7]





The synchronization state diagram in Figure 97–25 shall be used to synchronize 1000BASE-T1 PHYs priorto the 1000BASE-T1 link training. If Clause 98 Auto-Negotiation function is enabled, then the Auto-Negotiation function shall be used as the mechanism for PHY synchronization and the synchronization statediagram in Figure 97–25 remains in the SYNC_DISABLE state.

97.4.2.6.1 State diagram variables

force_configThis variable indicates whether the PHY operates as a MASTER or as a SLAVE. The variabletakes on one of the following values:

MASTER: this value is continuously asserted when the PHY operates as a MASTERSLAVE: this value is continuously asserted when the PHY operates as a SLAVE

force_phy_typeThis variable indicates what speed the PHY is to operate when Auto-Negotiation is disabled or notimplemented. The variable takes on one of the following values:

1000-T1: if Auto-Negotiation is disabled or not implemented and 1000BASE-T1 is selected100-T1: if Auto-Negotiation is disabled or not implemented and 100BASE-T1 is selectedNone: else


mr_autoneg_enable:see 98.5.1

mr_main_resetsee 98.5.1

power_onsee 98.5.1

send_s_sigdetThis variable indicates whether the SEND_S pattern was detected. This variable shall be set falseno later than 1 µs after the signal goes quiet on the MDI. Values:

true: SEND_S pattern detectedfalse: SEND_S pattern not detected

sync_link_controlThis variable indicates the data source for the PMA Transmit function.Values:

DISABLE: The data source is the PHY Link Synchronization function (sync_tx_symb)ENABLE: The data source is PMA_UNITDATA.request (tx_symb)

sync_tx_modeThis variable indicates what symbols are sent by the PHY Link Synchronization process.Values:

SEND_S: this value is continuously asserted to enable transmission of the PN sequencedefined in 97.4.2.6

SEND_Z: this value is asserted to disable transmission





97.4.2.6.2 State diagram timers

break_link_timersee 98.5.2

link_fail_inhibit_timersee 98.5.2

send_s_timerThis timer is used to control the duration SEND_S is transmitted. The timer shall expire1.0 µs±0.04 µs after being started.

sigdet_wait_timerThis timer is used to control the wait time after transmitting or detecting the end of SEND_S. Thetimer shall expire 4 µs±0.1 µs after being started.

97.4.2.6.3 Messages

sync_tx_symbA signal sent from Link Synchronization block to PMA Transmit indicating that a PAM2(SEND_S) or zero (SEND_Z) symbol is available. The Link Synchronization block generatessync_tx_symb synchronously with every transmit clock cycle.





97.4.2.6.4 State diagrams

Figure 97–25—PHY Link Synchronization state diagram

TRANSMIT_DISABLE

start break_link_timersync_tx_mode SEND_Zsync_link_control DISABLE

SILENT WAIT

sync_tx_mode SEND_Z

A

B

AA

LINK_GOOD

B

TX_SEND_S

start send_s_timersync_tx_mode SEND_S

A

SIGDET_WAIT

start sigdet_wait_timersync_tx_mode SEND_Z

PAUSE

start sigdet_wait_timersync_tx_mode SEND_Z

LINK_GOOD_CHECK

start link_fail_inhibit_timersync_link_control ENABLE

sigdet_wait_tim

er_done *

force_config =

MA

ST

ERsend_s_sigdet =

false *force_config =

SLA

VE

send_s_timer_done *force_config = MASTER

send_s_timer_done *force_config = SLAVE

SYNC_DISABLE

break_link_timer_done *force_config = MASTER

break_link_timer_done *force_config = SLAVE

send_s_sidget = true

send_s_sigdet = false *force_config = MASTER

sigdet_wait_timer_done

link_status = OK

power_on = true +mr_main_reset = true +

mr_autoneg_enable = true +

link_fail_inhibit_timer_done

link_status = FAIL mr_autoneg_enable = false

force_phy_type 1000-T1





97.4.2.7 Refresh Monitor function

A 1000BASE-T1 PHY supporting the EEE capability shall implement the Refresh monitor function. TheRefresh monitor operates when the PHY is in the LPI receive mode. If Refresh is not reliably detectedwithin a moving window of 50 Q/R cycles (4.32 ms), the refresh monitor shall set PMA_refresh_status toFAIL, which sets link_status to FAIL. Subsequently the PHY restarts auto-negotiation (if auto-negotiation isenabled) or synchronization (if auto-negotiation is disabled). PMA_refresh_status shall be set to OK whenthe Link Monitor state diagram (Figure 97–27) enters the LINK_UP state.

97.4.2.8 Clock Recovery function

The Clock Recovery function shall provide a clock suitable for signal sampling so that the RS FER indicatedin 97.4.2.3 is achieved. The received clock signal is expected to be stable and ready for use when traininghas been completed. The received clock signal is supplied to the PMA Transmit function by received_clock.

97.4.3 MDI

Communication through the MDI is summarized in 97.4.3.1 and 97.4.3.2.

97.4.3.1 MDI signals transmitted by the PHY

The symbols to be transmitted by the PMA are denoted by tx_symb. The modulation scheme used over eachpair is PAM3. PMA Transmit generates a pulse-amplitude modulated signal on each pair in the followingform:

(97–10)

In Equation (97–10), an is the PAM3 modulation symbol from the set {–1, 0, 1} to be transmitted attime , and denotes the system symbol response at the MDI. This symbol response shall complywith the electrical specifications given in 97.5.

97.4.3.2 Signals received at the MDI

Signals received at the MDI can be expressed for each pair as pulse-amplitude modulated signals that arecorrupted by noise as follows:

(97–11)

In Equation (97–11) hR(t) denotes the symbol response of the overall channel impulse response between thetransmit symbol source and the receive MDI and w(t) represents the contribution of various noise sourcesincluding uncancelled echo. The receive signal is processed within the PMA Receive function to yield thereceived symbols rx_symb.

97.4.4 State variables

97.4.4.1 State diagram variables

auto_neg_impThis variable indicates if an optional Auto-Negotiation sublayer is associated with the PMA.Values:

true: An optional Auto-Negotiation sublayer is associated with the PMAfalse: An optional Auto-Negotiation sublayer is not associated with the PMA

s t anhT t nT– n 0=

=

nT hT t

r t anhR t nT– w t +n 0=

=





configThe PMA generates this variable continuously and passes it to the PCS via the PMA_CON-FIG.indication primitive. Values:

MASTERSLAVE

en_slave_txThe en_slave_tx variable in the InfoField received by the SLAVE. Values:

0: Master is not ready for the SLAVE to transmit1: Master is ready for the SLAVE to transmit

infofield_completeThis variable indicates that a complete set of InfoField messages has been sent (see 97.4.2.4).Values:

false: a complete set of InfoField messages has not been senttrue: a complete set of InfoField messages has been sent

link_controlThis variable is defined in 97.2.1.1.1.


loc_phy_readyThis variable is set by the PMA Receive function to indicate the local PHY is ready or not ready toreceive data. The value of loc_phy_ready is equal to OK only if loc_rcvr_status = OK andpcs_status = OK. Otherwise its value is NOT_OK. This variable is conveyed to the link partner bythe PCS as defined in Table 97–1.Values:

OK: the local PHY is ready to receive dataNOT_OK: the local PHY is not ready to receive data

loc_countdown_doneThis variable is set to false when the PHY Control state diagram is in theDISABLE_TRANSMITTER state and is set to true immediately after transmitting the last bit ofthe DataSwPFC24–1 partial PHY frame.

loc_rcvr_statusVariable set by the PMA Receive function to indicate correct or incorrect operation of the receivelink for the local PHY. This variable is transmitted in the loc_rcvr_status bit of the InfoField by the local PHY. Values:

OK: the receive link for the local PHY is operating reliablyNOT_OK: operation of the receive link for the local PHY is unreliable

loc_SNR_marginThis variable reports whether the local device has sufficient SNR margin to continue to the nextstate. The criterion for setting the parameter loc_SNR_margin is left to the implementer.Values:

OK: the local device has sufficient SNR marginNOT_OK: the local device does not have sufficient SNR margin





PMA_refresh_statusThis variable indicates the status of the Refresh Monitor as described in 97.4.3. Values:

OK: refresh is detected reliablyFAIL: refresh is not detected reliably

pma_resetAllows reset of all PMA functions. It is set by PMA Reset.Values:

ONOFF

PMA_stateVariable for the value transmitted in the PMA_state<7:6> of the InfoField by the local PHY.Values:

00: TRAINING state01: COUNTDOWN state

PMA_watchdog_statusVariable indicating the status of the PAM3 monitor. Values:

OK: the local device has received sufficient PAM3 transitionsNOT_OK: the local device has not received sufficient PAM3 transitions

During normal operation NOT_OK is assigned when:

— PAM3 symbol 0 consecutively seen on the line for longer than 2 µs ± 0.1 µs

— PAM3 symbol +1 consecutively seen on the line for longer than 3.9 µs ± 0.1 µs

— PAM3 symbol –1 consecutively seen on the line for longer than 3.9 µs ± 0.1 µs

During Low Power Idle operation NOT_OK is assigned when:

— PAM3 symbol not toggling on the line during one full refresh window

rem_countdown_doneThis variable is set to false when the PHY Control state diagram is in the DISABLE_TRANSMIT-TER state or SILENT state and is set to true once the receiver has transitioned from PAM2 toPAM3 mode and has received a valid PHY frame containing all IDLEs.

rem_phy_readyThis variable is set by the PCS Receive function to indicate whether the remote PHY is ready ornot ready to receive data. This variable is received from the link partner by the PCS as defined inTable 97–1. The variable retains its value until the next normal Inter-Frame idle is received.Values:

OK: the remote PHY is ready to receive dataNOT_OK: the remote PHY is not ready to receive data

rem_rcvr_statusVariable set by the PCS Receive function to indicate whether correct operation of the receive linkfor the remote PHY is detected or not. This variable is received in the loc_rcvr_status bit in theInfoField from the remote PHY. This variable is set to NOT_OK if the PCS has not decoded avalid InfoField from the remote PHY.Values:

OK: the receive link for the remote PHY is operating reliablyNOT_OK: reliable operation of the receive link for the remote PHY is not detected





sync_link_controlThis variable is defined in 97.4.2.6.1.

tx_modeThe PMA generates this variable continuously and passes it to the PCS via the PMA_TX-MODE.indication primitive. Values:

SEND_N: this value is continuously asserted when transmission of sequences of symbolsrepresenting a GMII data stream take place

SEND_I: this value is continuously asserted when transmission of sequences of symbols representing an idle stream takes place

SEND_T: this value is continuously asserted when transmission of sequences of symbols representing the training sequences of symbols is to take place

SEND_Z: this value is asserted when transmission of zero symbols is to take place

97.4.4.2 Timers

All timers operate in the manner described in 14.2.3.2.

maxwait_timer A timer used to limit the amount of time during which a receiver dwells in the SILENT andTRAINING states. The timer shall expire 97.5 ms 0.5 ms after being started. This timer is used jointly in the PHY Control and Link Monitor state diagrams. The maxwait_timeris tested by the Link Monitor to force link_status to be set to FAIL if either of the followingconditions is true:

— the PMA_watchdog_status is NOT_OK

— the timer expires and loc_phy_ready is NOT_OK

— the PMA_refresh_status is FAIL

See Figure 97–26 and Figure 97–27.

minwait_timer A timer used to determine the minimum amount of time the PHY Control stays in the SILENT,TRAINING, SEND IDLE2, and SEND DATA states. The timer shall expire 975 µs 50 µs afterbeing started.





97.4.5 State diagrams

INIT_MAXWAIT_TIMER

start maxwait_timer

SILENT

tx_mode SEND_Zstart minwait_timer

COUNTDOWN

tx_mode SEND_TPMA_state 01

SEND IDLE1

tx_mode SEND_I

SEND DATA

tx_mode SEND_Nstart minwait_timer

TRAINING

tx_mode SEND_Tstart minwait_timerPMA_state 00

SEND IDLE2

tx_mode SEND_Istart minwait_timer

(link_control = DISABLE *auto_neg_imp = true * mr_autoneg_enable = true) +

(sync_link_control = DISABLE *(auto_neg_imp = false + mr_autoneg_enable = false)) +

pma_reset = ON

(link_control = ENABLE *auto_neg_imp = true * mr_autoneg_enable = true) +(sync_link_control = ENABLE *(auto_neg_imp = false + mr_autoneg_enable = false))

UCT

((config = MASTER) +(config = SLAVE * loc_SNR_margin = OK *en_slave_tx = 1)) * minwait_timer_done

loc_rcvr_status = OK * rem_rcvr_status = OK *minwait_timer_done * infofield_complete

DISABLE_TRANSMITTER

loc_countdown_done * infofield_complete

rem_countdown_done

loc_phy_ready = OK *rem_phy_ready = OK *minwait_timer_done

loc_rcvr_status = NOT_OK



Figure 97–26—PHY Control state diagram





97.5 PMA electrical specifications

This subclause specifies the electrical characteristics of the PMA for a 1000BASE-T1 Ethernet PHY.

97.5.1 EMC Requirements

See 96.5.1.

97.5.1.1 Immunity—DPI test

See 96.5.1.1.

97.5.1.2 Emission—150 conducted emission test

See 96.5.1.2.

97.5.2 Test modes

The test modes described as follows shall be provided to allow for testing of the transmitter jitter, transmitterdistortion, transmitter PSD, transmitter droop, and BER testing.

These test modes shall be enabled by setting a control register 1.2308.15:13 as shown in Table 97–12. Thetest modes shall only change the data symbols provided to the transmitter circuitry and do not alter theelectrical and jitter characteristics of the transmitter and receiver from those of normal (non-test mode)operation.

Figure 97–27—Link Monitor state diagram

NOTE 1—maxwait_timer is started in PHY Control state diagram (see Figure 97–26).

NOTE 2—The variables link_control and link_status are designated as link_control_1GigT1 and link_status_1GigT1,respectively, by the Auto-Negotiation Arbitration state diagram (Figure 98–7) if the optional Auto-Negotiation function isimplemented.

LINK_DOWN

link_status FAIL

LINK_UP

link_status OK

(link_control = DISABLE *auto_neg_imp = true * mr_autoneg_enable = true) +(sync_link_control = DISABLE *(auto_neg_imp = false + mr_autoneg_enable = false)) +pma_reset = ON

minwait_timer_done *tx_mode = SEND_N

maxwait_timer_done * loc_phy_ready = NOT_OK +PMA_refresh_status = FAIL +PMA_watchdog_status = NOT_OK





Test mode 1 enables testing of timing jitter on MASTER and SLAVE transmitters. MASTER and SLAVE1000BASE-T1 PHYs are connected over a link segment defined in 97.6. When in this mode, the1000BASE-T1 PHY shall provide access to a frequency reduced version of the transmit symbol clock orTX_TCLK125. This 125 MHz test clock is one sixth frequency divided version of TX_TCLK that times thetransmitted symbols.

Test mode 2 is for transmitter jitter testing on MDI when transmitter is in MASTER timing mode. When testmode 2 is enabled, the 1000BASE-T1 PHY shall transmit a continuous pattern of three {+1} symbolsfollowed by three {–1} symbols with the transmitted symbols timed from its local clock source of 750 MHz.The transmitter output is a 125 MHz signal.

Test mode 3 is not defined and the corresponding register is reserved for future use.

Test mode 4 is for transmitter linearity testing. When test mode 4 is enabled, 1000BASE-T1 PHY shalltransmit the sequence of symbols generated by the scrambler generator polynomial per Equation (97–12).

(97–12)

The maximum-length shift register used to generate the sequences defined by this polynomial shall beupdated once per symbol interval (2/750 MHz). The bits stored in the shift register delay line at a particulartime n are denoted by . At each symbol period the shift register is advanced by one bit and onenew bit represented by is generated. Bits and are exclusive ORed together togenerate the next bit. The bit sequences , , and generated from combinations of thescrambler bits, as shown in Equation (97–13), shall be used to generate the ternary symbols, and , asshown in Table 97–13. The transmitter shall time the transmitted symbols from a 750 MHz 0.01% clockin the MASTER timing mode. The transmit signal level and spectral shaping in this mode shall be same asnormal (non-test) mode. A typical transmitter output for transmitter test mode 4 is shown in Figure 97–28.

(97–13)

Table 97–12—MDIO management registers settings for test modes

Registervalue Register description

000 Normal (non-test mode) operation.

001 Test mode 1—Setting MASTER and SLAVE PHYs for transmit clock jitter test in linked mode.

010 Test mode 2—Transmit MDI jitter test in MASTER mode.

011 Reserved.

100 Test mode 4—Transmit distortion test.

101 Test mode 5—Normal operation in Idle mode. This is for the PSD Mask test.

110 Test mode 6—Transmitter droop test mode.

111 Test mode 7—Normal operation with zero data pattern. This is for BER monitoring.

g x 1 x9 x11+ +=

Scrn 10:0

Scrn 0 Scrn 8 Scrn 10

Scrn 0 x0n x1n x2n

T0n T1n

x0n Scrn 0 =

x1n Scrn 1 Scrn 4 =

x2n Scrn 1 Scrn 5 =





Test mode 5 is for checking whether the transmitter is compliant with the transmit PSD mask and thetransmit power level. When test mode 5 is enabled, 1000BASE-T1 PHY shall transmit as in non-testoperation and in the MASTER data mode with data set to normal Inter-Frame idle signals.

When test mode 6 is enabled, 1000BASE-T1 PHY shall transmit a continuous pattern of fifteen {+1}symbols followed by fifteen {–1} symbols with the transmitted symbols timed from its local clock source of750 MHz. The transmitter output is a 25 MHz signal.

Test mode 7 is for enabling measurement of the bit error ratio of the link including the RS-FEC encoder /decoder, transmit and receive analog front ends of 1000BASE-T1 PHY, and a cable connecting two1000BASE-T1 PHYs. This mode reuses the 1000BASE-T1 normal (non-test) mode with zero data pattern.Instead of encoding received data from MAC, continuous zero data pattern is encoded. In the receive side,

Table 97–13—Transmit test mode 4 symbol mapping

0 0 0 –1 –1

0 0 1 0 –1

0 1 0 –1 0

0 1 1 –1 +1

1 0 0 +1 0

1 0 1 +1 –1

1 1 0 +1 +1

1 1 1 0 +1

Figure 97–28—Typical transmitter output for transmitter test mode 4

x2n x1n x0n T1n T0n





after FEC and 80B/81B decoding, zero data sequence is expected with no error. Any non-zero data bitreceived is counted as error and calculated in BER.

97.5.2.1 Test fixtures

The following fixtures, or their equivalents, as shown in Figure 97–29, Figure 97–30, Figure 97–31,Figure 97–32, and Figure 97–33, in stated respective tests, shall be used for measuring the transmitterspecifications for data communication only. The tolerance of resistors shall be ± 0.1%.

Figure 97–29—Transmitter test fixture 1 for transmitter droop measurement

Digital oscilloscopeor

data acquisition module

100

Transmitterundertest

High impedancedifferential probe

with resistance > 10 k and capacitance < 1 pF

Figure 97–30—Transmitter test fixture 2 for transmitter distortion measurement

Digital oscilloscopeor

data acquisition module

50

50

VdTransmitterundertest

High impedancedifferential probe

Postprocessing

Transmit Reference Clock





97.5.3 Transmitter electrical specifications

The PMA provides the Transmit function specified in 97.4.2.2 in accordance with the electricalspecifications of this clause. The PMA shall operate with AC coupling to the MDI. Where a load is notspecified, the transmitter shall meet the requirements of this clause with a 100 resistive differential loadconnected to the transmitter output.

Figure 97–31—Transmitter test fixture 3 for MASTER and SLAVE clock jitter measurement

Link Partner DUT

Digital Scope /

Capturing Device

TX_TCLK125

Figure 97–32—Transmitter test fixture 4 for MDI jitter measurement

Transmitterunder test

Balun withdiff. inputimpedanceof 100

Digital Scope / Capturing Device

Figure 97–33—Transmitter test fixture 5 for power spectral density measurement and transmit power level measurement

Transmitterunder test

Balun withdiff. inputimpedanceof 100

SpectrumAnalyzer





97.5.3.1 Maximum output droop

With the transmitter in test mode 6 and using the transmitter test fixture 1, the magnitude of both the positiveand negative droop shall be less than 10%, measured with respect to an initial value at 4 ns after the zerocrossing and a final value at 16 ns after the zero crossing (12 ns period).

97.5.3.2 Transmitter distortion

In Figure 97–30, the sinusoidal disturbing signal Vd, shall have amplitude of 3.6 V peak-to-peakdifferential, and frequency given by one-sixth of the symbol rate (125 MHz) synchronous with the testpattern. The generator of the disturbing signal shall have sufficient linearity and range so it does notintroduce any appreciable distortion when connected to the transmitter output.

Transmitter distortion is measured by capturing the test mode 4 waveform using transmitter test fixture 2.The peak distortion is determined by sampling the differential signal output with the symbol rate clock at anarbitrary phase and processing a block of consecutive samples with pseudo-code given below or anequivalent. The captured block of signal shall be at least 40 µs long and be sampled with the minimumsampling rate of 7.5 Gs/s (10 times the transmit symbol rate of 750 Ms/s).

The peak distortion values, measured at a minimum of 10 equally spaced phases of a single symbol period,shall be less than 15 mV. Notice the peak signal level is normalized to 1 V in the processing code. Thepseudo-code removes the sinusoidal disturbing signal from the measured data and computes the peakdistortion. The code assumes the disturber signal and the data acquisition clock are frequency locked to theDUT transmit clock.

% Post processing pseudo-code for 1000BASE-T1 transmitter distortion clearNs=2^11–1; % Scrambler lengthNc=70; % Canceller length % Generate scrambler sequencescr=ones(Ns,1);for i=12:Ns scr(i)=mod(scr(i–11) + scr(i-9),2);end % 1000BASE-T1 2D-PAM3 assignmenttm4=ones(Ns,1);map=[–1 –1;–1 0;0 –1;1 –1;0 1;–1 1;1 1;1 0]; scr3=[scr, mod(circshift(scr,1) + circshift(scr,4),2),...

mod(circshift(scr,1) + circshift(scr,5),2)];data = 4*scr3(:,3)+ 2*scr3(:,2)+scr3(:,1);for n=1:length(data)

tm4([2*n–1,2*n]) =map(data(n)+1,:);endNs=2*Ns; % Test mode4 matrixfor i=1:Nc X0(i,:)=circshift(tm4,1-i);end

% Read captured data file, 40us long, 7.5GSample/sec, high resolution capturefid=fopen('RawData.bin','r');tx = fread(fid,inf,'double');fclose(fid);

% LPF 375MHz [A,B]=butter(2,1/10,'low'); tx=filter(A,B,tx);





% HPF 12MHztx = filter([1,–1],[1,-exp(-2*pi/625)],tx); % Select six periods, 10x oversampling, a row vectortx=tx((1:6*Ns*10)+2e3)'; % removes HPF transient % Disturber removal and integration (average) of six periodsTX=fft(tx); tx=ifft(TX(1:6:end)); % Level normalization to 1Vtx=tx/(max(tx)-min(tx))*2; % Compute distortion for 10 clock phasesfor n=1:10 tx1=tx(n:10:end); % Align data and test pattern temp=xcorr(tx1,tm4);index=find(abs(temp)==max(abs(temp)));X=circshift(X0, [0, mod(index(1)+Nc–10,Ns)]); % Compute coefficients that minimize squared errorcoef=tx1/X; % Linear cancellererr=tx1-coef*X; % Peak distortiondist(n) = max(abs(err));end % Print distortion in mV (normalized) for 10 sampling phases format bankpeakDistortion_mV = 1000*dist'

97.5.3.3 Transmitter timing jitter

The transmitter timing jitter is measured by capturing the TX_TCLK125 waveform in both MASTER andSLAVE configurations while in test mode 1 using the transmitter test fixture 3 shown in Figure 97–31.

When in test mode 1 and the link is up and the two PHYs have established link (link_status is set to OK), theRMS value of the MASTER TX_TCLK125 jitter relative to an unjittered reference shall be less than 5 ps.The peak-to-peak value of the MASTER TX_TCLK125 jitter relative to an unjittered reference shall be lessthan 50 ps.

When in test mode 1 and the link is up and the two PHYs have established link (link_status is set to OK), theRMS value of the SLAVE TX_TCLK125 jitter relative to an unjittered reference shall be less than 10 ps.The peak-to-peak value of the SLAVE TX_TCLK125 jitter relative to an unjittered reference shall be lessthan 100 ps.

TX_TCLK125 jitter shall be measured over an interval of 1 ms ± 10%. The band-pass bandwidth of thecapturing device shall be larger than 2 MHz. The unjittered reference is a constant clock frequency extractedfrom each record of captured TX_TCLK125. The unjittered reference is based on linear regression offrequency and phase that produces minimum Time Interval Error.

For PHYs supporting LPI mode, in order for the transmit jitter to be similar to normal power modeoperation, the clock reference used to clock transmit-symbols shall be continuous going from normal powermode into and out of LPI mode.

In addition to jitter measurement for transmit clock, MDI jitter is measured when in test mode 2 and usingtest fixture 4 as shown in Figure 97–32. The RMS value of the MDI output jitter relative to an unjittered





reference shall be less than 5 ps. The peak-to-peak value of the MDI output jitter relative to an unjitteredreference shall be less than 50 ps. Jitter shall be measured over an interval of 1 ms ± 10%. The band-passbandwidth of the measurement device shall be larger than 2 MHz. Unjittered reference is a constant clockfrequency extracted from each record of captured differential output on MDI. The unjittered reference isbased on linear regression of frequency and phase that produces minimum Time Interval Error.

(97–14)

(97–15)

where

f is the frequency in MHz

97.5.3.4 Transmitter Power Spectral Density (PSD) and power level

In test mode 5 (normal operation), the transmit power shall be less than 5 dBm and the power spectraldensity of the transmitter, measured into a 100 load using the test fixture 5 shown in Figure 97–33 shall bebetween the upper and lower masks specified in Equation (97–14) and Equation (97–15). The masks areshown in Figure 97–34. The measurements need to be calibrated for insertion loss of the differential Balunused in the test. The resolution bandwidth of 100 kHz and sweep time of larger than 1 second are consideredin PSD measurement.

UpperPSD f

80– dBm/Hz 0 f 100

76– f25------– dBm/Hz 100 f 400

85.6– f62.5----------– dBm/Hz 400 f 600

=

LowerPSD f 86– dBm/Hz 40 f 100

82– f25------– dBm/Hz 100 f 400

=

Figure 97–34—Transmitter Power Spectral Density, upper and lower masks

0 100 200 300 400 500 600 700 800 900 1000-100

-98

-96

-94

-92

-90

-88

-86

-84

-82

-80

-78

-76

Frequency, MHz

PS

D U

pp

er

an

d L

ow

er

Ma

sks

in d

Bm

/Hz Upper Mask

Lower Mask





97.5.3.5 Transmitter peak differential output

When measured with 100 termination, transmit differential signal at MDI shall be less than 1.30 V peak-to-peak. This limit applies to all transmit modes including SEND_S, SEND_T, SEND_I, and SEND_Nmodes.

97.5.3.6 Transmitter clock frequency

The symbol transmission rate of the MASTER PHY shall be within the range 750 MHz ± 100 ppm.

For a MASTER PHY, when the transmitter is in the LPI transmit mode, the transmitter clock short-term rateof frequency variation shall be less than 0.1 ppm/second. The short-term frequency variation limit shall alsoapply when switching to and from the LPI mode.

97.5.4 Receiver electrical specifications

97.5.4.1 Receiver differential input signals

Differential signals received at the MDI that were transmitted from a remote transmitter within thespecifications of 97.5.3 and have passed through a link segment type A (specified in 97.6.1 and 97.6.3) arereceived with a BER less than 10–10 and sent to the PCS after link reset completion. This BER specificationshall be satisfied by a frame loss ratio less than 10–7 for 125-octet frames. Operation on link segment type Bis optional. If supported, the frame loss ratio shall also be met for link segments specified at 97.6.2 and97.6.4.

97.5.4.2 Alien crosstalk noise rejection

This specification is provided to verify the receiver’s tolerance to alien crosstalk noise. The test is performedwith a noise source consisting of a signal generator with Gaussian distribution, bandwidth of 550 MHz andmagnitude of –100 dBm/Hz for devices supporting type A link segments and –110 dBm/Hz for devicessupporting type B link segments. The receive DUT is connected to these noise sources through a resistivenetwork, as shown in Figure 97–35, with a link segment as defined in 97.6. The noise is added at the MDI ofthe DUT. The BER is expected to be less than 10–10, and to satisfy this specification the frame loss ratio isless than 10–7 for 125-octet packets measured at MAC/PLS service interface.

97.6 Link segment characteristics

1000BASE-T1 is designed to operate over a single twisted-pair copper cable that meets the requirementsspecified in this subclause. The single twisted-pair copper cable supports an effective data rate of 1 Gb/s in

Figure 97–35—Alien crosstalk noise rejection test setup

MDI Receive DeviceUnder TestTransmitter

500 *

500 *

100 < 0.5 m

Link Segment

*Resistor matching

MDI

T R

to 1 part in 1000Noise source

(Gaussian signal generator)





each direction simultaneously. The term link segment used in this clause refers to a single twisted-paircopper cable operating in full duplex.

Two link segments are specified:

a) A link segment optimized for use in automotive applications that supports up to four in-lineconnectors using a single twisted-pair copper cable for up to at least 15 m. This link segment isreferred to as link segment type A.

b) An optional link segment supporting up to four in-line connectors using a single twisted-pair coppercable for up to at least 40 m to support applications requiring additional physical reach, such asindustrial and automation controls and transportation (aircraft, railway, bus and heavy trucks). Thislink segment is referred to as link segment type B.

97.6.1 Link transmission parameters for link segment type A

The transmission characteristics for type A link segment are specified to support operation over automotivetemperature and electromagnetic conditions.

97.6.1.1 Insertion loss

The insertion loss of each type A link segment shall meet the values determined using Equation (97–16).

dB (97–16)

where

f is the frequency in MHz;

The insertion loss for the link segment calculated using Equation (97–16) accounts for the insertion loss of asingle twisted-pair copper cable and four in-line connectors within each link segment. The insertion loss isillustrated in Figure 97–36.

InsertionLoss f 0.0023f 0.5907 f 0.0639 f+ +

1 f 600

Figure 97–36—Insertion loss calculated using Equation (97–16)





97.6.1.2 Differential characteristic impedance

The nominal differential characteristic impedance of each type A link segment is 100 for all frequenciesbetween 1 MHz and 600 MHz.

97.6.1.3 Return loss

In order to limit the noise at the receiver due to impedance mismatches each type A link segment shall meetthe values determined using Equation (97–17) at all frequencies from 1 MHz to 600 MHz. The referenceimpedance for the return loss specification is 100

dB (97–17)

where


The return loss is illustrated in Figure 97–37.

97.6.1.4 Differential to common mode conversion

The balance of the type A link segment is characterized by the differential to common mode conversion.Each type A link segment shall meet the values determined using Equation (97–18) at all frequencies from10 MHz to 600 MHz.

Return Loss

19 1 f 1024 5log10f– 10 f 40

16 40 f 13037 10log10f– 130 f 400

11 400 f 600

1 f 600

Figure 97–37—Return loss calculated using Equation (97–17)





dB (97–18)

where


The function ConversionLoss(f) represents the mode conversion loss at frequency f. The conversion loss isillustrated in Figure 97–38.

The mode conversion specification applies to:

— Longitudinal conversion loss (LCL) with s-parameter SDC11/SDC22 and description common modeto differential mode return loss

— Transverse conversion loss (TCL) with s-parameter SCD11/SCD22 and description differentialmode to common mode return loss

— Longitudinal conversion transmission loss (LCTL) with s-parameter SDC12/SDC21 and descriptioncommon mode to differential mode insertion loss

— Transverse conversion transmission loss (TCTL) with s-parameter SCD12/SCD21 and descriptiondifferential mode to common mode insertion loss

For compliance to the specification measurements of LCL and LCTL are sufficient as LCL and TCL areconsidered reciprocal and LCTL and TCTL are considered reciprocal. The differential to common modeconversion loss test methodologies are specified in Annex 97A.

97.6.1.5 Maximum link delay

The propagation delay of a type A link segment shall not exceed 94 ns at all frequencies between 2 MHz and600 MHz.

ConversionLoss f 50 10 f 80 72 11.51log10f– 80 f 600

10 f 600

Figure 97–38—Conversion loss calculated using Equation (97–18)





97.6.2 Link transmission parameters for link segment type B

The transmission characteristics for type B link segment are specified to support applications requiringadditional reach such as industrial and automation controls and transportation (aircraft, railway, bus, andheavy trucks) for up to at least 40 m. Type B link segment may be shielded or screened, consistent with thespecification in 97.6.2.5 and 97.6.4.

97.6.2.1 Insertion loss

The insertion loss of each type B link segment shall meet the values determined using Equation (97–19).

dB (97–19)

where


The insertion loss is illustrated in Figure 97–39.

The insertion loss for the link segment calculated using Equation (97–19) accounts for the insertion loss of asingle twisted-pair copper cable and four in-line connectors within each link segment.

97.6.2.2 Differential characteristic impedance

The nominal differential characteristic impedance of each type B link segment is 100 for all frequenciesbetween 1 MHz and 600 MHz.

97.6.2.3 Return loss

In order to limit the noise at the receiver due to impedance mismatches each type B link segment shall meetthe values determined using Equation (97–20) at all frequencies from 1 MHz to 600 MHz. The referenceimpedance for the return loss specification is 100

InsertionLoss f 0.7131 f 0.0040f 0.1100 f 0.08 f 0.018 f+ + + +

1 f 600

Figure 97–39—Insertion loss calculated using Equation (97–19)





dB (97–20)

where


The return loss is illustrated in Figure 97–40.

97.6.2.4 Maximum link delay

The propagation delay of a type B link segment shall not exceed 234 ns at all frequencies between 2 MHzand 600 MHz.

97.6.2.5 Coupling attenuation

The coupling attenuation requirements of the type B link segment depend on the electromagnetic noiseenvironment. The requirements in Table 97–14 shall be met based on the local environment as described bythe electromagnetic classifications given in Table 97–15, E1, E2, or E3. The coupling attenuation is tested asspecified in IEC 62153-4–14.

Return Loss

19 1 f 1024 5log10 f – 10 f 40

16 40 f 13037 10log10 f – 130 f 400

11 400 f 600

1 f 600






97.6.3 Coupling parameters between type A link segments

Noise coupled between the disturbed type A link segment and the disturbing type A link segment is referredto as alien crosstalk noise. To ensure the total alien NEXT loss and alien FEXT loss coupled between type Alink segments is limited, multiple disturber alien near-end crosstalk (MDANEXT) loss and multipledisturber alien FEXT (MDAFEXT) loss is specified. The test methodologies are specified in Annex 97Aand Annex 97B.

97.6.3.1 Multiple disturber alien near-end crosstalk (MDANEXT) loss

In order to limit the alien crosstalk at the near end of a type A link segment, the differential pair-to-pair near-end crosstalk (NEXT) loss between the disturbed type A link segment and the disturbing type A linksegment is specified to meet the bit error ratio objective. To ensure the total alien NEXT coupled into a typeA link segment is limited, multiple disturber alien NEXT loss is specified as the power sum of the individualalien NEXT disturbers.

97.6.3.2 Multiple disturber power sum alien near-end crosstalk (PSANEXT) loss

PSANEXT loss is determined by summing the power of the individual pair-to-pair differential alien NEXTloss values over the frequency range 1 MHz to 600 MHz as follows in Equation (97–21).

dB (97–21)

Table 97–14—Coupling attenuation Type B link segment

Frequency(MHz)

Minimum (dB)

E1 E2 E3

30 f 600 80 – 20log10(f)(Max 40 dB)

90 – 20log10(f)(Max 50 dB)

100 – 20log10(f)(Max 60 dB)

Table 97–15—Electromagnetic classifications Type B link segment

ElectromagneticMinimum (dB)

E1 E2 E3

Radiated RF – AM

3 V/m at (80 MHz to 1000 MHz)3 V/m at (1400 MHz to 2000 MHz)1 V/m at (2000 MHz to 2700 MHz)



Conducted RF 3 V at 150 kHz to 80 MHz 3 V at 150 kHz to 80 MHz 10 V at 150 kHz to 80 MHz

PSANEXTlossN f 10log10 10

-AN f j N

10------------------------

j 1=

m

–





where the function AN(f)j,N represents the magnitude (expressed in dB) of the alien NEXT loss at frequencyf of the disturbing type A link segment j (1 to m) for the disturbed type A link segment N.

The power sum ANEXT loss between a disturbed type A link segment and the disturbing type A linksegment shall meet the values determined using Equation (97–22).

dB (97–22)

where f is the frequency in MHz

PSANEXT is illustrated in Figure 97–41.

97.6.3.3 Multiple disturber alien far-end crosstalk (MDAFEXT) loss

In order to limit the alien crosstalk at the far-end of a type A link segment, the differential pair-to-pair alienfar-end crosstalk (FEXT) loss between the disturbed type A link segment and the disturbing type A linksegment is specified to meet the bit error ratio objective. To ensure the total alien FEXT coupled into a typeA link segment, multiple disturber attenuation to crosstalk ratio far-end ACRF is specified as the power sumof the individual alien ACRF disturbers.

97.6.3.4 Multiple disturber power sum alien attenuation crosstalk ratio far-end (PSAACRF)

PSAACRF is determined by summing the power of the individual pair-to-pair differential alien ACRFvalues over the frequency range 1 MHz to 600 MHz as follows in Equation (97–23).

PSANEXTloss f 54 10log10

f100--------- – 1 f 100

54 15log10f

100--------- – 6

f 100–400

---------------- – 100 f 600

Figure 97–41—PSANEXT calculated using Equation (97–22)





dB (97–23)

where the function AF(f)j,N represents the magnitude (expressed in dB) of the alien ACRF of the disturbingtype A link segment j (1 to m) for disturbed type A link segment N.

The power sum AACRF between a disturbed type A link segment and the disturbing type A link segmentshall meet the values determined using Equation (97–24).

dB (97–24)

where f is the frequency in MHz

PSAACRF is illustrated in Figure 97–42.

97.6.4 Coupling parameters between type B link segments

Noise coupled between the disturbed type B link segment and the disturbing type B link segment is referredto as alien crosstalk noise. To ensure the total alien NEXT loss and alien FEXT loss coupled between type Blink segments is limited, multiple disturber alien near-end crosstalk (MDANEXT) loss and multipledisturber alien FEXT (MDAFEXT) loss is specified.

97.6.4.1 Multiple disturber alien near-end crosstalk (MDANEXT) loss

In order to limit the alien crosstalk at the near end of a type B link segment, the differential pair-to-pairnear-end crosstalk (NEXT) loss between the disturbed type B link segment and the disturbing type B linksegment is specified to meet the bit error ratio objective. To ensure the total alien NEXT coupled into a type

PSAACRFN f 10log10 10

-AF f j N

10-----------------------

j 1=

m

–

PSAACRF f 20log10 10

10– log100.15 38.2 20log10f

100--------- –+

20–----------------------------------------------------------------------------------------------

4 10

67 20log10f

100--------- –

20–---------------------------------------------

+

–

Figure 97–42—PSAACRF calculated using Equation (97–24)





B link segment is limited, multiple disturber alien NEXT loss is specified as the power sum of the individualalien NEXT disturbers.

97.6.4.2 Multiple disturber power sum alien near-end crosstalk (PSANEXT) loss

PSANEXT loss is determined by summing the power of the individual pair-to-pair differential alien NEXTloss values over the frequency range 1 MHz to 600 MHz as follows in Equation (97–25).

dB (97–25)

where the function AN(f)j,N represents the magnitude (expressed in dB) of the alien NEXT loss at frequencyf of the disturbing type B link segment j (1 to m) for the disturbed type B link segment N.

The power sum ANEXT loss between a disturbed type B link segment and the disturbing type B linksegment shall meet the values determined using Equation (97–26).

dB (97–26)

where


97.6.4.3 Multiple disturber alien far-end crosstalk (MDAFEXT) loss

In order to limit the alien crosstalk at the far-end of a type B link segment, the differential pair-to-pair alienfar-end crosstalk (FEXT) loss between the disturbed type B link segment and the disturbing type B linksegment is specified to meet the bit error ratio objective. To ensure the total alien FEXT coupled into a typeB link segment, multiple disturber attenuation to crosstalk ratio far-end ACRF is specified as the power sumof the individual alien ACRF disturbers.

97.6.4.4 Multiple disturber power sum alien attenuation crosstalk ratio far-end (PSAACRF)

PSAACRF is determined by summing the power of the individual pair-to-pair differential alien ACRFvalues over the frequency range 1 MHz to 600 MHz as follows in Equation (97–27).

dB (97–27)

where the function AF(f)j,N represents the magnitude (expressed in dB) of the alien ACRF of the disturbingtype B link segment j (1 to m) for disturbed type B link segment N.

The power sum AACRF between a disturbed type B link segment and the disturbing type B link segmentshall meet the values determined using Equation (97–28) or 70 dB, whichever is less.

dB (97–28)

where


PSANEXTN f 10log10 10

-AN f j N

10------------------------

j 1=

m

–

PSANEXT f 65

1 f 600

PSAACRFN f 10log10 10

-AF f j N

10-----------------------

j 1=

m

–

PSAACRF f 61 20log10 f 100 –

1 f 600





97.7 Media Dependent Interface (MDI)

97.7.1 MDI connectors

The mechanical interface to the balanced cabling is a 2-pin connector or 2 pins of a multi-pin connector.Further specification of the mechanical interface is beyond the scope of this standard.

97.7.2 MDI electrical specification

The electrical requirements specified in 97.5.3 and 97.5.4 shall be met when the PHY is connected to theMDI connector mated with a specified balanced twisted-pair cable connector

97.7.2.1 MDI return loss

The differential impedance at the MDI (see Figure 97–43) for each transmit/receive channel shall be suchthat any reflection (due to differential signals incident upon the MDI with a test port having a differentialimpedance of 100 ) is attenuated relative to the incident signal per Equation (97–29).

dB (97–29)

where f is the frequency in MHz.

Return Loss f

18 18 20f

------10

log– 2 f 20

18 20 f 100

18 16.7 f100---------

10log– 100 f 600






97.7.2.2 MDI mode conversion loss

Mode conversion LCL (Sdc11) or TCL (Scd11) of the PHY measured at MDI shall meet the valuesdetermined using Equation (97–30) at all frequencies from 10 MHz to 600 MHz.

dB (97–30)

where


97.7.3 MDI fault tolerance

See 96.8.3.

97.8 Management Interfaces

1000BASE-T1 makes extensive use of the management functions that may be provided by the MDIO(Clause 45), and the communication and self-configuration functions provided by the optional Auto-Negotiation (Clause 98).

97.8.1 Optional Support for Auto-Negotiation

If Auto-Negotiation is supported and enabled the mechanism described in Clause 98 shall be used.

Auto-Negotiation is performed as part of the initial setup of the link, and allows the PHYs at each end toadvertise their capabilities and to automatically select the operating mode for communication on the link.Auto-Negotiation signaling is used for the following primary purposes for 1000BASE-T1:

a) To negotiate that the PHY is capable of supporting 1000BASE-T1 transmission

b) To determine the MASTER-SLAVE relationship between the PHYs at each end of the link

ConversionLoss f 55 10 f 80 77 11.51log10f– 80 f 600

10 f 600

Figure 97–44—MDI mode conversion loss calculated using Equation (97–30)





97.9 Environmental specifications

97.9.1 General safety

All equipment subject to this clause shall conform to IEC 60950-1. All equipment subject to this clause andintended for motor vehicle applications shall conform to ISO 26262. All equipment subject to this clausemay be additionally required to conform to any applicable local, state, or national motor vehicle standards oras agreed to between the customer and supplier.

97.9.2 Network safety

All cabling and equipment subject to this clause is expected to be mechanically and electrically secure in aprofessional manner. In automotive applications, all 1000BASE-T1 cabling is routed in way to providemaximum protection by the motor vehicle sheet metal and structural components, following SAE J1292,ISO 14229, and ISO 15764.

97.9.2.1 Environmental safety

All equipment subject to this clause, when used in the automotive environment, shall conform to thepotential environmental stresses with respect to their mounting location, as defined in the followingspecifications:

a) General loads: ISO 16750–1

b) Electrical loads: ISO 16750-2, ISO 7637-2:2008, and ISO 8820–1

c) Mechanical loads: ISO 16750-3, ASTM D4728, and ISO 12103–1

d) Climatic loads: ISO 16750-4 and IEC 60068-2–1/27/30/38/52/64/78

e) Chemical loads: ISO 167540-5 and ISO 20653

Automotive environmental conditions are generally more severe than those found in many commercial andindustrial environments. The target automotive, industrial, or commercial environment(s) require carefulanalysis prior to implementation.

97.9.2.2 Electromagnetic compatibility

A system integrating the 1000BASE-T1 PHY shall comply with all applicable local and national codes. Inaddition, the system may need to comply with more stringent requirements as agreed upon betweencustomer and supplier, for the limitation of electromagnetic interference. A 1000BASE-T1 PHY shall betested according to IEC CISPR 25 test methods defined to measure the PHY’s EMC performance in terms ofradio frequency (RF) immunity and RF emissions. When used in an automotive environment, a1000BASE-T1 PHY is expected to meet the following motor vehicle EMC requirements:

a) Radiated/conducted emissions: CISPR 25, IEC 61967–1/4, and IEC 61000-4-21

b) Radiated/conducted immunity: ISO 11452, IEC 62132–1/4, and IEC 61000-4-21

c) Electrostatic discharge: ISO 10605 and IEC 61000-4-2/3

d) Electrical disturbances: IEC 62215-3 and ISO 7637-2/3

Exact test setup and test limit values may be adapted to each specific application, subject to agreementbetween the customer and the supplier.

97.10 Delay constraints

In full duplex mode, predictable operation of the MAC Control PAUSE operation (Clause 31, Annex 31B)also demands that there be an upper bound on the propagation delays through the network. This implies thatMAC, MAC Control sublayer, and PHY implementers conform to certain delay maxima, and that network





planners and administrators conform to constraints regarding the cable topology and concatenation ofdevices.

The sum of the transmit and receive data delays for an implementation of a 1000BASE-T1 PHY shall notexceed 7168 bit times (14 pause_quanta or 7168 ns). Transmit data delay is measured from the input of agiven unit of data at the GMII to the presentation of the same unit of data by the PHY to the MDI. Receivedata delay is measured from the input of a given unit of data at the MDI to the presentation of the same unitof data by the PHY to the GMII.

NOTE—The physical medium interconnecting two PHYs introduces additional delay in a link.





97.11 Protocol implementation conformance statement (PICS) proforma for Clause 97, Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium, type 1000BASE-T14

97.11.1 Introduction

The supplier of a protocol implementation that is claimed to conform to Clause 97, Physical CodingSublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium, type 1000BASE-T1, shall complete the following protocol implementation conformance statement (PICS) proforma. Adetailed description of the symbols used in the PICS proforma, along with instructions for completing thePICS proforma, can be found in Clause 21.

97.11.2 Identification

97.11.2.1 Implementation identification

97.11.2.2 Protocol summary


Supplier

Contact point for inquiries about the PICS

Implementation Name(s) and Version(s)

Other information necessary for full identification—e.g., name(s) and version(s) for machines and/or operating systems; System Name(s)

NOTE 1—Only the first three items are required for all implementations; other information may be completed asappropriate in meeting the requirements for the identification.

NOTE 2—The terms Name and Version should be interpreted appropriately to correspond with a supplier’sterminology (e.g., Type, Series, Model).

Identification of protocol standard IEEE Std 802.3bp-2016, Clause 97, Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium, type 1000BASE-T1

Identification of amendments and corrigenda to this PICS proforma that have been completed as part of this PICS

Have any Exception items been required? No [ ] Yes [ ](See Clause 21; the answer Yes means that the implementation does not conform to IEEE Std 802.3bp-2016.)

Date of Statement





97.11.3 Major capabilities/options

97.11.4 General


GMII PHY associated with GMII 97.1 Interface is supported O Yes [ ]No [ ]

*EEE EEE capability 97.1.2.3 O Yes [ ]No [ ]

PCS 1000BASE-T1 PCS 97.3 M Yes [ ]

PMA 1000BASE-T1 PMA 97.4 M Yes [ ]

AN Auto-negotiation 97.1, 98 O Yes [ ]No [ ]

*CHNL Channel 97.6 Channel specification not applicable to a PHY manufacturer

O Yes [ ]No [ ]

*MDIO MDIO Capability 45.1 Register and Interface supported

O Yes [ ]No [ ]

*AUTO Automotive environment installation

97.9 O Yes [ ]No [ ]

*LSTB Operation on link segment type B

97.5.4.1 Optional O Yes [ ]No [ ]


G1 MASTER-SLAVE relation-ship when Auto-Negotiation is not used

97.1.2 Established by management of hardware configuration of the PHYs

M Yes [ ]

G2 Test circuit accuracy 97.1.5 Within ±1% unless otherwise stated

M Yes [ ]

G3 Sum of the transmit and receive data delays

97.10 Not exceed 7168 bit times (14 pause_quanta or 7168 ns)

M Yes [ ]

G4 Auto-negotiation 97.8.1 If supported per Clause 98 O Yes [ ]No [ ]





97.11.5 Physical Coding Sublayer (PCS)


PCT1 PCS Transmit state diagram 97.3.2.2 Conform to Figure 97–14 M Yes [ ]

PCT2 PCS Transmit bit ordering 97.3.2.2 Conform to Figure 97–5 and Figure 97–7

M Yes [ ]

PCT3 PCS data transmission 97.3.2.2 45 80B/81B blocks are aggre-gated, encoded by a PHY frame encode, and then scrambled by a PCS scrambler

M Yes [ ]

PCT4 PCS data encoding 97.3.2.2 Frames are encoded into a sequence of PAM3 symbols and transferred to the PMA

M Yes [ ]

PCT5 Transmitted Control codes 97.3.2.2.6 Values not in Table 97–1 are not to be transmitted

M Yes [ ]

PCT5a Received Control codes 97.3.2.2.6 Values not in Table 97–1 are treated as an error if received

M Yes [ ]

PCT6 Idle characters 97.3.2.2.7 Not be added within a data frame

M Yes [ ]

PCT7 LP_IDLE characters 97.3.2.2.8 Not be added within a data frame

M Yes [ ]

PCT8 EEE IDLE conversion 97.3.2.2.8 Convert LP_IDLE to IDLE if EEE is not supported

EEE:M Yes [ ]N/A [ ]

PCT9 FEC 97.3.2.2.11 Reed-Solomon code (450,406) M Yes [ ]

PCT10 RS-FEC encoder 97.3.2.2.11 Follow the bit order described in 97.3.2.2.3

M Yes [ ]

PCT11 Parity calculation 97.3.2.2.11 Produce the same result as the shift register implementation shown in Figure 97–8

M Yes [ ]

PCT12 RS-FEC encoder shift register initialization

97.3.2.2.11 Set to zero before the parity calculation begins

M Yes [ ]

PCT13 PCS MASTER scrambler 97.3.2.2.12 Conform to Figure 97–9 M Yes [ ]

PCT14 PCS SLAVE scrambler 97.3.2.2.12 Conform to Figure 97–9 M Yes [ ]

PCT15 PCS scrambler seed values 97.3.2.2.12 Non-zero and transmitted during the InfoField exchange

M Yes [ ]

PCT16 EEE compliant PHYs 97.3.2.2.15 Implement Figure 97–14 EEE:M Yes [ ]N/A [ ]

PCT17 EEE RS partial IDLE 97.3.2.2.15 Transmit no PHY frames partially filled with LP_IDLES


PCT18 EEE without SEND_N 97.3.2.2.15 lpi_tx_mode variable is ignored when the PMA_TX-MODE.indication message does not have the values SEND_N






97.11.6 PCS Receive functions

PCT19 EEE NORMAL 97.3.2.2.15 The PCS passes coded data to the PMA via the PMA_UNIT-DATA.request primitive when the lpi_tx_mode variable takes the value NORMAL and when the PMA asserts SEND_N


PCT20 EEE QUIET 97.3.2.2.15 The PCS passes zeros to the PMA via the PMA_UNIT-DATA.request primitive when the lpi_tx_mode variable takes the value QUIET and when the PMA asserts SEND_N


PCT21 EEE REFRESH 97.3.2.2.15 The PCS passes zero data encoded through PCS data path to the PMA via the PMA_UNITDATA.request primitive when the lpi_tx_mode variable takes the value REFRESH and when the PMA asserts SEND_N


PCT22 Wake frame 97.3.2.2.15 Be sent only during alternating PHY frame counts


PCT23 PCS reset execution 97.3.1 When power for the device containing the PMA has reached the operating state, or on the receipt of a request for reset from the management entity

M Yes [ ]


PCR1 PCS receive state diagram 97.3.2.3 Conform to Figure 97–12 M Yes [ ]

PCR2 PCS Receive bit ordering 97.3.2.3 Conform to Figure 97–6 M Yes [ ]

PCR3 PAM3 stream 97.3.2.3.1 Form stream from PMA_UNITDATA.indication primitive by concatenating requests in order from rx_data<0> to rx_data<2699>

M Yes [ ]

PCR4 PCS descrambler 97.3.2.3 Descramble the data stream for generation of RXD<7:0> to the GMII

M Yes [ ]

PCR5 MASTER side-stream descrambler

97.3.2.3.2 Equation (97–4) M Yes [ ]

PCR6 SLAVE side-stream descrambler

97.3.2.3.2 Equation (97–3) M Yes [ ]






97.11.7 PCS loopback

PCR7 Transmit PCS test pattern mode

97.3.3 Transmit continuously as illustrated in Figure 97–5

M Yes [ ]

PCR8 Receive PCS test pattern mode 97.3.3 Receive continuously as illustrated in Figure 97–6

M Yes [ ]

PCR9 MASTER side-stream scrambler

97.3.4 Equation (97–5) M Yes [ ]

PCR10 SLAVE side-stream scrambler 97.3.4 Equation (97–6) M Yes [ ]

PCR11 Initialized scrambler state 97.3.4 Never all zeros M Yes [ ]

PCR12 Scramble status 97.3.4.3 Acquire and report descram-bler state synchronization via scr_status

M Yes [ ]

PCR13 DECODE function 97.3.6.2.3 Decode the block as specified in 97.3.2.2.2

M Yes [ ]

PCR14 ENCODE function 97.3.6.2.3 Encode the block as specified in 97.3.2.2.2

M Yes [ ]

PCR15 Encode function encode LPI_IDLE

97.3.6.2.3 Only in SEND_LPI state EEE:M Yes [ ]N/A [ ]

PCR16 PCS Receive, RFER monitor, and PCS Transmit state diagrams

97.3.6.4 Figure 97–12, Figure 97–13, and Figure 97–14

M Yes [ ]


PCO1 PCS loopback mode 97.3.7.3 Enabled when MDIO register 3.2304.14 is set to a one.

MDIO:M Yes [ ]

PCO2 PCS loopback enabled 97.3.7.3 PCS accepts data on the transmit path from the GMII and return it on the receive path to the GMII when in loopback mode when in loopback mode

M Yes [ ]

PCO3 PCS loopback enabled 97.3.7.3 Transmit a continuous stream of GMII data to the 81B encoder and then to PMA sublayer and ignore all data presented to it by the PMA sublayer

M Yes [ ]






97.11.8 Physical Medium Attachment (PMA)


PMF1 PMA Reset function 97.4.2.1 M Yes [ ]

PMF2 PMA Transmit function 97.4.2.2 Continuously transmit onto the MDI pulses modulated by the symbols given by tx_symb after processing with optional transmit filtering.

M Yes [ ]

PMF3 Signals generated by PMA transmit

97.4.2.2 Comply with 97.5 M Yes [ ]

PMF4 MASTER TX_TCLK source 97.4.2.2 Local clock source while meeting the transmit jitter requirements of 97.5.3.3

M Yes [ ]

PMF5 The MASTER-SLAVE relationship

97.4.2.2 Include loop timing M Yes [ ]

PMF6 SLAVE TX_TCLK source 97.4.2.2 Recovered clock of 97.4.2.8 while meeting the jitter requirements of 97.5.3.3.

M Yes [ ]

PMF7 PMA_transmit_disable variable

97.4.2.2.1 When set to true, turn off the transmitter so that the trans-mitter Average Launch Power of the Transmitter is less than –53 dBm

M Yes [ ]

PMF8 Quality of rx_symb symbols 97.4.2.3 Allow RFER of less than 3.6 10–7 after RS-FEC decoding, over a channel meeting the requirements of 97.6

M Yes [ ]

PMF9 PMA receive fault function 97.4.2.3 Contribute to the receive fault bit specified in 45.2.1.134.6

MDIO:O Yes [ ]N/A [ ]

PMF10 PHY Control 97.4.2.4 Comply with Figure 97–26 M Yes [ ]

PMF11 12-octet InfoField 97.4.2.4 Include the fields in 97.4.2.4.2 through 97.4.2.4.8

M Yes [ ]

PMF12 Each unique InfoField 97.4.2.4 Transmitted at least 256 times M Yes [ ]

PMF13 InfoField Reserved bits 97.4.2.4.1 Set to zero on transmit and ignored when received by the link partner

M Yes [ ]

PMF14 Start of Frame Delimiter 97.4.2.4.2 Hexadecimal value 0xB-BA700

M Yes [ ]

PMF15 PMA_state<7:6> 97.4.2.4.4 Communicate the state of the transmitting transceiver to the link partner

M Yes [ ]

PMF16 Any Message Field value not listed in Table 97–7 or Table 97–8

97.4.2.4.4 Not be transmitted and ignored at the receiver

M Yes [ ]





PMF17 The Message Field setting for the first transmitted PMA frame

97.4.2.4.4 First row of Table 97–7 for the MASTER and the first or second row of Table 97–8 for the SLAVE

M Yes [ ]

PMF18 Indicate support of optional capabilities

97.4.2.4.5 Set the corresponding capability bits

M Yes [ ]

PMF19 State of the scrambler 97.4.2.4.5 S14:S0 at the first bit of the first PHY frame when the partial PHY frame counter equals to the DataSwPFC24 value

M Yes [ ]

PMF20 Seed S<14:0> 97.4.2.4.5 Not all zeros M Yes [ ]

PMF21 DataSwPFC24 97.4.2.4.6 Set to an integer multiple of 15

M Yes [ ]

PMF22 CRC16 (2 octets) 97.4.2.4.8 Implement the CRC16 polynomial (x+1)(x15+x+1) of the previous 7 octets

M Yes [ ]

PMF23 CRC16 97.4.2.4.8 Figure 97–23 M Yes [ ]

PMF24 CRC16 delay elements 97.4.2.4.8 Initialized to zero M Yes [ ]

PMF25 Start-up sequence 97.4.2.4.10 Comply with Figure 97–26 M Yes [ ]

PMF26 Enable EEE capability 97.4.2.4.10 Enabled if both PHYs set EEEen = 1


PMF27 Set en_slave_tx = 1 97.4.2.4.10 After the MASTER has sufficiently converged the necessary circuitry, allowing the SLAVE to transition to TRAINING

M Yes [ ]

PMF28 Enable 1000BASE-T1 OAM capability

97.4.2.4.10 Enabled only if both PHYs set OAMen = 1

M Yes [ ]

PMF29 SLAVE PHY TRAINING 97.4.2.4.10 Align transmit 81B-RS frame within +0/–1 partial PHY frames of the MASTER

M Yes [ ]

PMF30 SLAVE InfoField partial PHY frame Count

97.4.2.4.10 Match MASTER InfoField partial PHY frame Count for the aligned frame

M Yes [ ]

PMF31 Link Monitor function 97.4.2.5 Comply with Figure 97–27 M Yes [ ]

PMF32 Refresh monitor function 97.4.3 EEE:M Yes [ ]N/A [ ]

PMF33 Set PMA_refresh_status to FAIL

97.4.3 When Refresh is not detected within a moving window of 50 Q/R cycles


PMF34 Set PMA_refresh_status to OK

97.4.3 When Link Monitor state diagram enters LINK_UP state


PMF35 Clock Recovery function 97.4.2.8 Provide a clock suitable for signal sampling so that RS FER is achieved

M Yes [ ]






97.11.9 PMA electrical specifications

PMF36 maxwait_timer 97.4.4.2 Expire 97.5 ms ± 0.5 ms after being started

M Yes [ ]

PMF37 minwait_timer 97.4.4.2 Expire 975 µs ± 50 µs after being started

M Yes [ ]

PMF38 sigdet_wait_timer 97.4.2.6.2 Expires 4 µs ± 0.1 µs after being started

M Yes [ ]

PMF39 send_s_timer 97.4.2.6.2 Expires 1.0 µs ± 0.04 µs after being started

M Yes [ ]

PMF40 send_s_sigdet 97.4.2.6.1 Set to false no later than 1 µs after the signal goes quiet on the MDI

M Yes [ ]

PMF41 Auto-Negotiation function used for PHY synchronization

97.4.2.6 M Yes [ ]

PMF42 Function of Figure 97–25 97.4.2.6 Used to synchronize 1000BASE-T1 PHYs prior to the 1000BASE-T1 link training

M Yes [ ]

PMF43 PN sequence generator shift registers reset

97.4.2.6 The PN sequence generator shift registers are reset to a non-zero value upon entering into the TRANSMIT_DISABLE state (see Figure 97–25)

M Yes [ ]

PMF44a SLAVE PN sequencegenerator

97.4.2.6 See Equation (97–9) M Yes [ ]

PMF44b MASTER PN sequencegenerator

97.4.2.6 See Equation (97–8) M Yes [ ]

PMF45 The next Message Field set-ting

97.4.2.4.4 Equal to the same Message Field setting or the Message Field setting corresponding to a row below the current set-ting

M Yes [ ]


PME1 DPI and 150 emission tests 97.5.1 Used to establish a baseline for PHY EMC performance

M Yes [ ]

PME2 DPI method of IEC 62132-4 97.5.1.1 Used to test the sensitivity of the PMA receiver to radio frequency noise

M Yes [ ]

PME3 150 direct coupling method of IEC 61967-4

97.5.1.2 Used to test the conducted CM emission of the PMA transmitter to its electrical environment

M Yes [ ]

PME4 Test modes 97.5.2 Provided to allow for testing the transmitter

M Yes [ ]






PME5 Test modes 97.5.2 Enabled by setting control register 1.2308.15:13

MDIO:M

Yes [ ]N/A [ ]

PME6 Test mode change data only 97.5.2 The test modes only change the data symbols provided to the transmitter circuitry and do not alter the electrical and jitter characteristics of the transmitter and receiver from those of normal (non-test mode) operation.

M Yes [ ]

PME7 Test mode 1 97.5.2 Provide access to a frequency reduced version of the trans-mit symbol clock or TX_TCLK125 when in test mode 1

M Yes [ ]

PME8 Test mode 2 97.5.2 Transmit three {+1} symbols followed by three {–1} symbols continually

M Yes [ ]

PME9 Test mode 3 97.5.2 Transmit three {+1} symbols followed by three {–1} symbols continually

M Yes [ ]

PME10 Test mode 4 97.5.2 Transmit the sequence of symbols generated by the scrambler generator polynomial per Equation (97–12) when in test mode 4

M Yes [ ]

PME10a Test Mode 4 transmit clock 97.5.2 750 MHz ± 0.01% clock when in MASTER timing mode

M Yes [ ]

PME10b Test mode 4 signal level 97.5.2 Same as non-test mode M Yes [ ]

PME10c Test mode 4 Sequence genera-tor clock

97.5.2 2/750 MHz M Yes [ ]

PME10d Test mode 4 ternary symbols T0n and T1n

97.5.2 Generated from bits x0n, x1n, and x2n of the test mode 4 sequence generator

M Yes [ ]

PME11 Test mode 5 97.5.2 Transmit as in non-test operation and in the MAS-TER data mode with data set to normal Inter-Frame idle signals

M Yes [ ]

PME12 Test mode 6 97.5.2 Transmit fifteen {+1} sym-bols followed by fifteen {–1} symbols continually

M Yes [ ]

PME12a Test fixtures 97.5.2.1 Per Figure 97–29, Figure 97–30, Figure 97–31, Figure 97–32, and Figure 97–33 or equivalent

M Yes [ ]






PME12b Disturbing signal characteris-tics

97.5.2.1 Sinusoidal, amplitude of 3.6 V peak-to-peak differential, and frequency of one-sixth the symbol rate (125 MHz) synchronous with the test pattern

M Yes [ ]

PME13 Tolerance of resistors used in test fixtures

97.5.2.1 ± 0.1% M Yes [ ]

PME14 Disturbing signal generator 97.5.2.1 Have sufficient linearity and range so it does not introduce any appreciable distortion

M Yes [ ]

PME15 Coupling 97.5.3 Operate with AC coupling to the MDI

M Yes [ ]

PME16 Resistive differential load 97.5.3 Meet electrical requirements of this clause with a 100 resistive differential load connected to transmitter output if load is not specified

M Yes [ ]

PME17 Magnitude of both the positive and negative droop

97.5.3.1 Less than 10% measured with respect to an initial value at 4 ns after the zero crossing and a final value at 16 ns after the zero crossing

M Yes [ ]

ME17a Transmitter distortion signal capture

97.5.3.2 At least 40 µs long and sampled at a rate of at least 7.5 Gs/s (10 times the trans-mit symbol rate of 750 Ms/s)

M Yes [ ]

PME18 Transmitter distortion 97.5.3.2 Less than 15 mV for at least 10 measured equally spaced phases

M Yes [ ]

PME19 Transmitter distortion test mode 4 capture

97.5.3.2 Minimum of 40 µs long and minimum sampling rate of 7.5 Gs/s

M Yes [ ]

PME20 MASTER TX_TCLK125 jit-ter RMS

97.5.3.3 Less than 5 ps RMS M Yes [ ]

PME21 MASTER TX_TCLK125 jit-ter Peak-to-Peak

97.5.3.3 Less than 50 ps peak-to-peak M Yes [ ]

PME22 SLAVE TX_TCLK125 jitter RMS

97.5.3.3 Less than 10 ps RMS M Yes [ ]

PME23 SLAVE TX_TCLK125 jitter Peak-to-Peak

97.5.3.3 Less than 100 ps peak-to-peak M Yes [ ]

PME23b TX_TCLK125 jitter measurement bandwidth

97.5.3.3 Larger than 2 MHz M Yes [ ]

PME24 Reference clock 97.5.3.3 Reference clock is continuous when transitioning into or out of LPI mode


PME25 MDI output jitter RMS 97.5.3.3 Less than 5 ps RMS M Yes [ ]

PME25a MDI output jitter Peak to Peak 97.5.3.3 Less than 50 ps RMS M Yes [ ]






97.11.10 MDI electrical requirements

97.11.10.1 Characteristics of the link segment

PME25b MDI jitter measurement band-width

97.5.3.3 Larger than 2 MHz M Yes [ ]

PME26 Transmit power in test mode 5 97.5.3.4 Less than 5 dBm M Yes [ ]

PME27 Power spectral density in test mode 5

97.5.3.4 Between the upper and lower masks specified in Equation (97–14) and Equation (97–15), when measured into a 100 load using the test fixture 5 shown in Figure 97–33

M Yes [ ]

PME28 TX_TCLK125 jitter measurement

97.5.3.3 Measured over an interval of 1 ms ± 10%

M Yes [ ]


PMI1 Transmit differential signal 97.5.3.5 Less than 1.30 V peak-to-peak for all transmit modes when measured with 100 reference termination

M Yes [ ]

PMI2 MASTER PHY symbol trans-mission rate

97.5.3.6 Within the range 750 MHz ± 100 ppm

M Yes [ ]

PMI3 LPI mode the short-term rate of frequency variation

97.5.3.6 Less than 0.1 ppm/second EEE:M Yes [ ]N/A [ ]

PMI4 Receiver differential input sig-nals

97.5.4.1 Frame loss ratio less than 10–7 for 125-octet frames

M Yes [ ]

PMI5 Frame loss ratio for operation on link segment type B

97.5.4.1 Met for link segments specified at 97.6.2 and 97.6.4

LSTB:M Yes [ ]N/A [ ]


LKS2 Insertion loss of each type A link segment

97.6.1.1 Equation (97–16) CHNL:M Yes [ ]N/A [ ]

LKS3 Return loss (with 100 reference impedance) of each type A link segment


LKS4 Differential to common mode conversion of each type A link segment

97.6.1.4 Equation (97–18) for all frequencies from 10 MHz to 600 MHz

CHNL:M Yes [ ]N/A [ ]

LKS5 Maximum link delay for type A link segment

97.6.1.5 Not exceed 94 ns at all frequencies between 2 MHz and 600 MHz







LKS6 Insertion loss of each type B link segment


LKS7 Return loss (with 100 reference impedance) of each type B link segment


LKS8 Maximum link delay for type B link segment

97.6.2.4 Not exceed 234 ns at all frequencies between 2 MHz and 600 MHz


LKS9 Coupling attenuation of the type B link segment

97.6.2.5 Table 97–14 CHNL:M Yes [ ]N/A [ ]

LKS10

Power sum ANEXT loss between a disturbed type A link segment and the disturb-ing type A link segment


LKS11 Power sum AACRF between a disturbed type A link seg-ment and the disturbing type A link segment


LKS12

Power sum ANEXT loss between a disturbed type B link segment and the disturb-ing type B link segment


LKS13

Power sum AACRF between a disturbed type B link seg-ment and the disturbing type B link segment

97.6.4.4 The lesser of Equation (97–28) and 70 dB







97.11.11 MDI Requirements

97.11.12 EEE capability requirements


MDI1 Symbol response 97.4.3.1 Comply with 97.5 M Yes [ ]

MDI2 MDI electrical specification 97.7.2 Meet the electrical requirements specified in 97.5.3 and 97.5.4 when the PHY is connected to the MDI connector mated with a specified balanced twisted-pair cable connector

M Yes [ ]

MDI3 Return loss 97.7.2.1 Equation (97–29) M Yes [ ]

MDI4 MDI wire pair short circuit 96.8.3 Under all operating conditions withstand without damage the application of short circuits of any wire to the other wire of the same pair or ground potential or positive voltages of up to 50 V dc with the source current limited to 150 mA, as per Table 96–6, for an indefinite period of time

M Yes [ ]

MDI5 Operation after short circuit 96.8.3 Resume normal operation M Yes [ ]

MDI6 MDI wire pair transients and ESD

96.8.3 Under all operating conditions, withstand without damage high voltage transient noise and ESD per application requirements

M Yes [ ]

MD17 MDI mode conversion loss 97.7.2.2 Equation (97–30) M Yes [ ]


EEE1 Transition to and from LPI mode

97.1.2.3 Cause no data frames be lost or corrupted.


EEE2 Normal power resumption 97.1.2.3 Resume normal power mode on the PHY frame following a PCS transmission of a wake frame


EEE3 LPI synchronization 97.3.5.1 Synchronize refresh intervals during LPI mode


EEE4 Partial PHY frame count syn-chronization

97.3.5.1 When SLAVE, synchronize partial PHY frame count to MASTER’s partial PHY frame count within 1 partial PHY frame


EEE5 tx_refresh_active and tx_wake_start signals

97.3.5.1 Derive tx_refresh_active and tx_wake_start signals from the transmitted PHY frames


EEE6 Quiet period 97.3.5.2 Transmit PAM3 symbol zero on to the MDI






97.11.13 Environmental specifications


ES1 General safety 97.9.1 Conforms to IEC 60950-1 (for IT and motor vehicle applications) and to ISO 26262 (for motor vehicle applications only, if required by the given application)

M Yes [ ]

ES1a Conforms to ISO 26262 97.9.1 If intended for motor vehicle applications

AUTO:M

Yes [ ]N/A[ ]

ES2 Environmental safety 97.9.2.1 Conform to the potential environmental stresses with respect to their mounting location, as defined in: ISO 16750-1, ISO 16750-2, ISO 17637-2:2008, ISO 8820-1, ISO 16750-3, ASTM D4728, ISO 12103-1, ISO 16750-4, IEC 60068-2–1/27/30/38/52/64/78, ISO 167540-5, and ISO 20653

AUTO:M

Yes [ ]N/A[ ]

ES3 Electromagnetic compatibility: local and national codes

97.9.2.2 Compliance with applicable local and national codes for the limitation of electromagnetic interference

M Yes [ ]

ES4 Electromagnetic compatibility: EMC test methods

97.9.2.2 Tested according to IEC CISPR 25 test methods defined to measure the PHY’s EMC performance

M Yes [ ]

ES5 Electromagnetic compatibility: motor vehicle EMC require-ments

97.9.2.2 Meet the following motor vehicle EMC requirements: CISPR 25, IEC 61967–1/4, IEC 61000-4-21, ISO 11452, IEC 62132–1/4, IEC 61000-4-21, ISO 10605, IEC 61000-4-2/3, IEC 62215-3, ISO 7637-2/3

AUTO:M

Yes [ ]N/A[ ]





98. Auto-Negotiation for single differential-pair media

98.1 Overview

98.1.1 Scope

Clause 98 describes the single twisted-pair Auto-Negotiation function that allows a device to advertiseenhanced modes of operation it possesses to a device at the remote end of a link segment and to detectcorresponding enhanced operational modes that the other device may be advertising. Annex 98A describesthe Selector Field that is used by Auto-Negotiation to identify the type of message being sent.

The objective of the single twisted-pair Auto-Negotiation function is to provide the means to exchangeinformation between two devices that share a link segment and to automatically configure both devices totake maximum advantage of their abilities. It has the additional objective of providing a commonsynchronization time between two devices prior to link training.

Single twisted-pair Auto-Negotiation is performed using differential Manchester encoding (DME) pages.DME provides a DC balanced signal. DME does not add packet or upper layer overhead to the networkdevices. DME is transferred in a half-duplex manner over the single twisted-pair copper cable.

Single twisted-pair Auto-Negotiation does not test the link segment characteristics.

The function allows the devices at both ends of a link segment to advertise abilities, acknowledge receiptand understanding of the common mode(s) of operation that both devices share, and to reject the use ofoperational modes that are not shared by both devices. Where more than one common mode exists betweenthe two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation usinga predetermined priority resolution function. The single twisted-pair Auto-Negotiation function allows theidentification of the operational mode of the link partner. Should multiple modes be present, managementmay select between the various offered modes. How such selection is done is beyond the scope of thisstandard.

98.1.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model

The single twisted-pair Auto-Negotiation function is provided at the Physical Layer of the ISO/IEC OSIreference model as shown in Figure 98–2. A device that supports multiple modes of operation may advertiseits capabilities using the single twisted-pair Auto-Negotiation function. The actual transfer of information isobserved only at the MDI.

98.2 Functional specifications

The single twisted-pair Auto-Negotiation function provides a mechanism to control connection of a singleMDI to a single PHY type, where more than one PHY type may exist. A management interface providescontrol and status of single twisted-pair Auto-Negotiation, but the presence of a management agent is notrequired.

Auto-Negotiation shall provide the following functions (as shown in Figure 98–1):

a) Transmit

b) Receive

c) Half duplex

d) Arbitration





These functions shall comply with the state diagrams from Figure 98–7 through Figure 98–10. The singletwisted-pair Auto-Negotiation functions shall interact with the technology-dependent PHYs through theTechnology Dependent Interface (see 98.4).

98.2.1 Transmit function requirements

The Transmit function provides the ability to transmit pages. The first pages exchanged by the local deviceand its link partner after Power-On, link restart, or renegotiation contain the base link codeword defined inTable 98–2. The local device may modify the link codeword to disable an ability it possesses, but will nottransmit an ability it does not possess. This makes possible the distinction between local abilities andadvertised abilities so that multi-ability devices may Auto-Negotiate to a mode lower in priority than thehighest common ability.

98.2.1.1 DME transmission

Auto-Negotiation’s method of communication builds upon the encoding mechanism known as differentialManchester encoding (DME). The DME page encodes the data that is used to control the Auto-Negotiationfunction. DME pages shall not be transmitted when Auto-Negotiation is complete and the highest commondenominator PHY has been enabled.

98.2.1.1.1 DME page encoding

A DME page carries a 48-bit Auto-Negotiation page. It consists of 157 evenly spaced transition positionsstarting from the initial transition from silent to active in the preamble. The page contains a Start Delimiter,the 48-bit page, 16-bit CRC, and an end delimiter (see Figure 98–6). The odd-numbered transition positionsrepresent clock information. The even numbered transition positions represent data information. DME pagesare alternately transmitted between the two devices with quiet period separating the DME pages. When theDME page is active, the PHY shall transmit either +1 or –1 level with the voltage levels as specified in98.2.1.1.4.

Figure 98–1—High-level model

TechnologySpecific

PMA = 1000BASE-T1

TechnologySpecific

PMA = #2

TechnologySpecific

PMA = #N

Transmission Arbitration ReceiveAN Half-Duplex

Auto-Negotiation Functions

MDI





The first 26 transition positions contain the Start Delimiter, which marks the beginning of the page. TheStart Delimiter contains a transition from quiet to active at position 1 followed by transitions at positions 2,3, 5, 7, 8, 12, 13, 14, 15, 19, 21, 24, 25, 26 and no transitions at the remaining positions.

The final 2 transition positions contain the ending delimiter, which marks the end of the page. The endingdelimiter contains a transition at position 155 and no transitions at the remaining positions. Position 157contains a transition from active to quiet.

Each of the remaining 64 odd-numbered transition positions between the starting and ending delimiters shallcontain a transition. The remaining 64 even-numbered transition positions shall represent data informationas follows:

— A transition present in an even-numbered transition position represents a logical one.

— A transition absent from an even-numbered transition position represents a logical zero.

The first 48 of these positions shall carry the data of the Auto-Negotiation page. The final 16 positions carrythe 16-bit CRC.

The CRC16 polynomial is x16 + x15 + x2 + 1. The CRC16 shall produce the same result as theimplementation shown in Figure 98–3. The 16 delay elements S0,..., S15, shall be initialized to zero.Afterwards the 48 data bits are used to compute the CRC16 with the switch connected (setting CRCgen).After all the 48 bits have been processed, the switch is disconnected (setting CRCout) and the 16 valuesstored in the delay elements are transmitted in the order illustrated, first S15, followed by S14, and so on,until the final value S0.

Figure 98–2—Location of Auto-Negotiation function within the ISO/IEC OSI reference model

PRESENTATION

APPLICATION

SESSION

TRANSPORT

NETWORK

DATA LINK

PHYSICAL

OSI

REFERENCEMODEL

LAYERS

ETHERNET

LAYERS

MAC - MEDIA ACCESS CONTROL

RECONCILIATION

HIGHER LAYERS

MDI = MEDIUM DEPENDENT INTERFACEGMII = TEN GIGABIT MEDIA INDEPENDENT INTERFACE

PCS = PHYSICAL CODING SUBLAYERPMA = PHYSICAL MEDIUM ATTACHMENT

PHY = PHYSICAL LAYER DEVICE

MDI

1000BASE-T1

PMA

PCS

MEDIUM

LLC - LOGICAL LINK CONTROLOR OTHER MAC CLIENT

MAC CONTROL (OPTIONAL)

PHY

NOTE 2—Auto-Negotiation is optional. Auto-Negotiation communicates

AN2

with the PMA sublayer through the PMA service interface messages PMA_LINK.request and PMA_LINK.indication.

GMII1

NOTE 1—GMII is optional.AN = AUTO-NEGOTIATION





The polarity at position 0 is randomly determined in an implementation specific manner.

The purpose of randomizing the starting polarity is to remove the spectral peaks that would otherwise occurwhen sending the same DME page repeatedly. Randomly choosing the starting polarity results in randomlyinverting or not inverting the encoded page so that repetitions of the same page no longer produce a periodicsignal.

Clock transition positions are differentiated from data transition positions by the spacing between them, asshown in Figure 98–4 and enumerated in Table 98–1.

The encoding of data using DME bits in a DME page is illustrated in Figure 98–4.

98.2.1.1.2 DME page timing

The timing parameters for DME pages shall be followed as in Table 98–1. The transition positions within aDME page are spaced with a period of T1. T2 is the separation between clock transitions. T3 is the timefrom a clock transition to a data transition representing a one. The period, T1, shall be 30.0 ns ± 0.01%.Transitions shall occur within ± 0.8 ns of their ideal positions.

T5 specifies the duration of a DME page. The minimum number of transitions and maximum number oftransitions in a page is represented by T4a. T4b indicates that the start of a DME page begins with atransition from 0 to ±1 and the end of the DME page is a transition from ±1 to 0.

Figure 98–3—CRC16

S0 +S1 S2 S14 + S15

+

CRC16 output

D0 through D47

Logic 0

CRCgen CRCout

Figure 98–4—Data bit encoding within DME pages

Clock transitions

First bit on wire

Data

Encoding

Transition positions 1 2 3 4 5 6 7

1 1 0D0 D1 D2





Table 98–1 summarizes the timing parameters. The transition timing parameters are illustrated in Figure 98–5and Figure 98–6.

98.2.1.1.3 DME page Delimiters

The page is preceded by a unique Start Delimiter consisting of a 26 × T1 sequence that includes multipleDME transition violations. For a Start Delimiter starting with a 0 to +1 transition, the bit sequence is:

+1 –1 +1 +1 –1 –1 +1 –1 –1 –1 –1 +1 –1 +1 –1 –1 –1 –1 +1 +1 –1 –1 –1 +1 –1 +1.

The DME page ends with an end delimiter that consists of a logical 0 bit. An example of the delimiters isshown in Figure 98–6.

NOTE—The Start Delimiter may begin with a 0 to +1 or 0 to –1 transition depending upon the DME page startingpolarity randomizer.

Table 98–1—DME page timing summary

Parameters Min Typ Max Units

T1 Transmit position spacing (period) 29.997 30 30.003 ns

T2 Clock transition to clock transition 59.8 60 60.2 ns

T3 Clock transition to data transition (data = 1) 29.9 30 30.1 ns

T4a +1 to –1 or –1 to +1 transitions in a DME page 79 — 143 —

T4b 0 to ±1 or ±1 to 0 transitions in a DME page 2 2 2 —

T5 DME page width 4679 4680 4681 ns

Figure 98–5—DME page transition timing

Clocktransition

Clocktransition

Datatransition

T2

T3

D0

D1

D46

D47

S15

S0

Start Delimiter Payload CRC16 End Delimiter

T5

Figure 98–6—DME Page





98.2.1.1.4 Transmitter peak differential output

When measured with 100 termination, transmit differential signal at MDI shall be within range of1 V ± 30% peak-to-peak.

98.2.1.2 Link codeword encoding

The base link codeword (Base Page) transmitted within a DME page shall convey the encoding shown inTable 98–2. The Auto-Negotiation function supports additional pages using the Next Page function.

Encoding for the link codeword(s) used in the Next Page exchange are defined in 98.2.4.3. In a DME page,D0 shall be the first bit transmitted.

D[4:0] contains the Selector Field. D[9:5] contains the Echoed Nonce field. D[11:10] contains capabilitybits to advertise capabilities not related to the PHY. C[1:0] is used to advertise pause capability. D[12] is theforce MASTER-SLAVE bit (see 98.2.1.2.5). D[15:13] contains the RF, Ack, and NP bits. The RF, Ack, andNP bits shall function as specified in 98.2.1.2.7, 98.2.1.2.8, and 98.2.1.2.9, respectively. D[20:16] containsthe Transmitted Nonce field. D[47:21] contains the Technology Ability Field.

98.2.1.2.1 Selector Field

Selector Field (S[4:0]) is a 5-bit wide field, encoding 32 possible messages. Selector Field encodingdefinitions are shown in Annex 98A. Combinations not specified are reserved. Reserved combinations of theSelector Field shall not be transmitted.

The Selector Field for IEEE Std 802.3 is shown in Table 98–3.

98.2.1.2.2 Echoed Nonce Field

Echoed Nonce Field (E[4:0]) is a 5-bit wide field containing the nonce received from the link partner. If thedevice has not received a DME page with good CRC16, the bits in this field shall contain logical zeros. If thedevice has received a DME page with good CRC16, the bits in this field shall contain the value received inthe Transmitted Nonce Field from the link partner at the same time as the Acknowledge bit is set.

Table 98–2—Link codeword Base Page

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15S0 S1 S2 S3 S4 E0 E1 E2 E3 E4 C0 C1 M/S RF Ack NP

D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31T0 T1 T2 T3 T4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26

Table 98–3—Selector Field Encoding

S4 S3 S2 S1 S0 Selector description

0 0 0 0 1 IEEE Std 802.3





98.2.1.2.3 Transmitted Nonce Field

Transmitted Nonce Field (T[4:0]) is a 5-bit wide field whose lower 4 bits contains a random or pseudo-random number. A new value shall be generated for each entry to the Ability Detect state. The method ofgenerating the nonce is left to the implementer. The lower 4 bits of the transmitted nonce should have auniform distribution in the range from 0 to 24 – 1. The method used to generate the value should be designedto minimize correlation to the values generated by other devices.

Bit T[4] should be set to 1 if the device prefers or is forced to be MASTER and 0 if the device prefers or isforced to be SLAVE.

If the device has received a DME page with good CRC16 and the link partner has a Transmitted Nonce Field(T[4:0]) that matches the devices generated T[4:0], the device shall invert its T[0] bit and regenerate a newrandom value for T[3:1] and use that as its new T[4:0] value. Since the DME pages are exchanged in a half-duplex manner, it is possible to swap to a new T[4:0] value prior to transmitting the DME page. One devicewill always see a DME page with good CRC16 before the other device hence this swapping will guaranteethat nonce_match will never be true.

98.2.1.2.4 Technology Ability Field

Technology Ability Field (A[26:0]) is a 27-bit wide field containing information indicating supportedtechnologies specific to the selector field value when used with the single twisted-pair Auto-NegotiationEthernet. These bits are mapped to individual technologies such that abilities are advertised in parallel for asingle selector field value. The Technology Ability Field encoding for the IEEE 802.3 selector with singletwisted-pair Auto-Negotiation Ethernet is described in 98B.3.

Multiple technologies may be advertised in the link codeword. A device shall support the data service abilityfor a technology it advertises. It is the responsibility of the Arbitration function to determine the commonmode of operation shared by a link partner and to resolve multiple common modes.

98.2.1.2.5 Force MASTER-SLAVE

The force MASTER-SLAVE bit, D12, allows a device to force its MASTER-SLAVE configuration. If thisbit is set to 0 then the device is in preferred mode, otherwise it is in the forced mode. The MASTER-SLAVEresolution is shown in Table 98–4.

Table 98–4—MASTER-SLAVE Configuration

Local Device Remote Device

Local Device Resolution Remote Device Resolution

M/S T[4] M/S T[4]

0 X 0 X Device with higher T[4:0] is MASTER, otherwise SLAVE

Device with higher T[4:0] is MASTER, otherwise SLAVE

0 X 1 0 MASTER SLAVE

0 X 1 1 SLAVE MASTER

1 0 0 X SLAVE MASTER

1 1 0 X MASTER SLAVE

1 0 1 0 Configuration Fault Configuration Fault





98.2.1.2.6 Pause Ability

Pause (C0:C1) is encoded in bits D11:D10 of the base link codeword. The 2-bit Pause is encoded as follows:

a) C0 is the same as PAUSE as defined in Annex 28B

b) C1 is the same as ASM_DIR as defined in Annex 28B

The Pause encoding is defined in 28B.2, Table 28B–2. The PAUSE bit indicates that the device is capable ofproviding the symmetric PAUSE functions as defined in Annex 31B. The ASM_DIR bit indicates thatasymmetric PAUSE is supported. The value of the PAUSE bit when the ASM_DIR bit is set indicates thedirection the PAUSE frames are supported for flow across the link. Asymmetric PAUSE configurationresults in independent enabling of the PAUSE receive and PAUSE transmit functions as defined byAnnex 31B. See 28B.3 regarding PAUSE configuration resolution.

98.2.1.2.7 Remote Fault

Remote Fault (RF) is encoded in bit D13 of the base link codeword. The default value is logical zero. TheRemote Fault bit provides a standard transport mechanism for the transmission of simple fault information.When the RF bit in the BASE-T1 AN advertisement register (Register 7.514.13) is set to logical one, the RFbit in the transmitted base link codeword is set to logical one. When the RF bit in the received base linkcodeword is set to logical one, the Remote Fault bit in the BASE-T1 AN LP Base Page ability register(Register 7.517.13) will be set to logical one, if the management function is present.

98.2.1.2.8 Acknowledge

Acknowledge (Ack) is used by the Auto-Negotiation function to indicate that a device has successfullyreceived its link partner’s link codeword. The Acknowledge Bit is encoded in bit D14 of link codeword. Ifno Next Page information is to be sent, this bit shall be set to logical one in the link codeword after thereception of at least one DME page with a correct CRC. If Next Page information is to be sent, this bit shallbe set to logical one after the device has successfully received at least one DME page with correct CRC, andwill remain set until the Next Page information has been loaded into the BASE-T1 AN NEXT PAGEtransmit register (Registers 7.520, 7.521, 7.522). In order to save the current received link codeword, it shallbe read from the BASE-T1 AN LP NEXT PAGE ability register (Register 7.523, 7.524, 7.525) before theNext Page of transmit information is loaded into the BASE-T1 AN NEXT PAGE transmit register. After theCOMPLETE ACKNOWLEDGE state has been entered, the link codeword will be transmitted at least threetimes.

98.2.1.2.9 Next Page

Next Page (NP) is encoded in bit D15 of link codeword. Support of Next Pages is mandatory. If the devicedoes not have any Next Pages to send, the NP bit shall be set to logical zero. If a device wishes to engage in

1 0 1 1 SLAVE MASTER

1 1 1 0 MASTER SLAVE

1 1 1 1 Configuration Fault Configuration Fault

Table 98–4—MASTER-SLAVE Configuration (continued)

Local Device Remote Device

Local Device Resolution Remote Device Resolution

M/S T[4] M/S T[4]





Next Page exchange, it shall set the NP bit to logical one. If a device has no Next Pages to send and its linkpartner has set the NP bit to logical one, it shall transmit Next Pages with Null message codes and the NP bitset to logical zero while its link partner transmits valid Next Pages. Next page exchanges will occur if eitherthe device or its link partner sets the Next Page bit to logical one. The Next Page function is defined in98.2.4.3.

98.2.1.3 Transmit Switch function

The Transmit Switch function shall enable the transmit path from a single technology-dependent PHY to theMDI once a highest common denominator choice has been made and Auto-Negotiation has completed.During Auto-Negotiation, the Transmit Switch function shall connect only the DME page generatorcontrolled by the Transmit State Diagram to the MDI. When a PHY is connected to the MDI through theTransmit Switch function, the signals at the MDI shall conform to all of the PHY’s specifications.

98.2.2 Receive function requirements

The Receive function detects the DME page sequence, decodes the information contained within, and storesthe data in rx_link_code_word[64:1]. The receive function incorporates a receive switch to controlconnection to the various PMAs.

98.2.2.1 DME page reception

To be able to detect the DME bits, the receiver should have the capability to receive DME signals sent withthe electrical specifications of the PHY. The DME transmit signal level is specified in 98.2.1.1.4.

98.2.2.2 Receive Switch function

The Receive Switch function shall enable the receive path from the MDI to a single technology-dependentPHY once a highest common denominator choice has been made and Auto-Negotiation has completed.

During Auto-Negotiation, the Receive Switch function shall connect the DME page receiver controlled bythe Receive state diagram to the MDI and the Receive Switch function shall also connect the appropriatereceivers to the MDI.

98.2.2.3 Link codeword matching

The Receive function shall generate ability_match, acknowledge_match, and consistency_match variablesas defined in Arbitration state diagram Figure 98–7.

98.2.3 AN half-duplex function requirements

The AN half-duplex function is defined by Figure 98–10 and ensures that only one of the link partners istransmitting a DME page at each step during the DME page exchange process. The AN half-duplex functionuses a blind timer to ensure that the receiver ignores signals reflected from the channel following the end ofthe device's transmitted DME page. A silent timer is used to ensure that the device does not begintransmitting the DME page until after the link partner has exited from the blind timer. The half-duplexbackoff timer resolves concurrent transmissions by using a random wait time to listen for a DME page toarrive from the link partner before the local device transmits a DME page.

98.2.4 Arbitration function requirements

The Arbitration function is defined by Figure 98–7 and ensures proper sequencing of the Auto-Negotiationfunction using the Transmit function, Receive function, and AN half-duplex function. The Arbitrationfunction enables the Transmit function to advertise and acknowledge abilities. Upon indication of





acknowledgment, the Arbitration function determines the highest common denominator using the priorityresolution function and enables the appropriate technology-dependent PHY via the Technology DependentInterface (see 98.4).

98.2.4.1 Renegotiation function

A Renegotiation request from any entity, such as a management agent, shall cause the Arbitration functionto disable all technology-dependent PHYs and halt any transmit data and link transition activity until thebreak_link_timer expires. Consequently, the link partner will go into link fail and normal Auto-Negotiationresumes. The local device shall resume Auto-Negotiation after the break_link_timer has expired by issuingDME pages with the Base Page valid in tx_link_code_word[64:1]. Once Auto-Negotiation has completed,renegotiation will take place if the Highest Common Denominator technology that receiveslink_control = ENABLE returns link_status = FAIL. To allow the PHY an opportunity to determine linkintegrity using its own link integrity test function, the link_fail_inhibit_timer qualifies thelink_status = FAIL indication such that renegotiation takes place if the link_fail_inhibit_timer has expiredand the PHY still indicates link_status = FAIL.

98.2.4.2 Priority Resolution function

Since a local device and a link partner may have multiple common abilities, a mechanism to resolve whichmode to configure is required. The mechanism used by Auto-Negotiation is a Priority Resolution functionthat predefines the hierarchy of supported technologies. The single PHY enabled to connect to the MDI byAuto-Negotiation shall be the technology corresponding to the bit in the Technology Ability Field commonto the local device and link partner that has the highest priority as defined in 98B.4 (listed from highestpriority to lowest priority).

The common technology is referred to as the highest common denominator, or HCD, technology. If the localdevice receives a Technology Ability Field with a bit set that is reserved, the local device shall ignore thatbit for priority resolution. Determination of the HCD technology occurs on entrance to the AN GOODCHECK state. In the event that there is no common technology, HCD shall have a value of “NULL,”indicating that no PHY receives link_control = ENABLE and link_status[HCD] = FAIL.

98.2.4.3 Next Page function

The Next Page function uses the Auto-Negotiation arbitration mechanisms to allow exchange of Next Pagesof information, which may follow the transmission and acknowledgment procedures used for the base linkcodeword. The Next Page has both Message Code Field and Unformatted Code Fields.

A dual acknowledgment system is used. Acknowledge (Ack) is used to acknowledge receipt of theinformation; Acknowledge 2 (Ack2) is used to indicate that the receiver is able to act on the information (orperform the task) defined in the message.

The Toggle (T) bit is used to ensure proper synchronization between the local device and the link partner.

Next page exchange occurs after the base link codewords have been exchanged if either end of the linksegment set the Next Page bit to logical one indicating that it had at least one Next Page to send. Next pageexchange consists of using the normal Auto-Negotiation arbitration process to send Next Page messages.

The Next Page contains two message encodings. The message encodings are defined as follows: messagecode, which contains predefined 11-bit codes, and unformatted code, which contains 32-bit codes. MultipleNext Pages with appropriate message codes and unformatted codes can be transmitted to send extendedmessages. Each series of Next Pages shall have a Message code that defines how the Unformatted codes willbe interpreted. Any number of Next Pages may be sent in any order; however, it is recommended that thetotal number of Next Pages sent be kept small to minimize the link start-up time.





Next page transmission ends when both ends of a link segment set their Next Page bits to logical zero,indicating that neither has anything additional to transmit. It is possible for one device to have more pages totransmit than the other device. Once a device has completed transmission of its Next Page information, itshall transmit Next Pages with Null message codes and the NP bit set to logical zero while its link partnercontinues to transmit valid Next Pages. An Auto-Negotiation able device shall recognize reception ofMessage Pages with Null message codes as the end of its link partner’s Next Page information.

98.2.4.3.1 Next page encodings

The Next Page shall use the encoding shown in Table 98–5 and Table 98–6 for the NP, Ack, MP, Ack2, andT bits. These bits shall function as specified in 98.2.1.2.9, 98.2.1.2.8, 28.2.3.4.5, 28.2.3.4.6, and 28.2.3.4.7respectively. There are two types of Next Page encodings: message and unformatted. For message NextPages, the MP bit shall be set to logical one, the 11-bit field D[10:0] shall be encoded as a Message CodeField and D[47:16] shall be encoded as Unformatted Code Field. For Unformatted Next Pages, the MP bitshall be set to logical ZERO: D[10:0] and D[47:16] shall be encoded as the Unformatted Code Field.

98.2.4.3.2 Use of Next Pages

Next page exchange will commence after the Base Page exchange if either device requests it by setting theNP bit to logical one.

Next page exchange shall continue until neither device on a link has more pages to transmit as indicated bythe NP bit. A Next Page with a Null Message Code Field value shall be sent if the device has no otherinformation to transmit.

A message code can carry either a specific message or information that defines how the correspondingunformatted codes should be interpreted.

Table 98–5—Message Next Page

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 T Ack2 MP Ack NP

D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31U0 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15


Table 98–6—Unformatted Next Page

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15U0 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 T Ack2 MP Ack NP







98.3 State diagram variable to Auto-Negotiation register mapping

The state diagrams of Figure 98–7 to Figure 98–10 generate and accept variables of the form “mr_x,” wherex is an individual signal name. These variables comprise a management interface to communicate Auto-Negotiation information to and from the management entity. Clause 45 MDIO registers are defined inMMD7 to support Auto-Negotiation. The Clause 45 MDIO electrical interface is optional. Where nophysical embodiment of the MDIO exists, provision of an equivalent mechanism to access the information isrecommended.

Table 98–7 describes the MDIO register to the state diagrams variable mapping.

98.4 Technology-Dependent Interface

The Technology-Dependent Interface is the communication mechanism between each technology’s PMAand the Auto-Negotiation function. Auto-Negotiation can support multiple technologies, all of which neednot be implemented in a given device. Each of these technologies may utilize its own technology-dependentlink integrity test function.

98.4.1 PMA_LINK.indication

This primitive is generated by the PMA to indicate the status of the underlying medium. The purpose of thisprimitive is to give the Auto-Negotiation function a means of determining the validity of received codeelements.

98.4.1.1 Semantics of the service primitive


Table 98–7—State diagram variable to Single twisted-pair Auto-Negotiation MDIO register mapping

State diagram variable Description / MDIO register mapping

mr_adv_ability[48:1] {7.516.15:0, 7.515.15:0, 7.514.15:0} BASE-T1 AN advertisement registers

mr_autoneg_complete 7.513.5 Auto-Negotiation complete

mr_autoneg_enable 7.512.12 Auto-Negotiation enable

mr_lp_adv_ability[48:1] For Base Page:{7.519.15:0, 7.518.15:0, 7.517.15:0} BASE-T1 AN LP Base Page ability registersFor Next Page(s):{7.525.15:0, 7.524.15:0, 7.523.15:0} BASE-T1 AN LP NEXT PAGE ability register

mr_main_reset 7.512.15 AN reset

mr_next_page_loaded Set on write to BASE-T1 AN NEXT PAGE transmit register;cleared by Arbitration state diagram

mr_np_tx[48:1] {7.522.15:0, 7.521.15:0, 7.520.15:0} BASE-T1 AN NEXT PAGE transmit register

mr_page_rx 7.513.6 Page received

mr_restart_negotiation 7.512.9 Restart Auto-Negotiation

set to 1 7.513.3 Auto-Negotiation ability





The link_status parameter shall assume one of two values: OK or FAIL, indicating whether the underlyingreceive channel is intact and enabled (OK) or not intact (FAIL).

98.4.1.2 When generated

A technology-dependent PMA generates this primitive to indicate a change in the value of link_status.

98.4.1.3 Effect of receipt

The effect of receipt of this primitive shall be governed by the state diagram of Figure 98–7.

98.4.2 PMA_LINK.request

This primitive is generated by Auto-Negotiation to allow it to enable and disable operation of the PMA.

98.4.2.1 Semantics of the service primitive


The link_control parameter shall assume one of two values: DISABLE or ENABLE.

The link_control=DISABLE mode shall be used by the Auto-Negotiation function to disable PMAprocessing.

The link_control=ENABLE mode shall be used by Auto-Negotiation to turn control over to a single PMAfor all normal processing functions.

98.4.2.2 When generated

The Auto-Negotiation function shall generate this primitive to indicate to the PHY how to respond, inaccordance with the state diagram of Figure 98–7. Upon power-on or reset, if the Auto-Negotiation functionis enabled (mr_autoneg_enable=true) the PMA_LINK.request(DISABLE) message shall be issued to alltechnology-dependent PMAs.

98.4.2.3 Effect of receipt

This primitive affects operation of the underlying PMA.

98.5 Detailed functions and state diagrams

The notation used in state diagrams follows the conventions in Clause 28. Variables in a state diagram withdefault values evaluate to the variable default in each state where the variable value is not explicitly set.

Auto-Negotiation shall implement the Transmit state diagram, Receive state diagram, half-duplex statediagram, and Arbitration state diagram. Additional requirements to these state diagrams are made in therespective functional requirements sections. Options to these state diagrams clearly stated as such in thefunctional requirements sections or state diagrams shall be allowed. In the case of any ambiguity betweenstated requirements and the state diagrams, the state diagrams shall take precedence.

98.5.1 State diagram variables

A variable with “_[x]” appended to the end of the variable name indicates a variable or set of variables asdefined by “x”. “x” may be as follows:





— all; represents all specific technology-dependent PMAs supported in the local device.

— HCD; represents the single technology-dependent PMA chosen by Auto-Negotiation as thehighest common denominator technology through the Priority Resolution.

— notHCD; represents all technology-dependent PMAs not chosen by Auto-Negotiation as the highestcommon denominator technology through the Priority Resolution.

— 1GigT1; represents that the 1000BASE-T1 PMA is the signal source.

Variables with [48:1] appended to the end of the variable name indicate arrays that can be directly mappedto 48-bit registers. For these variables, “[x]” indexes an element or set of elements in the array, where “[x]”may be as follows:

a) Any integer

b) Any range of integers

c) Any variable that takes on integer values

d) NP; represents the index of the Next Page bit

e) ACK; represents the index of the Acknowledge bit

f) RF; represents the index of the Remote Fault bit

Variables of the form “mr_x”, where x is a label, comprise a management interface that is intended to beconnected to the Management function. However, an implementation-specific management interface mayprovide the control and status function of these bits. The mapping between state diagram variables andSingle twisted-pair Auto-Negotiation MDIO registers is shown in Table 98–7.

ability_matchIndicates that at least one link codeword with good CRC16 was received.Values:

false: at least one link codeword with good CRC16 has not been received (default)true: at least one link codeword with good CRC16 has been received

NOTE—This variable is set by this variable definition; it is not set explicitly in the state diagrams.

ability_match_word [48:1]A 48-bit array that is loaded upon transition to Acknowledge Detect state with the value of the linkcodeword that caused ability_match = true for that transition. For each element in the array trans-mitted.Values:

ZERO: data bit is logical zeroONE: data bit is logical one


ack_finishedStatus indicating that the final remaining_ack_cnt link codewords with the Ack bit set have beentransmitted.Values:

false: more link codewords with the Ack bit set to logical one is transmittedtrue: all remaining link codewords with the Ack bit set to logical one have been

transmitted

ack_nonce_matchIndicates whether the echoed nonce received from the link partner matches the transmitted noncefield sent by the local device. The echoed nonce value from the DME page that caused acknowl-edge_match to be set is used for this test.Values:





false: link partner echoed nonce does not equal local device transmitted noncetrue: link partner echoed nonce equals local device transmitted nonce

acknowledge_matchIndicates that at least one link codeword with the Acknowledge bit set and with good CRC16 wasreceived. The link codeword that initially set the ability_match variable should not be used to setthis variable.Values:

false: at least one link codeword with the Acknowledge bit set and with good CRC16has not been received (default)

true: at least one link codeword with the Acknowledge bit set and with good CRC16has been received


an_link_goodIndicates that Auto-Negotiation has completed.Values:

false: negotiation is in progress (default)true: negotiation is complete, forcing the Transmit and Receive functions to IDLE

an_receive_idleIndicates that the Receive state diagram is in the IDLE state.Values:

false: the Receive state diagram is not in the IDLE state (default)true: the Receive state diagram is in the IDLE state

base_pageStatus indicating that the page currently being transmitted by Auto-Negotiation is the initial linkcodeword encoding used to communicate the device’s abilities.Values:

false: a page other than base link codeword is being transmittedtrue: the base link codeword is being transmitted

code_selA random or pseudo-random value uniformly distributed. A new value is generated each time thevariable code_sel is used.Values:

ZERO: a zero has been assignedONE: a one has been assigned

complete_ackControls the counting of transmitted link codewords that have their Acknowledge bit set.Values:

false: transmitted link codewords with the Acknowledge bit set are not counted(default)

true: transmitted link codewords with the Acknowledge bit set are counted

consistency_matchIndicates that the ability_match_word is the same as the link codeword that causedacknowledge_match to be set.Values:

false: the link codeword that caused ability_match to be set is not the same as the linkcodeword that caused acknowledge_match to be set, ignoring the Acknowledgebit value and the echoed nonce value





true: the link codeword that caused ability_match to be set is the same as the linkcodeword that caused acknowledge_match to be set, ignoring the Acknowledgebit value and the echoed nonce value


detect_mv_endStatus indicating that the receiver has detected the end delimiter.Values:

false: set to false after any Receive State Diagram state transition (default)true: end delimiter has been detected

detect_mv_startStatus indicating that the receiver has detected a Start Delimiter as defined in 98.2.1.1.1.Values:

false: set to false after any Receive State Diagram state transition (default)true: Start Delimiter has been detected

detect_transitionStatus indicating that the receiver has detected a transition.Values:

false: set to false after any Receive State Diagram state transition (default)true: set to true when a transition is received

incompatible_linkParameter used following Priority Resolution to indicate the resolved link is incompatible with thelocal device settings. A device’s ability to set this variable to true is optional.Values:

false: a compatible link exists between the local device and link partner (default)true: optional indication that Priority Resolution has determined no highest common

denominator exists following the most recent negotiation


link_controlControls the connection of each PMD to the MDI. When all PMD transmitters are isolated fromthe MDI, the AN transmitter is connected to the MDI.Values:

DISABLE: isolates the PMD from the MDIENABLE: connects the PMD (both transmit and receive) to the MDI


mr_autoneg_completeStatus indicating whether Auto-Negotiation has completed or not.Values:

false: Auto-Negotiation has not completedtrue: Auto-Negotiation has completed

mr_autoneg_enableControls the enabling and disabling of the Auto-Negotiation function.Values:

false: Auto-Negotiation is disabledtrue: Auto-Negotiation is enabled





mr_adv_ability[48:1]A 48-bit array that contains the Advertised Abilities link codeword. For each element within thearray:Values:


mr_lp_adv_ability[48:1]A 48-bit array that contains the link partner’s Advertised Abilities link codeword. For eachelement within the array: Values:


mr_main_resetControls the resetting of the Auto-Negotiation state diagrams.Values:

false: do not reset the Auto-Negotiation state diagramstrue: reset the Auto-Negotiation state diagrams

mr_next_page_loadedStatus indicating whether a new page has been loaded into the BASE-T1 AN NEXT PAGEtransmit register (see 45.2.7.14g).Values:

false: a New Page has not been loadedtrue: a New Page has been loaded

mr_np_tx[48:1]A 48-bit array that contains the new Next Page to transmit. For each element within the array:Values:


mr_page_rxStatus indicating whether a New Page has been received. A New Page has been successfullyreceived when acknowledge_match = true and consistency_match = true and the link codewordhas been written to mr_lp_adv_ability[48:1].Values:

false: a New Page has not been receivedtrue: a New Page has been received

mr_restart_negotiationControls the entrance to the TRANSMIT DISABLE state to break the link before Auto-Negotiation is allowed to renegotiate via management control.Values:

false: renegotiation is not taking placetrue: renegotiation is started

nonce_matchIndicates whether the transmitted nonce received from the link partner matches the transmittednonce field sent by the local device.Values:





false: link partner transmitted nonce does not equal local device transmitted noncetrue: link partner transmitted nonce equals local device transmitted nonce

np_rxFlag to hold the value of rx_link_code_word[NP] upon entry to the COMPLETEACKNOWLEDGE state. This value is associated with the value of rx_link_code_word[NP] whenacknowledge_match was last set.Values:

ZERO: local device np_rx bit equals a logical zeroONE: local device np_rx bit equals a logical one

page_polarityStarting polarity of the page.Values:

ZERO: starting polarity of page is negativeONE: starting polarity of page is positive

power_onCondition that is true until such time as the power supply for the device that contains the Auto-Negotiation state diagrams has reached the operating region or the device has low-power mode setvia 1000BASE-T1 PMA control register bit 1.2304.11. Values:

false: the device is completely powered (default)true: the device has not been completely powered

receive_blindControls whether the receiver should ignore activity on the line.Values:

true: ignore received DME transitionsfalse: accept received DME transitions

receive_DME_activeStatus indicating whether or not a DME page reception is in progress.Values:

true: DME page reception in progressfalse: DME page reception completed

rx_link_code_word[64:1]A 64-bit array that contains the data bits to be received from a DME page. For each element withinthe array:Values:

ZERO: data bit is a logical zeroONE: data bit is a logical one

rx_nonce[4:0]A 5-bit array that contains the transmitted nonce received from the DME page that causedability_match = true. For each element within the array:Values:

ZERO: data bit is a logical zeroONE: data bit is a logical one

TD_AUTONEGControls the signal sent by Auto-Negotiation on the TD_AUTONEG circuit.Values:





disable: transmission of Auto-Negotiation signals is disabledidle: Auto-Negotiation maintains the current signal level on the MDImv_end_delimiter: Auto-Negotiation causes the transmission of the end delimiter on the

MDImv_start_delimiter: Auto-Negotiation causes the transmission of the Start Delimiter on

the MDI as defined in 98.2.1.1.1transition: Auto-Negotiation causes a transition in the level on the MDI

toggle_rxFlag to keep track of the state of the link partner’s Toggle bit.Values:

ZERO: link partner’s Toggle bit equals logical zeroONE: link partner’s Toggle bit equals logical one

toggle_txFlag to keep track of the state of the local device’s Toggle bit.Values:

ZERO: local device’s Toggle bit equals logical zeroONE: local device’s Toggle bit equals logical one

transmit_abilityControls the transmission of the link codeword containing tx_link_code_word[64:1].Values:

false: any transmission of tx_link_code_word[64:1] is halted (default)true: the transmit state diagram begins sending tx_link_code_word[64:1]

transmit_ackControls the setting of the Acknowledge bit in the tx_link_code_word[64:1] to be transmitted.Values:

false: sets the Acknowledge bit in the transmitted tx_link_code_word[64:1] to a logicalzero (default)

true: sets the Acknowledge bit in the transmitted tx_link_code_word[64:1] to a logicalone

transmit_disableControls the transmission of tx_link_code_word[64:1].Values:

false: tx_link_code_word[64:1] transmission is allowed (default)true: tx_link_code_word[64:1]transmission is halted

transmit_DME_doneStatus indicating the DME page transmission completed.Values:

true: DME page transmission completedfalse: DME page transmission in progress

transmit_DME_waitControl indication whether a DME page can be transmitted.Values:true: pause DME page transmissionfalse: continue DME page transmission

transmit_mv_end_doneStatus indicating that the transmission of the end delimiter has completed.





Values:false: transmission of the end delimiter is in progresstrue: transmission of the end delimiter has completed

transmit_mv_start_doneStatus indicating that the transmission of the Start Delimiter defined in 98.2.1.1.1 has been com-pleted.Values:

false: transmission of the Start Delimiter is in progresstrue: transmission of the Start Delimiter has been completed

tx_link_code_word[64:1]A 64-bit array that contains the data bits to be transmitted in an DME page.tx_link_code_word[48:1] contains the Auto-Negotiation page to be transmitted.tx_link_code_word[64:49] contains the CRC16. This array may be loaded from mr_adv_ability ormr_np_tx. For each element within the array:Values:

ZERO: data bit is logical zeroONE: data bit is logical one.

98.5.2 State diagram timers

All timers operate in the manner described in 40.4.5.2.backoff_timer

Timer for the random amount of time to wait for a page to arrive from the link partner beforetransmitting a page. The timer shall expire according to the formula below after being started.If T[4] bit is 1 then the timer duration is set as (6805 ns to 6925 ns) + (random integer from0 to 15) × (2120 ns to 2240 ns).If T[4] bit is 0 then the timer duration is set as (7895 ns to 8015 ns) + (random integer from0 to 15) × (2120 ns to 2240 ns).A new random integer from 0 to 15 inclusive is generated every time the backoff_timer isstarted. The random value should be uniformly distributed.

blind_timerTimer for the amount of time to blind the receiver after end of transmission to prevent thedevice from seeing its own echo. The timer shall expire 2000 ns to 2120 ns after being started.

break_link_timerTimer for the amount of time to wait in order to assure that the link partner enters a Link Failstate. The timer shall expire 300 µs to 305 µs after being started.

clock_detect_max_timerTimer for the maximum time between detection of differential Manchester clock transitions.The clock_detect_max_timer shall expire 63 ns to 75 ns after being started or restarted.

clock_detect_min_timerTimer for the minimum time between detection of differential Manchester clock transitions.The clock_detect_min_timer shall expire 45 ns to 57 ns after being started or restarted.

data_detect_max_timerTimer for the maximum time between a clock transition and the following data transition. Thistimer is used in conjunction with the data_detect_min_timer to detect whether the data bitbetween two clock transitions is a logical zero or a logical one. The data_detect_max_timershall expire 33 ns to 45 ns from the last clock transition.





data_detect_min_timerTimer for the minimum time between a clock transition and the following data transition. Thistimer is used in conjunction with the data_detect_max_timer to detect whether the data bitbetween two clock transitions is a logical zero or a logical one. The data_detect_min_timershall expire 15 ns to 27 ns from the last clock transition.

interval_timerTimer for the separation of a transmitted clock pulse from a data bit. The interval_timer shallexpire 30 ns ± 0.01% from each clock pulse and data bit.

link_fail_inhibit_timerTimer for qualifying a link_status=FAIL indication or a link_status=OK indication when aspecific technology link is first being established. A link will only be considered “failed” if thelink_fail_inhibit_timer has expired and the link has still not gone into the link_status=OKstate. The link_fail_inhibit_timer shall expire 97 ms to 98 ms after entering the AN LINKGOOD CHECK state.

NOTE—The link_fail_inhibit_timer expiration value is greater than the time required for the link partner to completeAuto-Negotiation after the local device has completed Auto-Negotiation plus the time required for the specifictechnology to enter the link_status=OK state.

page_test_max_timerTimer for the maximum time between detection of start and end delimiters. Thepage_test_max_timer shall expire 4800 ns to 4920 ns after being started or restarted.

receive_DME_timerTimer for the maximum amount of time to receive a complete page before timeout. The timershall expire 6805 ns to 6925 ns after being started.

rx_wait_timerTimer for the maximum time between detection of DME pages. This timer is used to detectwhether the link partner is transmitting DME pages. The rx_wait_timer shall expire 15 µs to17 µs after being started or restarted.

silent_timerTimer for the amount of time to wait after receiving a page before transmitting a page. Thetimer shall expire 2120 ns to 2240 ns after being started.

98.5.3 State diagram counters

remaining_ack_cntA counter that may take on integer values from 0 to 3. The number of additional link codewordswith the Acknowledge Bit set to logical one to be sent to ensure that the link partner receives theacknowledgment.Values:

not_done: positive integers between 0 and 2 inclusivedone: positive integer 3init: counter is reset to zero

rx_bit_cntA counter that may take on integer values from 0 to 64. This counter is used to keep a count of databits received from a DME page and to ensure that when erroneous extra transitions are received,the first 48 bits are kept while the next 16 bits are used for CRC16 check and any additional bitsare ignored. When this counter reaches 64, enough data bits have been received. This counter doesnot increment beyond 64 and does not return to 0 until it is reinitialized.





tx_bit_cntA counter that may take on integer values from 1 to 64. This counter is used to keep a count ofdata bits sent within a DME page. When this counter reaches 64, all data bits have been sent.

98.5.4 Function

CRC16(x[48:1])Returns the output of the CRC16 generator described in 98.2.1.1.1 after processing the 48-bit input x.

98.5.5 State diagrams

Figure 98–7—Arbitration state diagram

ABILITY DETECT

transmit_ability truetoggle_tx mr_adv_ability[12]ability_match falseacknowledge_match falsetx_link_code_word[48:1] mr_adv_ability[48:1]mr_page_rx falsebase_page trueack_finished falseconsistency_match false

TRANSMIT DISABLE

start break_link_timerlink_control_[all] DISABLEtransmit_disable truemr_page_rx falsemr_autoneg_complete falsemr_next_page_loaded false

ACKNOWLEDGE DETECT

if(base_page = true) thentx_link_code_word[10:6] rx_nonce[4:0]transmit_ability truetransmit_ack truelink_control_[all] DISABLE

COMPLETE ACKNOWLEDGE

complete_ack truetransmit_ability truetransmit_ack truetoggle_rx rx_link_code_word[12]toggle_tx !toggle_txmr_page_rx truenp_rx rx_link_code_word[NP]mr_lp_adv_ability rx_link_code_word[48:1]

NEXT PAGE WAIT

transmit_ability truemr_page_rx falsebase_page falsetx_link_code_word[48:13] mr_np_tx[48:13]tx_link_code_word[12] toggle_txtx_link_code_word[11:1] mr_np_tx[11:1]ack_finished falsemr_next_page_loaded false

AN GOOD CHECK

link_control_[notHCD] DISABLElink_control_[HCD] ENABLEan_link_good truestart link_fail_inhibit_timer

Auto-Negotiation ENABLE

mr_page_rx falsemr_autoneg_complete false

AN GOOD

an_link_good truemr_autoneg_complete true

break_link_timer_done

(acknowledge_match = true *(consistency_match = false +(ack_nonce_match = false *base_page = true))) +an_receive_idle = true

acknowledge_match = true *(ack_nonce_match = true +base_page = false) *consistency_match = true

ability_match = true * nonce_match = false

ack_finished = true *mr_next_page_loaded = true *

((tx_link_code_word[NP] = 1) +(np_rx = 1)

ability_match = true *nonce_match = true

ability_match = true *((toggle_rx ^ ability_match_word[12]) = 1)

ack_finished = true *tx_link_code_word[NP] = 0 *

np_rx = 0

power_on = true +mr_main_reset = true +

mr_restart_negotiation = true +mr_autoneg_enable = false

mr_autoneg_enable = true

link_status_[HCD] = OK

link_status_[HCD] = FAIL

(link_status_[HCD] = FAIL *link_fail_inhibit_timer_done) +incompatible_link = true

an_receive_idle = true





Figure 98–8—Transmit state diagram

WAIT 2

TD_AUTONEG disabletransmit_DME_done falsepage_polarity code_selremaining_ack_cnt remaining_ack_cnt + 1if (remaining_ack_cnt = done)then ack_finished true

TRANSMIT REMAININGACKNOWLEDGE

remaining_ack_cnt init

TRANSMIT CLOCK BIT

start interval_timerTD_AUTONEG transition

TRANSMIT DELIMITER TAIL

TD_AUTONEG mv_end_delimitertransmit_DME_done true

TRANSMIT DELIMITER HEAD

TD_AUTONEG mv_start_delimiterremaining_ack_cnt done

WAIT 1

TD_AUTONEG disabletransmit_DME_done falsepage_polarity code_sel

IDLE

TD_AUTONEG disable

TRANSMIT COUNT ACK

TD_AUTONEG mv_start_delimiter

TRANSMIT ABILITY

tx_bit_cnt 1tx_link_code_word[64:49] CRC16(tx_link_code_word[48:1])

TRANSMIT DATA BIT

start interval_timerif (tx_link_code_word(tx_bit_cnt) = 1)

then TD_AUTONEG transitionelse TD_AUTONEG idle

tx_bit_cnt tx_bit_cnt + 1

power_on = true +mr_main_reset = true +mr_autoneg_enable = false +an_link_good = true +transmit_disable = true

complete_ack = false +transmit_ability = true +transmit_mv_start_done

remaining_ack_cnt = done +ack_finished = true +complete_ack = false

transmit_DME_wait false

UCT

transmit_DME_wait = false

transmit_mv_end_done +remaining_ack_cnt = done

complete_ack = true +transmit_mv_start_done

UCT

UCT

interval_timer_done

transmit_mv_end_done +remaining_ack_cnt = not_done

transmit_mv_start_done

interval_timer_donetx_bit_cnt = 64





Figure 98–9—Receive state diagram

detect_mv_start = true *

detect_mv_end = true *

UCT

an_link_good = true +mr_autoneg_enable = false +power_on = true +mr_main_reset = true +

UCT

page_test_max_timer_done

page_test_max_timer_done

transmit_disable = true

IDLE

an_receive_idle truereceive_DME_active false

DELIMITER WAIT

receive_DME_active truestart rx_wait_timer

DME_CAPTURE

rx_bit_cnt 0start page_test_max_timerreceive_DME_active true

DME CLOCK

start data_detect_max_timerstart data_detect_min_timerrx_bit_cnt rx_bit_cnt + 1start clock_detect_max_timerstart clock_detect_min_timer

detect_transition = true *receive_blind = false *

clock_detect_min_timer_done *clock_detect_max_timer_not_done

DME DATA_1

rx_link_code_word[rx_bit_cnt] 1DME DATA_0

rx_link_code_word[rx_bit_cnt] 0

detect_transition = true *receive_blind = false *data_detect_min_timer_done *data_detect_max_timer_not_done

A

detect_transition = true *receive_blind = false *

clock_detect_min_timer_done *clock_detect_max_timer_not_done

receive_blind = false detect_mv_start = true *receive_blind = false

rx_wait_timer_done

A

detect_mv_end = true *receive_blind = false A

receive_blind = false





Figure 98–10—Half-duplex state diagram

BLIND

transmit_DME_wait truereceive_blind truestart blind_timer

RECEIVE WAIT

start backoff_timerreceive_blind false

RECEIVE ACTIVE

stop backoff_timerstart receive_DME_timer

SILENT

stop receive_DME_timerstart silent_timer

TRANSMIT ACTIVE

transmit_DME_wait falsereceive_blind true

an_link_good = true +mr_autoneg_enable = false +power_on = true +mr_main_reset = true +transmit_disable = true

blind_timer_done

receive_DME_active = true

receive_DME_active = false

silent_timer_done

receive_DME_timer_done

backoff_timer_done

transmit_DME_done = true





98.6 Protocol implementation conformance statement (PICS) proforma for Clause 98, Auto-Negotiation for Single Differential-Pair Media1

98.6.1 Introduction

The supplier of a protocol implementation that is claimed to conform to Clause 98, Auto-Negotiation forSingle Differential-Pair Media, shall complete the following protocol implementation conformancestatement (PICS) proforma. A detailed description of the symbols used in the PICS proforma, along withinstructions for completing the PICS proforma, can be found in Clause 21.

98.6.2 Identification

98.6.2.1 Implementation identification

98.6.2.2 Protocol summary


Supplier






Identification of protocol standard IEEE Std 802.3bp-2016, Clause 98, Auto-Negotiation for Single Differential-Pair Media



Date of Statement





98.6.3 General

98.6.4 DME transmission


G1 Single twisted-pair Auto-Negotiation function

98.2 Provide Auto-Negotiation transmit, Auto-Negotiation receive, Auto-Negotiation half-duplex, and Auto-Negotiation arbitration

M Yes [ ]

G2 Auto-Negotiation functions 98.2 M Yes [ ]


DME1 DME pages 98.2.1.1 Not be transmitted when Auto-Negotiation is complete and the highest common denominator PHY has been enabled.

M Yes [ ]

DME2 DME page encoding levels 98.2.1.1.1 Transmit either a +1 or –1 level M Yes [ ]

DME3 DME Page 64 odd-numbered transmission positions

98.2.1.1.1 Contain a transition M Yes [ ]

DME4 DME Page 64 even-numbered transmission positions

98.2.1.1.1 Represent data M Yes [ ]

DME5 DME Page first 48 even-numbered positions

98.2.1.1.1 Carry the data of the Auto-Negotiation page

M Yes [ ]

DME6 CRC16 98.2.1.1.1 Comply with Figure 98–3 and initialize 16 delay elements to zero

M Yes [ ]

DME7 Timing parameters for DME pages

98.2.1.1.2 Table 98–1 M Yes [ ]

DME8 DME page period, T1 98.2.1.1.2 30.0 ns ± 0.01% M Yes [ ]

DME9 DME page transitions 98.2.1.1.2 Occur within ± 0.8 ns of their ideal position

M Yes [ ]N/A [ ]

DME10

Transmit differential signal at the MDI

98.2.1.1.4 Within range of 1 V ± 30% peak-to-peak when measured in reference to a 100 termination

M Yes [ ]





98.6.5 Link codeword encoding


DT1 Base Page transmitted within a DME page

98.2.1.2 Convey the encoding shown in Table 98–2

M Yes [ ]

DT2 Encoding for link codeword(s) used inside a Next Page exchange

98.2.1.2 In a DME page, D0 is the first bit transmitted

M Yes [ ]

DT3 RF, ACK, NP bits 98.2.1.2 Function as specified in 98.2.1.2.7, 98.2.1.2.8, and 98.2.1.2.9, respectively

M Yes [ ]

DT4 Reserved combinations of the Selector Field

98.2.1.2.1 Not be transmitted M Yes [ ]

DT5 Echoes Nonce Field bad 98.2.1.2.2 Contain logical zeros when the device does not receive a DME page with good CRC16

M Yes [ ]

DT6 Echoed Nonce Field good 98.2.1.2.2 Contain the value received in the Transmitted Nonce Field from the link partner when the device has received a DME page with good CRC16

M Yes [ ]

DT7 Generate a new Transmitted Nonce Field value for each entry to the Ability Detect state

98.2.1.2.3 M Yes [ ]

DT8 Matching T[4:0] 98.2.1.2.3 Invert T[0] bit and regenerate a new random value for T[3:1]

M Yes [ ]

DT9 Support the data service ability for a technology it advertises

98.2.1.2.4 M Yes [ ]

DT10 Acknowledge bit with no Next Page

98.2.1.2.8 Set to 1 after the reception of at least one DME page with correct CRC

M Yes [ ]

DT11 Acknowledge bit with Next Page

98.2.1.2.8 Set to 1 after the device successfully receives reception of at least one DME page with correct CRC and remain set until Next Page information has been loaded

M Yes [ ]

DT12 No Next Page to send 98.2.1.2.9 Set Next Page to 0 M Yes [ ]

DT13 Next Page to send 98.2.1.2.9 Set Next Page to 1 M Yes [ ]

DT14 No Next Page to send and link partner Next Page is set to 1

98.2.1.2.9 Transmit Next Pages with Null message codes and the Next Page set to 0

M Yes [ ]

DT15 Transmit Switch function 98.2.1.3 Enable the transmit path from a single technology-dependent PHY to the MDI once Auto-Negotiation has completed

M Yes [ ]





DT16 Transmit Switch function during Auto-Negotiation

98.2.1.3 Connect only the DME page generator controlled by the Transmit State Diagram to the MDI

M Yes [ ]

DT17 Signal at the MDI 98.2.1.3 Conform to all the PHY’s specifications when a PHY is connected to the MDI through the Transmit Switch function

M Yes [ ]






98.6.6 Arbitration function requirements


AF1 Regeneration request 98.2.4.1 Cause Arbitration function to disable all technology-dependent PHYs and halt any transmit data and link transition activity until the break_link_timer expires

M Yes [ ]

AF2 break_link_timer expires 98.2.4.1 Resume Auto-Negotiation M Yes [ ]

AF3 Priority Resolution function 98.2.4.2 Highest priority is assigned to the single PHY enabled to connect to the MDI by Auto-Negotiation

M Yes [ ]

AF4 Receipt of a Technology Ability Field with a bit that is reserved

98.2.4.2 Ignore the bit for priority resolution

M Yes [ ]

AF5 No common technology 98.2.4.2 Value “NULL” is assigned to HCD

M Yes [ ]

AF6 Next Pages message encodings 98.2.4.3 Have a Message code that defines how the Unformatted code will be interpreted for each series of Next Pages

M Yes [ ]

AF7 Completed transmission of Next Page information

98.2.4.3 Transmit Next Pages with Null message codes and the NP bit set to 0

M Yes [ ]

AF8 Receipt of Message Pages with Null message codes

98.2.4.3 End of its link partner’s Next Page information

M Yes [ ]

AF9 Next Page encoding 98.2.4.3.1 Shown in Table 98–5 and Table 98–6

M Yes [ ]

AF10 NP, Ack, MP, Ack2 and T bits 98.2.4.3.1 Function as specified in 98.2.1.2.9, 98.2.1.2.8, 28.2.3.4.5, 28.2.3.4.6, and 28.2.3.4.7, respectively

M Yes [ ]

AF11 Message Next Pages 98.2.4.3.1 MP bit set to 1, D[10:0] encoded as a Message Code Field, and D[47:16] encoded as Unformatted Code Field

M Yes [ ]

AF12 Unformatted Next Pages 98.2.4.3.1 MP bit set to 0, D[10:0] and D[47:16] encoded as the Unformatted Code Field

M Yes [ ]

AF13 Next Page exchange 98.2.4.3.1 Continue until neither device on a link has more pages to transmit

M Yes [ ]

AF14 Next Page with Null Message Code Field value

98.2.4.3.1 Sent if the device has no other information to transmit

M Yes [ ]





98.6.7 Service primitives

98.6.8 State diagram and variable definitions


TDI1 link_status parameter 98.4.1.1 OK, FAIL MDIO:M Yes [ ]

TDI2 Receipt of link_status primitive

98.4.1.3 Comply with Figure 98–7 M Yes [ ]

TDI3 link_control parameter 98.4.2.1 DISABLE, ENABLE M Yes [ ]

TDI4 link_control=DISABLE 98.4.2.1 Used by Auto-Negotiation to disable PMA processing

M Yes [ ]

TDI5 link_control=ENABLE 98.4.2.1 Used by Auto-Negotiation to turn control over to a single PMA for all normal processing functions

M Yes [ ]

TDI6 Generation of link_control primitive

98.4.2.2 Generated by Auto-Negotiation function

M Yes [ ]

TDI7 Auto-Negotiation enabled upon power-on or reset

98.4.2.2 Issue PMA_LINK.request(DISABLE) message to all technology-dependent PMAs

M Yes [ ]


SD1 Auto-Negotiation 98.5.5 Implement Figure 98–7, Figure 98–8, and Figure 98–9

M Yes [ ]

SD2 State diagrams 98.5.5 State diagrams take precedence when ambiguity exists between state requirements and the state diagram

M Yes [ ]

SD3 backoff_timer 98.5.2 Expire according to the formula described in 98.5.2

M Yes [ ]

SD4 blind_timer 98.5.2 Expire 2000 ns to 2120 ns after being started

M Yes [ ]

SD5 break_link_timer 98.5.2 Expire 300 µs to 305 µs after being started

M Yes [ ]

SD6 clock_detect_max_timer 98.5.2 Expire 63 ns to 75 ns after being started or restarted

M Yes [ ]

SD7 clock_detect_min_timer 98.5.2 Expire 45 ns to 57 ns after being started or restarted

M Yes [ ]

SD8 data_detect_max_timer 98.5.2 Expire 33 ns to 45 ns from the last clock transition

M Yes [ ]

SD9 data_detect_min_timer 98.5.2 Expire 15 ns to 27 ns from the last clock transition

M Yes [ ]





SD10 interval_timer 98.5.2 Expire 30 ns ± 0.01% from each clock pulse and data bit

M Yes [ ]

SD11 link_fail_inhibit_timer 98.5.2 Expire 97 ms to 98 ms after entering the AN LINK GOOD CHECK state

M Yes [ ]

SD12 page_test_max_timer 98.5.2 Expire 4800 ns to 4920 ns after being started or restarted

M Yes [ ]

SD13 receive_DME_timer 98.5.2 Expire 6805 ns to 6925 ns after being started

M Yes [ ]

SD14 rx_wait_timer 98.5.2 Expire 15 µs to 17 µs after being started or restarted

M Yes [ ]

SD15 silent_timer 98.5.2 Expire 2120 ns to 2240 ns after being started

M Yes [ ]






Annex 97A

(normative)

Common mode conversion test methodology

97A.1 Introduction

This annex describes the test methodologies that shall be used to measure the 1000BASE-T1 link segmentdifferential to common mode conversion loss specified in 97.6.1.4.

97A.2 Test configuration and measurement

The common mode conversion loss is measured in a specified test environment to ensure repeatability.Individual test fixtures are illustrated in Figure 97A–1 and Figure 97A–2. The 1000BASE-T1 link segmentis placed on a reference plane raised 10 cm from the surface of the ground plane.

To avoid ground-plane edge effects the 1000BASE-T1 link segment is placed 30 mm from the edge of theground plane, this same spacing is used between adjacent sections of the same link segment to avoidunwanted coupling. The link segment parameters specified in 97.6 are to be measured using Annex 97Amethodology.

Figure 97A–1—Four-port test setup

VNASddxySccxySdcxy

Link segment under test, meandered if necessary.

Notes:1. Two DM/CM test fixtures are used for all 4-port differential mode and common mode measurements.2. Brackets provide reference “0V” for CM at the ends of DUT and VNA cables.3. The entire setup is on a large metal GND plane , which extends at least 30mm beyond the setup.

DM/CM TEST FIXTURES FOR DM and CM MEASUREMENTS (4-port)

FOAM, r 1.4

LARGE METAL GROUND PLANE

TOP VIEW

SIDE VIEW

30m

m

30mm

FOAM, r 1.430m

m

VNA

30mm 30mm

30m

m

H=10mm±10%

VNA common-mode impedance is set to 200Ω on both differential ports

METAL BRACKETS CONNECT GND PLANE AND TEST FIXTURES





Figure 97A–2—Three-port common mode conversion loss measurement

Link segment under test, meandered if necessary.

Notes:1. The 50 Ω 0.1% resistors are RF-type SMD 0805 or smaller, e.g. Vishay FC series thin-film resistors.2. Brackets provide reference “0V” for CM at the ends of DUT and VNA cables.3. The entire setup is on a large metal GND plane , which extends at least 30mm beyond the setup.


FOAM, r 1.4


TOP VIEW

SIDE VIEW

30m

m

30mm

FOAM, r 1.430m

m

VNASdsxy

30mm 30mm

30m

m

VNA

H=10mm±10%

VNA common-mode impedance set to:

- 200Ω common-mode ondifferential port

- 100Ω on single -ended port*

* The resistive network provides 100Ω in series with the VNA setimpedance of 100Ω, resulting in 200Ω termination for common mode. METAL BRACKETS CONNECT GND

PLANE AND TEST FIXTURES





97A.3 Protocol implementation conformance statement (PICS) proforma for Annex 97A, Common mode conversion test methodology2

97A.3.1 Introduction

The supplier of a protocol implementation that is claimed to conform to Clause 97A, Common modeconversion test methodology, shall complete the following protocol implementation conformance statement(PICS) proforma. A detailed description of the symbols used in the PICS proforma, along with instructionsfor completing the PICS proforma, can be found in Clause 21.

97A.3.2 Identification

97A.3.2.1 Implementation identification

97A.3.2.2 Protocol summary

2Copyright release for PICS proformas: Users of this standard may freely reproduce the PICS proforma in this subclause so that it canbe used for its intended purpose and may further publish the completed PICS.

Supplier




NOTE 1—Only the first three items are required for all implementations; other information may be completed as appropriate in meeting the requirements for the identification.

NOTE 2—The terms Name and Version should be interpreted appropriately to correspond with a supplier’s terminology (e.g., Type, Series, Model).

Identification of protocol standard IEEE Std 802.3bp-2016, Clause 97A, Common mode conversion test methodology



Date of Statement





97A.3.3 Major capabilities/options


CMC1 1000BASE-T1 test methodologies

97A.1 Used to measure the 1000BASE-T1 link segment differential to common mode conversion loss specified in 97.6.1.4

M Yes [ ]No [ ]





Annex 97B

(normative)

Alien Crosstalk Test Procedure

97B.1 Introduction

Annex 97B describes a procedure for measuring ANEXT loss and AFEXT loss between pairs of adjacentlink segments consisting of cables and in-line connectors.

The procedure is required to assess the alien crosstalk performance of the link segments as specified in97.6.3 and 97.6.4. This procedure is intended for use in the laboratory, to evaluate that the link segmentscomplies with the PSANEXT loss and PSAACRF requirements, when properly installed.

97B.1.1 Alien crosstalk test configurations

The limits for PSANEXT and PSAACRF are based on the alien crosstalk test configurations in Figure 97B–2,Figure 97B–3, Figure 97B–4, and Figure 97B–5. The automotive link segment test configurations arederived from two automotive industry use cases representative of common scenarios.

Measurements to be performed at 23°C ± 5°C relative humidity 25% to 75%.

Multiport test fixtures are used for multiport link segments. The number of disturbing ports to be included inthe power sum calculation is dependent on the configuration. Significant connectors may be located in thesame or other mounting systems in close proximity and are assessed as follows. For any given configuration,the determination of which ports to be included can be made based on the ANEXT loss contribution to thedisturbed port. If at any frequency point the ANEXT measurement is less than 90 dB, then the entireANEXT loss and PSAACRF response of that connector combination shall be included in the overall powersum result.

Link segment ends not under test are terminated in 100 differential mode and 200 common mode.

97B.2 Alien crosstalk coupled between type A link segments

The use case 1 alien crosstalk test configuration consists of three link segments of 5 m length and two in-lineconnectors, equally spaced at 1.66 m distance.

The use case 2 alien crosstalk test configuration consists of 5 link segments bundled together over a 5 mlength with the center link segment extending unbundled for 3 m. The 3 m unbundled section includes2 in-line connectors in addition to the 2 in-line connectors in the 5 m bundled section.

The alien crosstalk measurements are to be performed utilizing the test setup and methodology specified inAnnex 97B.





97B.3 Cable bundling

The cable bundle shall be placed on dielectric insulation material (R < 1.4) of 10 mm height overconducting ground plane. The cables are uniformly fixed in their position by means of cable straps oradhesive tape to keep the cables attached together with a maximum distance between the fixation devices of30 cm.

The measurement test fixtures are to be connected to the reference ground plane by means of conductingstands, copper braid, or foil.

If it is necessary to split up the wiring harness at the end of the bundle in order to accommodate themeasurement fixtures, the length of the area split up is limited to the maximum of 30 cm.

An example of cable bundling for the 2-around–1 alien crosstalk test configuration is illustrated inFigure 97B–4.

An example of cable bundling for the 4-around–1 alien crosstalk test configuration is illustrated inFigure 97B–5. For use case 2, the link segment extending unbundled for 3 m is centered in the cable bundlee.g., cable 2 in Figure 97B–5.

Figure 97B–1—Alien crosstalk test setup

VNASddxySccxySdcxy

Notes:1. Two DM/CM test fixtures are used for all 4-port differential mode and common mode measurements.2. Brackets provide reference “0V” for CM at the ends of DUT and VNA cables.3. The entire setup is on a large metal GND plane , which extends at least 200mm beyond the setup.


FOAM, r 1.4


TOP VIEW

SIDE VIEW

>200

mm

FOAM, r 1.4>200

mm

VNA

>150mm

>150

mm

VNA common-mode impedance is set to 200Ω on both differential ports

H=10mm±10%

METAL BRACKETS CONNECT GND PLANE AND TEST FIXTURES

Alien crosstalk test configuration Figure 97B-2 through Figure 97B-4





Figure 97B–2—Use Case 1 test configuration

test fixture

test fixture

1.66m 1.66m 1.66m in-line in-line

Height to bundle(H = 10 mm ± 10 %) GroundGround

Figure 97B–3—Use Case 2 test configuration

test fixture test

fixture

test fixture1.66m 1.66m 1.66m 1.5m 1.5m

GroundGround

in-line in-line in-line in-line

Height to bundle(H = 10 mm ± 10 %)

Figure 97B–4—Cable bundle in 2-around–1 configuration

3

1 2

10 mm

Figure 97B–5—Cable bundle in 4-around–1 configuration

54

1 2 3

10 mm





97B.4 Protocol implementation conformance statement (PICS) proforma for Annex 97B, Alien Crosstalk Test Procedure3

97B.4.1 Introduction

The supplier of a protocol implementation that is claimed to conform to Clause 97B, Alien Crosstalk TestProcedure, shall complete the following protocol implementation conformance statement (PICS) proforma.A detailed description of the symbols used in the PICS proforma, along with instructions for completing thePICS proforma, can be found in Clause 21.

97B.4.2 Identification

97B.4.2.1 Implementation identification

97B.4.2.2 Protocol summary

3Copyright release for PICS proformas: Users of this standard may freely reproduce the PICS proforma in this subclause so that it canbe used for its intended purpose and may further publish the completed PICS.

Supplier






Identification of protocol standard IEEE Std 802.3bp-2016, Clause 97B, Alien Crosstalk Test Procedure



Date of Statement





97B.4.3 Major capabilities/options


ACTP1 Sum of ANEXT loss and PSAACRF response

97B.1.1 Include entire ANEXT loss and PSAACRF response of connector combination in the overall power sum result, if at any frequency point the ANEXT measurement is less than 90 dB

M Yes [ ]No [ ]

ACTP2 Cable bundle placement 97B.3 On dielectric insulation material (R < 1.4) of 10 mm height over conducting ground plane

M Yes [ ]No [ ]





Annex 98A

(normative)

Selector Field definitions

98A.1 Introduction

The Selector Field, S[4:0] in the link codeword, shall be used to identify the type of message being sent byAuto-Negotiation. The following table identifies the types of messages that may be sent. The Selector Fielduses a 5-bit binary encoding, which allows 32 messages to be defined. All unspecified combinations arereserved. Reserved combinations shall not be transmitted.

Table 98A–1—Selector Field Encoding

S4 S3 S2 S1 S0 Selector description

0 0 0 0 0 Reserved

0 0 0 0 1 IEEE Std 802.3

0 0 0 1 X Reserved

0 0 1 X X Reserved

0 1 X X X Reserved

1 X X X X Reserved





Annex 98B

(normative)

IEEE 802.3 Selector Base Page definition

98B.1 Introduction

This annex provides the Technology Ability Field bit assignments, Priority Resolution table, and MessagePage transmission conventions relative to the IEEE 802.3 Selector Field value within the Base Pageencoding.

The Technology Ability Field is inserted into the Priority Resolution hierarchy and made a part of the Auto-Negotiation process. The relative hierarchy of the existing technologies is designed in such a way thatbackward compatibility with existing Auto-Negotiation implementations is maintained.

Reserved bits shall be transmitted as zeros. This is to ensure that devices implemented using the currentpriority table forward updated priority tables.

98B.2 Selector field value

The value of the IEEE 802.3 Selector Field is S[4:0] = 00001.

98B.3 Technology Ability Field bit assignments

The Technology Ability Field consists of bits D21 through D47 (A0–A26, respectively) in the IEEE 802.3Selector Base Page. Table 98B–1 summarizes bit assignments in the Technology Ability Field. Note that theorder of the bits within the Technology Ability Field has no relationship to the relative priority of thetechnologies.

98B.4 Priority Resolution

Since a local device and a link partner may have multiple abilities in common, a prioritization scheme existsto ensure that the highest common denominator ability is chosen. The following list shall represent therelative priorities of the technologies supported by the IEEE 802.3 Selector Field value, where priorities arelisted from highest to lowest:

Table 98B–1—Technology Ability Field bit assignments

bit Selector description

A0 100BASE-T1 ability

A1 RESERVED

A2 1000BASE-T1 ability

A3 through A26 RESERVED





— 1000BASE-T1

— 100BASE-T1

98B.5 Message Page transmission convention

Each series of Unformatted Pages shall be preceded by a Message Page containing a message code thatdefines how the following Unformatted Pages is used.





Annex 98C

(normative)

Next Page Message Code Field definitions

98C.1 Introduction

The Message Code Field of a message page used in Next Page exchange shall be used to identify themeaning of a message. Table 98C–1 identifies the types of messages that may be sent.

The Message Code Field uses an 11-bit binary encoding that allows 2048 messages to be defined. Allmessage codes not specified shall be reserved.

98C.2 Message code 1—Null Message code

The Null Message code shall be transmitted during Next Page exchange when the Local Device has nofurther messages to transmit and the Link Partner is still transmitting valid Next Pages. See 98.2.4.3 formore details.

98C.3 Message code 5—Organizationally Unique Identifier (OUI) tag code

The OUI tag code message shall consist of a Message Next Page with the message code field 000 0000 0101followed by one Unformatted Next Page defined as follows. The unformatted code field of Message NextPage 5 shall contain the most significant 11 bits of the OUI or CID (bits 23:13) in bits 26:16 (bits U0 to U10)with the most significant OUI or CID bit in bit 26 (bit U10) of the unformatted code field, the next 11 mostsignificant bits of the OUI or CID (bits 12:2) in bits 42:32 (bit U26 to U16) with the most significant bit inbit 42 (bit U26). The unformatted code field of the Unformatted Next Page shall contain the remaining leastsignificant 2 bits of the OUI or CID (bits 1:0) in bits 10:9 (U10 and U9) with OUI or CID bit 1 in bit 10 (bitU10) with the bits 8:0, 26:16 (bits U8 to U0, U21 to U11) as a user-defined user code value that is specific to

Table 98C–1—Message Code Field values

Message code M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Message code

description

0 0 0 0 0 0 0 0 0 0 0 0 Reserved

1 0 0 0 0 0 0 0 0 0 0 1 Null Message

2 to 4 Reserved

5 0 0 0 0 0 0 0 0 1 0 1 Organizationally Unique Identifier Tagged Message

6 0 0 0 0 0 0 0 0 1 1 0 AN device Identifier Tag Code

7 to 2047 1 1 1 1 1 1 1 1 1 1 1 Reserved





the OUI or CID transmitted. The remaining unformatted code field bits in the Message Next Page and theUnformatted Next Page shall be sent as zero and ignored on receipt.

For example, assume that a manufacturer’s IEEE-assigned OUI/CID value is AC-DE-48 and themanufacturer-selected user-defined user code associated with the OUI or CID is 1100 1110 0001 1111 11002.The message code values generated from these two numbers is encoded into the message Next Page andUnformatted Next Page codes, as specified in Figure 98C–1. For clarity, the position of the global broadcastg is illustrated.

NOTE—Figure 98C–1 shows the order Next Pages are transmitted, with the first transmitted Next Page shown in theleftmost position. This bits within each page are shown with the first transmitted bit (i.e., least significant bit) in theleftmost position. This is the same convention for bit order in the figures of Clause 98. Figure 28C–1 uses the oppositeconvention for bit order.

98C.4 Message code 6—AN device identifier tag code

The AN device ID tag code message shall consist of a Message Next Page with the message code field000 0000 0110 followed by one Unformatted Next Page defined as follows. The unformatted fields of thismessage contain the AN device identifier (registers 7.2 and 7.3). The unformatted code field of MessageNext Page 6 shall contain the most significant 11 bits of the AN device identifier (7.2.15:5) in bits 26:16(bits U0 to U10) with the most significant AN device identifier bit in bit 26 (bit U10) of the unformattedcode field, and the next 11 most significant bits of the AN device identifier (bits 7.2.4:0 to 7.3.15:10) in bits42:32 (bit U26 to U16) with the most significant bit in bit 42 (bit U26) of the unformatted code field. Theunformatted code field of the Unformatted Next Page shall contain the remaining least significant 10 bits ofthe AN device identifier (bits 7.3.9:0) in bits 10:1 (bit U10 to U1). Bits 0, 26:16 (bits U0, U21 to U11) of theunformatted code field of the Unformatted Next Page shall contain a user-defined user code value that isspecific to the device identifier transmitted. The remaining unformatted code field bits in the Message NextPage and the Unformatted Next Page shall be sent as zero and ignored on receipt.

Figure 98C–1—Message code 5 sequence

OUI/CID user-defined

binary

g

message code

AC DE 48

1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 1 0 0

0 1 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1

MSB LSB

0 0 1 1 1 1 1 1 1 000 0 1 1 1 0 0 1 1 0 0

0 0 1 1 1 1 1 1 1 0 0

CE 1F C

T, Ack2, MP, Ack and NP bits reserved bits

Message Next Page Unformatted Next PageD

0

D0

D47

D47

1 10 0 0 0 0 0 0 0 0

hexadecimal


IEEE standards.ieee.orgPhone: +1 732 981 0060 Fax: +1 732 562 1571 © IEEE




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지식재산권 확약서 정보

해당 사항 없음


TTAE.IE-802.3bp-2016 ２

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시험인증 관련 사항



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본 표준의 연계(family) 표준



TTAE.IE-802.3bp-2016 ４

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참고 문헌



TTAE.IE-802.3bp-2016 ５

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영문표준 해설서

1. Introduction

이 표준에 해당하는 단일 트위스티드 페어 카퍼 케이블 (twisted pair copper cable)

상에서 1Gb/s 동작을 위한 물리 계층과 관리에 대한 개요, 정의, 약어, 참고 문헌 등을

기술한다.

30. Management

이 표준을 준수하는 시스템의 관리에 있어서 데이터 터미널 장비(DTE)를 위한 계층

관리와 매체 부속 장치(MAU)를 위한 계층 관리를 기술하고 링크 자동 협상 관리에

대해 규정한다.

34. Introduction to 1000 Mb/s baseband network

이 표준에 해당하는 1000 Mb/s 기저 대역 네트워크의 개요를 기술한다.

45. Management Data Input/Output (MDIO) Interface

이 표준을 준수하는 관리 데이터 입/출력 (MDIO) 인터페이스에 대해 기술한다.

MDIO 인터페이스 레지스터를 규정하고 MDIO 인터페이스에 대한 프로토콜 구현 적합성

명세서 (PICS) 형식을 기술한다. MDIO 인터페이스는 STA(Station Management)와 MMD

(MDIO Device) 간 관리 인터페이스를 의미한다

78. Energy-Efficient Ethernet (EEE)

이 표준을 준수하는 에너지 고효율 이더넷 (EEE) 에 대해 규정한다. EEE 는 저전력

유휴(LPI, Low Power Idle) 모드에서의 동작을 지원하기 위해 정의한 물리 계층

기능으로서 EEE 에서의 LPI 모드 타이밍 파라미터를 기술하고 통신 링크 접속 지연을

규정한다.

97. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and

baseband medium, type 1000BASE-T1

이 표준을 준수하는 물리 부호화 부계층 (PCS), 물리 매체 접속 (PMA) 부계층 및

기저 대역 매체인 1000BASE-T1 유형에 대해 기술한다. 1000BASE-T1 서비스


TTAE.IE-802.3bp-2016 ６

프리미티브 및 인터페이스를 규정하고 PMA 의 전기적 규격과 링크 세그먼트 특성을

기술한다. 또한 매체 종속 인터페이스 (MDI)와 관리 인터페이스를 규정하며 환경적 규격,

지연 제약 등에 대해 설명하고 프로토콜 구현 적합성 명세서 양식을 기술한다.

98. Auto-Negotiation for single differential-pair media

이 표준을 준수하는 단일 디퍼런셜 페어 (differential pair) 매체에서의 자동 협상

기능에 대해 기술한다. 기능적 규격을 제시하고 상태 다이어그램 변수를 자동 협상

레지스터로 변환시키는 맵핑과 기술 종속 인터페이스를 규정한다. 자동 협상의 세부

기능 및 상태 다이어그램, 프로토콜 구현 적합성 명세서 양식을 기술한다.

Annex 97A (normative) Common mode conversion test methodology

이 표준을 준수하는 시스템의 공통 모드 변환 시험 방법론에 대해 규정한다. 시스템

구성과 측정 방법, 프로토콜 구현 적합성 명세서 양식을 기술한다.

Annex 97B (normative) Alien Crosstalk Test Procedure

이 표준을 준수하는 시스템의 이질 누화 시험 절차를 규정한다. 타입 A 의 링크 구간

간의 이질 누화와 케이블 번들링(bundling)에 대해 기술하고 프로토콜 구현 적합성

명세서 양식을 기술한다.

Annex 98A (normative) Selector Field definitions

이 표준을 준수하는 선택자 필드를 정의한다.

Annex 98B (normative) IEEE 802.3 Selector Base Page definition

이 표준을 준수하는 IEEE 802.3 선택자 기본 페이지를 정의한다.

Annex 98C (normative) Next Page Message Code Field definitions

이 표준을 준수하는 넥스트 페이지 메시지 코드 필드를 정의한다. 메시지 코드 1 인

널(Null) 메시지 코드, 메시지 코드 5 인 조직 고유 식별자 (Organizationally Unique

Identifier), 메시지 코드 6 인 AN 기구 식별자 태그 코드에 대해 기술한다.


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