TA Omar Akkawi inst.eecs.berkeley/~cs61c-to

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (1) Garcia, Spring 2007 © UCB

TA Omar Akkawi

inst.eecs.berkeley.edu/~cs61c-to

inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures

Lecture 26 CPU Design: Designing a Single-cycle CPU, pt 2

2008-04-02

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How to Design a Processor: step-by-step1. Analyze instruction set architecture (ISA)

=> datapath requirements• meaning of each instruction is given by the register transfers

• datapath must include storage element for ISA registers

• datapath must support each register transfer2. Select set of datapath components and establish clocking methodology

3. Assemble datapath meeting requirements4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.

5. Assemble the control logic


Clocking Methodology

• Storage elements clocked by same edge• Being physical devices, flip-flops (FF) and

combinational logic have some delays • Gates: delay from input change to output change • Signals at FF D input must be stable before active clock

edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay

• “Critical path” (longest path through logic) determines length of clock period

Clk

.

.

.

.

.

.

.

.

.

.

.

.


Register-Register Timing: One complete cycleClk

PCRs, Rt, Rd,Op, Func

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, BRegister File Access TimeOld Value New Value

busWALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

AL

U

5Rd


3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]

op rs rt immediate016212631

6 bits 16 bits5 bits5 bits

immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs RtA

LU

5Rd

But we’re writing to Rt register??


3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]



immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• Already defined 32-bit MUX; Zero Ext?

What about Rt register read??

32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroE

xt 3216imm16

ALUSrc

01

0

1

AL

U

5

RegDst


3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16



32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroE

xt 3216imm16

ALUSrc

01

0

1

AL

U

5

RegDst


3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216

imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

AL

U 0

1WrEn Adr

DataMemory

5

?


3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]

Ex.: sw rt, rs, imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216

imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

AL

U 0

1WrEn Adr

DataMemory

5


3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]

Ex.: sw rt, rs, imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216

imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

AL

U 0

1WrEn Adr

DataMemory

5


3f: The Branch Instruction

beq rs, rt, imm16• mem[PC] Fetch the instruction from memory• Equal = R[rs] == R[rt] Calculate branch condition• if (Equal) Calculate the next instruction’s address PC = PC + 4 + ( SignExt(imm16) x 4 )

else PC = PC + 4




Datapath for Branch Operations• beq rs, rt, imm16

Datapath generates condition (equal)op rs rt immediate

016212631


Already have mux, adder, need special sign extender for PC, need equal compare (sub?)imm16

clk

PC

00

4 nPC_sel

PC E

xt

Adder

Adder

Mux

Inst Address

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

AL

U

5

=

Equal


Putting it All Together:A Single Cycle Datapath

imm16

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrEqual

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

clk

PC

00

4

nPC_sel

PC E

xt

Adr

InstMemory

Adder

Adder

Mux

01

0

1

=AL

U 0

1WrEn Adr

DataMemory

5


An Abstract View of the Implementation

DataOut

clk

5

Rw Ra Rb

RegisterFile

Rd

Data In

DataAddr Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

PC

5Rs

5Rt

32

323232A

B

Nex

t Add

ress

Control

Datapath

Control Signals Conditions

clk clk

AL

U


An Abstract View of the Critical Path Critical Path (Load Instruction) =

Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write

clk

5

Rw Ra Rb

RegisterFile

Rd

Data In

DataAddr Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

PC

5Rs

5Rt

32

323232A

B

Nex

t Add

ress

clk clk

AL

U(Assumes a fast controller)


Administrivia

• Authnews is back up!• The server for off-campus newsgroup access was down for a few days, but it’s back up now, so resume using it.

• Project 1 grading is being looked into.• Many students have had questions about grades for project 1, so the TAs in charge of project 1 are investigating it. Stay tuned for further announcements.

• Homework 6 due Saturday.


Peer Instruction

ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT

A. Our ALU is a synchronous deviceB. We should use the main ALU to

compute PC=PC+4C. The ALU is inactive for memory

reads or writes.


Summary: A Single Cycle Datapath

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrzero

01

0

1

=AL

U 0

1WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel instrfetchunitclk

• We have everything except control signals

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TA Omar Akkawi inst.eecs.berkeley/~cs61c-to