ICM 2003, Dec. 9-1 1, Cairo, Egypt.

Tail Current Flicker Noise Reduction in LC VCOs by Complementary Switched1 Biasing

Ahmed K. Kassim I , Khaled Sharaf ', and Hani Ragaie (1) Mentor Graphics, 5 1 Beirut St., Heliopolis, Cairo 1 1341, Egypt.

(2) Ain Shams University, Faculty of Engineering, 1 Elsarayat St., Abbasia, Cairo, Egypt.

Abstruct-A new LC voltagecontrolled oscillator circuit topology is proposed, in which the flicker noise generated by the tail transistor is noticeably reduced by utilizing the phenomenon of flicker noise intrinsic reduction due to switched biasing. A macro model of MOSFET under switched biasing is used to prove the idea. Circuit simulations are done on two oscillators with the same tail current value; one with fixed biasing and the other with the proposed switching. A 4 dBclHz phase noise improvement is achieved at IkHz frequency offset in the switched biasing scheme under the same power dissipation and tuning range.

Index Terms-Phase noise, voltage-controlled oscillator, impulse sensitivity function

I. INTRODUCTION ow frequency noise can be harmful not only on the low frequency circuits but also on RF circuits. This fact appears strange from the first glance, but knowing that

most of RF circuit has high nonlinearity and/or time variation nature clarifies the flicker noise effect mechanism. Those effects upconvert the flicker noise to higher frequencies impacting the circuit operation. One of the circuits that is greatly affected by the flicker noise upconversion is the voltage-controlled oscillator (VCO). The low frequency phase noise of the MOSFET transistors is upconverted to the oscillation frequency deteriorating the phase noise at offsets that are important for communication systems (such as 60OkHz offset). Because of that upconversion of the flicker noise, the phase noise profile is divided mainly to three regions: - 30dBldecade. -2OdBfdecade and flat region due to noise floor. The flicker noise is the main contributor in the first region while the thermal noise is the main contributor in the other region. A lot of research effort was made in the last decade to avoid the harmful effect of the flicker noise on the oscillator phase noise [l], [3], [6], [7], [8]. Referring to the cross- coupled negative-resistance VCO with tail current I shown in fig .l , it was illustrated in [6] that the main contributor in the - 30dBldecade region is the tail current transistor flicker noise. There are two mechanisms of upconverting the flicker noise of the tail current to tank nodes. The first is through upconverting the noise power directly to the oscillation

L Fig. 1. N-type negative differential resistance VCO.

frequency fo by the mixing effect made by switching transistors. The second meclhanism is through upconverting some of the flicker noise power to 2h by channel length modulation of the tail current transistor. Then, translating such upconverted noise back to J , through mixing effect by the negative G , transistors. For tlhe lirst mechanism, i t was shown in [SI that minimizing the dc component of the impulse sensitivity function (ISF) leads to minimizing the upconvertion of flicker noise to J . This can be done by using complementary negative resistance architecture, as shown in fig . I , and adjusting the N and P device geometries such that gmp=gmn. However equalizing the device transconductances of N and P transistors based on simulation does not guarantee matching in reality. Another way has been introduced in [SI to suppress IOW frequency noise. The idea was to put off-chip inductor with a large value on1 the way of the tail current or off- chip capacitor on tail current drain node. Although this solution can be efficient but 11 contradicts thc on-chip solution and this is not the trend of FLF design nowadays. The second mechanism of noise upconversion through the channel length modulation of the tail current has a number of prevention plans. The symmetry of the circuit with respect to the vertical axis including the inductor layout was suggested in [6] to lower the amplitude of the drain node voltage oscillation and hence, minimizing the upconversion to 2J. In the same paper [6] it was suggested to use cascode current source andfor large capacitor from tail current drain to ground. This capacitor

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stabilizes the tail drain voltage and short circuits the upconverted noise preventing it from reaching the tank and contributing to phase noise. It has been shown in [7] that using that capacitor results in reducing the loaded quality factor o f , the tank through loading by the negative G , transistors. The solution suggested in [7] is to add a coil to resonate parasitic capacitance associated with the common source of the two negative G , transistors as shown in fig . I . A new LC voltage-controlled oscillator circuit topology is proposed, in which the flicker noise generated by the tail transistor is noticeably reduced by utilizing the phenomenon of flicker noise intrinsic reduction due to switched biasing. The structure of the paper is as follows. In sec 11, the flicker noise reduction under switched biasing is discussed. A complementary biasing technique is shown in sec. 111. studying its effect on VCO phase noise. In sec. IV a new VCO circuit realizing the switched biasing technique is illustrated. While section V ends with the conclusion.

11. FLlCKER NOISE REDUCTION BY SWITCHED BIASING

A. Physical Phenomenon Comparing the flicker noise of two MOS transistors with

same dimensions, one of them is biased by a fixed bias (fig. 2(a)) and the other is biased by the waveform in fig. 2(b), the flicker noise of the switched one at its "ON" times is 2-3dB lower [ I 1, [3]. Referring to fig. 2(b), as V,, increases, the flicker noise decreases. This flicker noise reduction is reported to reach 7dB [4].

Vd Vd MOS threshold (Vd VBB /

then to the dependent current source attached to the original transistor [2].

~ Fig. 3 shows the noise power behavior for the fixed bias transistor (curve a). the switched bias transistor with classical model (curve b) and switched bias transistor using the proposed macro model (curve c). Bias modulation leads to 6dB reduction in flicker noise [4] as shown in curve b. Another extra 6dB reduction in flicker noise region [4] is pronounced in curve c to match the experimental flicker noise measurements of switched-bias MOSFETs [I]. '

Fig. 2.Tw0 transistors (a) with fixed bias and the (b) with switched bias (freq.=2.68GHz).

l'%e key Point of the switched biasing technique is that it reduces tail current intrinsic flicker noise, relaxing the design task that was mainly concentrating on minimizing flicker noise upconversion. In [3], the same technique has been utilized to reduce the flicker noise of a coupled sawtooth ring Oscillator. Fig. 4 illUStraIeS the basic proposed complenlentary binses architecture. The oscillator designer does not haVC 10 miltch the transconductances of the P-MOS and the N-MOS to reduce the upconversion of the flicker noise. Therefore the two device dimensions can be selected independently. Fig. 5 is the phase noise behavior of three cases. Case a is the phase noise versus frequency for the oscillator in fig. 1 [phase noise =-33.9dBc/Hz @IkHz], case c is the phase noise for the same oscillator with no flicker noise at all for the tail current [phase noise = -36.8dBdHz @IkHz] and case b is the

B. Macro Model for MOSFET under switching The macro-model idea is to perform flicker noise de-

embedding outside the MOSFET as a dependent current source. Thereafler, applying a current mode filter on the flicker noise to model what happens during switching. The characteristics of the current-mode filter are dependent on the switching frequency& [2].

The deembedding is based on subtracting the drain currents of WO transistors having the Same bias point of the original transistor. One of them is totally noiseless and the other has zero thermal noise. This subtraction results in only the bias-dependant flicker noise current. This latter is mirrored

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switched oscillator phase noise [phase noise =-30.2dBc/I I L @ 1 kHz].

CI €

WBB

"th nJ VBB

-U1 V h

t-0

Fig. 4. Proposed complementary architecture.

-1. h

Fig. 5. Case a is the fixed bias VCO phase noise, case b . is the switched VCO phase noise and case c is the phase

noise of VCO with no tail flicker noise.

IV. PRACTICAL IMPLEMENTATION Fig. 6 is the classical oscillator (VCO-I) with the noise filter proposed in [8]. The filter prevents the upconverted noise at the tail drain (to 26) to be downconverted to the oscillator frequency by the aid o f negative G , transistors mixing effect. But there is still a low frequency flicker noise not upconverted

to 2/;,. This will be upconvcrted by the aid of iicgalive G,,, transistors directly to the osciillation frequency. An off-chip solution was introduced in [8] to suppress this noise. Our proposed VCO is showrt in fig. 7 (VCO-11) .The new

oscillator has the same classical oscillator main core but with a substantial difference in both tail current and biasing circuit. The tail current is composed of two transistors having their gates connected to the output of another LC fixed frequency osci Ilator.

The. oscillator is simulated .at 0.35um technology using Eldo-RF simulator. The pow" dissipation is 8,.5mW. The main oscillator frequency i:j 2.33GHz and the biasing oscillator frequency is 2.6861-32. These two frequencies are selected to be unrelated (the reason will be explained in the next paragraph) and distant enough to guarantee a single output oscillation frequency through the main oscillator tank filtering effect.

Fig. 8 shows a comparison of the phase noises'of VCO-I [phase noise= -32.6dBc/Hz @IkHz] and VCO-I1 [phase noise=-36.4 dBc/Hz @, IkHz,] .The improvement is about 3.8dB. This 3.8dB improvement is greater than the improvement in the square wave switching case in Fig. 4 (only 2.3dB). This is attributed to the following. First, the noise spectrum of the biasing oscillator exists only at a very narrow I)antl ticside ils osciilalioii ~rccliiciicy (~.OXGIIY.).AII(I according to the phase noise theory in [5]; the contribution in tFe main oscillator phase noise will not occur if there isino coincidence between any of the biasing oscillator harmonics and main oscillator harmonics. This will happen only if the two frequencies are unrelated. So, it is essential to satisfy this condition (2.33GHz and 2.68GHz are unrelated), otherwise there will be a substantial contribution of the biasing oscillator phase noise in the main oscillator phase noise. Second, due to switching by sine wave there is times in which both transistor are off, so the average of g, summation for both transistor [5.764e-3S] i s less than the avterage of g, summation of both transistors in the case of square wave [7.8e-3S]. Therefore it is expected to have a reduction in flicker noise since flicker noise current is proportional to 9,:.

VC)D '1'

Fig. 6. The fixed bias oscillator typical realization (VCO-I).

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Fig. 7. The proposed circuit to realize the tail current complementary switching (VCO-11).

V. CONCLUSION

A complementary switched biasing technique of an LC CMOS VCO tail current has been proposed. The total phase noise of such scheme has been improved by a factor up to 4dB compared to the classical reported schemes with the same power dissipation and tuning range. The simulation was done using Eldo-RF simulator. A macro model for MOSFET flicker noise reduction under switched biasing has been used in simulation. The technology used in simulation is 0.35um and the power dissipation is 8.5mW.

ACKNOWLEDGMENT

I would like to thank Mentor Graphics Corporation for support by tools and time and I thank specially Dr. Mohamed Tawfik, Egypt Mentor Consulting Manager for his technical and time support. I would like also to thank Mohamed Hassan from Device Modeling team in Mentor Graphics who helped me developing the macro model for the mentioned phenomenon.

REFERENCES

[ I ] A. P. van der Wel, E. A. M. Klumperink, S. L. J Gierkink, R. E. Wassenaar, and H. Wallinga, “MOSFET I/f Noise Measurement Under Switched Bias Conditions,” IEEE Electron Device Letters, Vol. 21, no. I , pp. 43-46, Jan. 2000.

Fig. 8. The comparison of fig .6 oscillator (curve a) and fig. 7 oscillator (curve b).

[2] Ahmed Kamal, Mohamed Hassan, Mohamed Dessouky, Khaled. Sharaf and Hani Ragai, “A Macro Model for Simulation of MOSFET Flicker Noise Reduction by Switched biasing,” To be submitted to IEE Electronic Letters. [3] Eric A. M. Klumperink, Sander L. J. Gierkink, Arnoud P. van der Wel,and Bram Nauta, “Reducing MOSFET l/f Noise and Power Consumption by Switched Biasing, “IEEE Journal of Solid-state Circuits, Vol. 35, no. 7, pp. 994-1001, July 2000. [4] CMOS RF Modeling, Characterization and Applications, Eds. M.Jama1 Deen and Tor A. Fjeldy, World Scieniijic Publishing, Singapore (2002). ISBN 981 -02-4905-5 [5] Ali Hajimiri and Thomas H. Lee, ”A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid- State Circuits, Vol. 33, no. 2, pp. 179-194, Feb. 1998. [6] Bram De Muer, M. Borremans, M. Steyaert, and G. Li Puma, ”A 2-GHz Low-Phase-Noise Integrated LC-VCO Set with Flicker-Noise Upconversion Minimization,” IEEE Journal of Solid-State Circuits, Vol. 35, no. 7, pp. 1034- 1038, July. 2000. [7] Emad Hegazi, Henrik Sjoland, and Asad A. Abidi, “A Filtering Technique to Lower LC Oscillator Phase Noise,” IEEE Journal os Solid-State Circuits, Vol. 36, no. 12, pp. 1921-1930, Dec. 2001. [8] Pietro Andreani, and Henrik Sjoland, “Tail Current Noise Suppression in RF CMOS VCOs,” IEEE Journal of Solid- State Circuits, Vol. 37, no. 3, pp. 342-348, Mar. 2002. [9] Ahmed Kamal, Mentor Graphics Corporation, “A New Low Phase Noise LC Oscillator for RF Applications using Tail Current Flicker Noise Reduction by Complementary Switched Biasing,” patent pending.

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