TAU Panel: Timing constraints: Are they constraining designs or designers

Bruce Zahn

March 2015

Design Flow

• Constraints used throughout entire flow• Must be correct, realistic, understood by multiple tools

• Missing/inconsistent/conflicting constraints lead to problems in optimization• Over constraining may cause implementation tool to thrash

• Multiple constraint inputs must be managed throughout design process• Constraints change throughout flow• Constraint management for hierarchical design flow

Synthesis DFT Placement CTS RouteSignoff

STA

Functional Constraints

IPConstraints

DFT Constraints

• Customer/front end• IP provider• DFT

Source

Hierarchical Constraints

• Design partitioned and implemented in parallel across multiple locations

• Must support top-down and bottom up flow

• Blocks available first

• Top level always comes late

• Constraints flexible to support model or flat (netlist) view of block

• Top and blocks need to be independent to allow concurrent design

• Block constraints slightly pessimistic compared to top

• This may cause some consistency issues

• Do not want to re-open closed blocks due to top level changes

SDC Vs. TCL

• SDC• Common constraint set – consistency across tools

• Must be re-generated • When constraints change• Different configuration of netlist (flat vs. models)

• Machine generated – very difficult to work with (read/edit/debug)• Busses and wildcards expanded

• TCL • Compact, readable and easier to debug/modify

• Support variables, wildcards, conditional statements• Constraint set customized to work with hierarchical flow

• Block represented as model or netlist

• Some tcl commands not understood by all tools

Merged Constraints vs. MCMM

• Implementation using Multi-Corner-Multi-Mode • Resource intensive – many scenarios

• Difficult to check all real paths constrained across all modes

• Need models for all modes

• Not all modes exist due to complexity of constraint generation• Results in some path unconstrained in optimization tool

• Merged Constraints

• Difficult to generate and manage

• Some EDA tools perform mode merging• Time consuming to verify merged constraints

• Many false violations due to transfers that are not real• Func clocks DFT clocks

How can EDA tools help

• Need EDA tools to help manage constraints

• Output constraints in readable format – do not expand

• Improved merged or MCMM flow

• Ability to validate quality of constraints across all scenarios

• Support hierarchical design constraints where blocks may be either:

• Models – cannot see inside

• Flat netlist – can see internals

• Support bottom up flow

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