TDCpix design & what if

TDCpix design & what if

G. Aglieri, P.Jarron, J. Kaplon, A. Kluge, M. Morel, M. Noy, L. Pertktold, K. Poltorak

August 27, 2012

Aug 27, 2012

Outline Description of base line functionality

And backup functions

Data transmission

Status of individual blocks and assembly

A. Kluge 2

Aug 27, 2012

TDCpix block diagram

Aug 27, 2012

simplified TDCpix

A. Kluge 4

Aug 27, 2012

Main data path, serial read-out

A. Kluge 5

Aug 27, 2012

Parallel read out

A. Kluge 6

Aug 27, 2012

TDC serial read-out

A. Kluge 7

Aug 27, 2012

Bandgap override

A. Kluge 8

Aug 27, 2012

Components with no backup

A. Kluge 9

Aug 27, 2012

Clk modes

A. Kluge 10

serialPLL2.4lowClkSync

serialPLL2.4highClkSync

serialPLL3.2

ext320lowClkSync

ext320highClkSync

ext480lowClkSync

ext480highClkSync

pllOverride

# 0 1 2 3 4 5 6 7

code 001110 000110 001100 H110H0 H100H0 H110H1 H100H1 1011H0

clkInDigital

320 320 320 320 320 480 480 320

clkPLL 2400 2400 3200 - - - - 320

clkSync 240 480 320 160 320 240 480 32

clkFIFOread

40 40 53 27 27 40 40 5.3

clkMultiSerial

480 480 640 320 320 480 480 64

clkConfig 320 320 320 320 320 240 240 320

Aug 27, 2012

Serial transmission data rate

20 MHz 2.4 Gbit/s 40 Mwords/s (+21% (132 Mhits/s); + 54% (104 Mhits/s)

27 MHz 3.2 Gbit/s 53 Mwords/s (+60% (132 Mhits/s); + 104% (104 Mhits/s)

A. Kluge 11

Clock divider

2.4/3.2 GHz

1.2/1.6 GHz serial mux & shift (/2)

40/53 MHz parallel_load (/60)

240/320 MHz (/10)

Fifo read

clkSync

2.4/3.2 GHz20 MHzPLL

Aug 27, 2012

Parallel data transmission (multi serial, 48 bits)

48 bits (not 8b10); 4 I/O pairs

Input frequency comes from PLL or from outside

Several modes: mode serialPLL2.4&ext480: clkFIFOread = 40 MHz clkMultiSerial

= 480 MHz 40 Mhits/s (21 % (132 Mhits/s) +54 % (104 Mhit/s)

mode serialPLL3.2: clkFIFOread = 53 MHz clkMultiSerial = 640 MHz 53Mhits/s (+60% (132 Mhits/s); + 104% (104 Mhits/s)

mode ext320: clkFIFOread = 27 MHz clkMultiSerial = 320 MHz 27 Mhits/s (-19 % (132 Mhits/s) +3 % (104 Mhit/s))

mode PLLoverride: clkFIFOread = 5.3 MHz clkMultiSerial = 64 MHz 5.3 Mhits/s (-96 % (132 Mhits/s) -95 % (104 Mhit/s))

mode serialTDC

A. Kluge 12

Aug 27, 2012

Status of blocks and assembly

A. Kluge 13

Aug 27, 2012

TDCpix digital layout

A. Kluge 14

Assembly & power distribution & IO ring

Aug 27, 2012

Quarter chip

A. Kluge 15

Aug 27, 2012

Configuration & dll clk & reset distributor

A. Kluge 16

Aug 27, 2012

Reference digital

A. Kluge 17

Aug 27, 2012

Reference analog

A. Kluge 18

Aug 27, 2012

Temperatur sensor

A. Kluge 19

Aug 27, 2012

IO pads

A. Kluge 20

Aug 27, 2012

IO ring & power distribution

A. Kluge 21

Aug 27, 2012

Data transmission

A. Kluge 22

Aug 27, 2012

Link synchronisation sequence

Initiated upon reset from pin (Sequence of 65536 synch words) reset_cmd command (Sequence of 65536 synch

words) send_k_sync_requ command (as long as the

command is active)

Each synchronisation word consists of: 6*10 bit characters are sent. Each 6* 10 bit character is 5* K28.5 symbols

followed by one K27.7.

A. Kluge 23

Aug 27, 2012

Data transmission Idle command

If no data is transmitted or no frame word is transmitted

the idle command is sent over the link. It is identical to the link synchronisation word

and consists of 5 K28.5 symbols followed by one K27.7

A. Kluge 24

Aug 27, 2012

Data transmission: frame word

Every time coarse counter rolls over after 2048 clk_dll cycles a frame word is sent at the next available word slot. clk_dll frequency where the coarse counter and the frame counter is

advanced can in principle be different from the clk_sync frequency. The time intervall between two frames depends mainly on clk_dll.

However, once a frame request is initiated in the clk_dll domain, this request is ported into the clk_sync domain and is executed at the next word transmission cycle which has a period of 6 clk_sync cycles.

Thus in nominal conditions (clk_sync & clk_dll = 320 MHz) the frame is sent out in average each (1/320 MHz * 2048 =) 6.4 µs. However as 2048 cycles cannot be divided 6 (number of 8b10b words in each data word) the number of word transmission cycles between two frame words toggles between 341 and 342 (2 * 341 and 1 *342 or 2 * 6.39375 µs and 6.4125 µs).

The frame word is defined as follows: word_frame0(27 downto 0) <= frame_counter; word_frame0(36 downto 28) <= hit_counter; word_frame0(42 downto 37) <= qchip_collision_count; word_frame0(46 downto 43) <= “0000” not used; word_frame0(47) <= '1'; --format bit

A. Kluge 25

Aug 27, 2012

Data transmission: frame word

--(47) status bit 1 bit

--(46..43) not used = ‘0‘ 4 bit

--(42..37) # of collisions in previous frame 6 bits 2**6=64, 3.3 MHz*10*6.4us=211hits --> count to 64

allows 1/3 of hits to collide

--(36..28) # of hits in previous frame 9 bits hits per qchip and frame= 130 Mhits/s/4*6.4us=208-> max hits in frame: worst case: clk_dll = 240 MHz

clk_sync = 320MHz clk serial 3200 MHz-> number of -> 2048 / 240 MHz = 8.53 us frame length -> transmission cycles in one frame : 8.53 us *(3200MHz / 60)= 455 -> 9 bit

--(27..0) framecounter 28 bit 2**28*6.4us=1718s

A. Kluge 26

Aug 27, 2012

Data transmission: data word

The data word is sent whenever a hit is available and no word with higher priority needs to be sent.

The data word is defined as follows: (47) Status/data selector 1 bit (46..40) Address 7 bit (90 pixel groups) (39..35) Address-hit arbiter 5 bit (34..30) Address pileup 5 bit (29) Leading coarse time selector 1 bit (28..17) Leading coarse time 12 bit

1bit rollover indicator+2048(11bit)*3.125 ns=6.4 µs (16..12) Leading fine time 5 bit 98 ps -> 3.125 ns (11) Trailing coarse time selector 1 bit (10..5) Trailing coarse time 6 bit 64*3.125 ns = 200 ns (4..0) Trailing fine time 5 bit 98 ps -> 3.125 ns

A. Kluge 27

Aug 27, 2012

Data type The word transmission priority is defined as

follows: send_k_sync_slot_requ (user request) send_testpattern_requ (user request) send_k_word_request (user request) send_serial_time_requ (user request) send_frame_requ send_data_requ

A. Kluge 28

Aug 27, 2012

Configuration register Operation modes and Configuration register

--configuration register

send_k_sync_requ <= configuration_data_int_in(0); default = ‘0’

send_k_word_requ <= configuration_data_int_in(1); default = ‘0’

k_word_type <= configuration_data_int_in(5 downto 2);default = “0000”

enable_serial_time_int <= configuration_data_int_in(6);default = ‘0’

enable_test_pattern_int <= configuration_data_int_in(7); default = ‘0’

new_data_testpattern <= configuration_data_int_in(8); default = ‘0’ --> new_data_testpattern acts as write command for the data_testpattern fifo, --> each 01 transition is used as write cmd

A. Kluge 29

Aug 27, 2012

Configuration register (2)

data_testpattern <= configuration_data_int_in(62 downto 9); default = “00..00” --> Data_testpattern is composed of two words: --> word_test_pattern_int <= data_testpattern (47 downto 0); --> are 6 times 8 bit characters composing the 48 qchip_word, --> K_word is a 6 bit word indicating whether the 6 characters are

to be treated as data or k character.

--> k_word_test_pattern <= data_testpattern (53 downto 48); --54 bit: data_testpattern -> write data into cell 54 of

data_testpattern --> subsequent writing moves write pointer of FIFO so that all 8

FIFO cells can be written --> when test pattern is enabled, all 8 FIFO cells are read

subsequently and pushed into --> the data stream, thus the data stream consists of a multiple of

8 data words.

A. Kluge 30

Aug 27, 2012

TDC serial read-out The 32 bit to 5 bit encoder, group and

column FIFOs in the TDCs are not used.

Instead the two 32 bit fine registers and the 52 bit coarse register of one TDC channel are chained together.

In each quarter chip there are 90 TDC channels and thus 90 serial TDC chains. Each of these chains indicates a new data set by activating its serial_holding bit.

Serial chains are multiplexed into serial & parallel read-out

A. Kluge 31

Aug 27, 2012

ASIC status by Gianluca

Aug 27, 2012NA62 GTK WG

28/8/2012 - TDCpix status

Outline by Gianluca

Progress since last status report (17 Jul 2012)

Status

Road ahead

NA62 GTK WG 28/8/2012 - TDCpix status

Analog blocks

Implementation of Serializers Issue with fast load signals skew discovered Solutions being explored and checked by

simulation

06/02/2012 22/05/2012 17/07/2012 28/08/2012

Distribution of PLL clock TO DO DONE DONE DONE

TO DO DONE RE-DONE! WORKINGTO DO WORKING WORKING WORKING

TO DO TO DO WORKING WORKING

JanTO DO DONE DONE DONETO DO DONE DONE DONE

Temperature interlock TO DO DONE DONE DONETO DO TO DO TO DO TO DO

Karolina

Layout and routing of PLL and serializers custom cellPowering and decoupling of SerializersSignoff verification by analog sims with parasitics

Bandgap for pixels / analog Bandgap for pixels / digital

Functional simlulation of full matrix


Digital blocks

06/02/2012 22/05/2012 17/07/2012 28/08/2012Gianluca

TDC serial readout functionality TO DO DONE DONE DONERevision of timing of building blocks TO DO DONE DONE DONEImport custom blocks into digital TDC flow TO DO DONE DONE DONETDC implementation TO DO WORKING DONE DONEGate level simulation of TDC TO DO TO DO WORKING WORKINGAnalysis of TDC powering TO DO TO DO WORKING DONE

AlexQuarter chip RTL design, all functionalities TO DO DONE DONE DONEQuarter Chip implementation TO DO WORKING DONE DONEGate level simulation of Quarter Chip TO DO TO DO WORKING WORKING

Matthew

TO DO DONE DONE DONEVerification of global DLL clock distribution TO DO DONE DONE DONEModification to global Configuration TO DO WORKING DONE DONE

TO DO TO DO WORKING WORKINGTest pulse trigger buffering and distribution TO DO TO DO DONE DONE

Global DLL clock distribution and sync, implementation

Gate level simulation of global configuration interfacing with slave blocks and pixels

Gianluca Aglieri Rinella


Top level06/02/2012 22/05/2012 17/07/2012 28/08/2012

AlexI/O and Power pads design WORKING WORKING DONE WORKINGTop level schematic TO DO WORKING DONE DONETop level netlist DONE DONE

Sandro

TO DO DONE DONE DONEImplementation of top level including pads TO DO TO DO WORKING WORKINGTop level assembly and sign-off TO DO TO DO TO DO TO DO

EveryoneTop level assembly, contribute TO DO TO DO WORKING WORKINGStatic and dynamic powering needs NA NA NA WORKING

Import SLVS I/O pads from GBT to TDCpix technology

Power de-coupling Need of significant on-chip power decoupling

capacitance identified Specially relevant for digital power domain Addition of on-chip capacitor implies re-spin of

implementation of some blocks Analog and DLL power domains already including

significant decoupling


Status at a glance on 6 Feb 2012


Status at a glance 22 May 2012


Status at a glance 17 July 2012


Status at a glance 28 Aug 2012

Aug 27, 2012

Status Present work:

Progress on design and implementation of all building block Stand-alone functional &sign-off verification for

all blocks in progress Iteration of engineering changes in serializer

circuits Top level EoC and IO and power pad placement

first version completed Assembly of TDCpix digital & DRC & LVS

A. Kluge 41

Aug 27, 2012NA62 GTK WG

28/8/2012 - TDCpix status

Status

Future work: Complete stand-alone sign-off verification for

individual blocks Re-spin implementation of TDC adding

decoupling capacitance Complete implementation of top level:

TDCpix digital & analog TDCpix_top I/O and power pad ring refinements Signal routing Power distribution Sign-off checks

Powering, DRC, LVS, Antenna in TDCpix_top Functional verification of the full chip by

simulation on final netlist functional verification of TDCpix_top_digital & functional verification of TDCpix_top

Documents

TDCpix design & what if