Teaching Computer Design Using Virtual Prototyping

Ronald D. Williams, Senior Member, IEEE, Robert H. Klenke, Senior Member, IEEE,

and

James H. Aylor, Fellow, IEEE

IEEE TRANSACTIONSONEDUCATION,VOL 46 2 2003. , NO. ,MAY

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OverviewI. INTRODUCTION

II. ECE 435 — COMPUTER ORGANIZATION AND DESIGN

III. ECE 436 — ADVANCED DIGITAL DESIGN

IV. AN EXAMPLE FINAL PROJECT

V. CONCLUSION

DISCUSSION

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I. INTRODUCTION

• The Computer Engineering group of the University of Virginia has developed and implemented a sequence of two senior- level courses that fully embrace the concept of virtual prototyping.

• ECE435 — Computer Organization and Design

• ECE436 — Advanced Digital Design

• The rapid increase in complexity and size of digital systems has reduced the effectiveness of old design methodologies based on physical prototyping.

• This virtual prototyping design methodology often permits the first physical prototype to be a manufacturable product.

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I. INTRODUCTION (cont.)• To provide the students with a range of practical pro

totyping experiences• The first design pass uses only design capture and

simulation and serves to convey the basics of design and the tools.

• The second pass involves design refinement and synthesis, and it clarifies the function of design iteration and tradeoff analysis.

• The major effort to design a complete digital processor is effectively completed twice :

- Once as an individual effort during the first course

- Again as a team effort during the second course.

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435II. ECE — COMPUTER ORGA NI ZATI ONANDDESI GN

• A. ECE435 Lectures

• B. ECE 435 Labs

• C. Methodology

• D. Tools

• E. Functional Testing

• F. Results

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A. ECE 435 Lectures• Teach the students the concepts of computer design

at the register transfer level.

• Elements are presented along with...

• Once the students understand the basics of

hardware description, the lectures shift to computer

design and organization.

- Simulation-based design,

- The Hardware Description Language (HDL).

- Computer design techniques and tools,

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• Most of the labs demonstrate how to write, compile,

and simulate VHDL code.

B. ECE 435 Labs

• The major focus of these labs is the design of a data

path and control unit that can implement the instructi

on set architecture (ISA) of a small 8-bit computer c

alled the 35VEE8.

• The instruction set for the 35VEE8 was given to the st

udents at the beginning of the semester in the form of

a programmers reference manual so that they knew

the functionality objectives from the start of their

design.

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B. ECE 435 Labs (cont.)

3) Design, describe in VHDL, and simulate an 8-bit two-to-one multiplexor and an 8-bit transparent latch.

2) Using the 1-bit ALU from the previous laboratory exercise, compose and simulate an 8-bit ALU.

1) Design, describe in VHDL, and simulate a 1-bit arithmetic and logic unit (ALU). Cascaded together, these form an ALU of arbitrary bit width.

• The laboratory assignments…

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B. ECE 435 Labs (cont.)

8) Run a sample program and determine the maximum clock frequency, number of clock cycles, and the average execution time per instruction.

7) Connect the data path and the control unit together.

6) Design and simulate a control.

5) Implement and simulate the data path design.

4) Design a data path on paper that is capable of performing all the specifications for the 35VEE8.

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• The design methodology is a mixture of top down and bottom up.

C. ECE 435 Methodology

- Create a library of register-transfer-level components.

- Proceed to design the data path and control unit for processor

- Return to the top-level specification, the programmer’s reference manual,

top-down manner

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• Design Architect is used for basic VHDL

development work.

D. ECE 435 Tools

• Graphical system composition produces VHDL as

its output for simulation.

• Mentor Graphic’s QuickHDL is used on UNIX

workstations.

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• Individual blocks have been verified, placed together into larger units, and simulated.

E. ECE 435 Functional Testing

• The students must provide simulation results.

• Timing analysis is also required for some of the labs.

• Most students simulate their data path independently from the control unit to make sure that each performs at least a portion of the instructions correctly.

• Next the data path is integrated with the control unit, and individual instruction execution is tested.

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• In each year that the course has been offered, appr

oximately 90% of the class has produced a working

processor at the completion of the class.

F. ECE 435 Results

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III. ECE 436 — ADVANCED DIGITAL DESIGN

• A. ECE436 Lectures

• H. Results

• G. Functional Testing

• F. Construction

• E. Tools

• D. Methodology

• C. ECE 436 Project

• B. ECE 436 Labs

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• The objective of this second course is to implement designs in hardware.

A. ECE436 Lectures

• Logic decomposition => to partition the designs in FPGA or PLD architectures

• The differences among logic families and the advantages and disadvantages

• Discussed and compared to fault models, generation a

nd reduction of fault tables, fault simulation algorithms.

• Testability techniques to assist with debugging

• Different levels of design including: register transfer, logic, algorithm and behavioral, and system level.

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• The laboratory assignments was designed to familiarize the students with the use of the test equipment such as..

B. ECE 436 Labs

- Logic analyzers,

- Oscilloscopes,

- Logic programmers that they use to build and debug their designs.

• The laboratory assignments…

1) Using Actel macros, design an arithmetic logic unit

(ALU) for the 35VEE8 that can be implemented in

an Actel FPGA. Use the ALU and models of discrete

components to implement a 16-bit adder.

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B. ECE 436 Labs (cont.)

4) Use the logic analyzer and oscilloscope to observe operation and measure timing delays for a test circuit implemented using an Actel FPGA and 22V10 PAL.

2) Write a synthesizable behavioral VHDL description of the 35VEE8 ALU. Use the Leonardo synthesis tool to develop a gate level implementation using Actel macros. Incorporate this ALU into the 16-bit adder datapath developed in the previous assignment and test.

3) Write a synthesizable behavioral VHDL description of the memory controller state machine to be used in the 35VEE8 system. Synthesize the gate level implementation using Autologic. Implement that design in a 22V10 programmable array logic (PAL) using the PLDSII tool.

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- Timed to determine the performance of the design.

C. ECE 436 Project

• The second deadline …

- Final demonstration using a benchmark program.

- Final written report for the completion of the project.

• The first deadline …

- The critical design review .

- Presenting overall design methodology and any

risk areas

- The course instructors attempt to ascertain from the presentation that the group’s design is technically

correct and that they are on schedule to complete

the design.

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D. ECE 436 Methodology• top-down manner…

• bottom-up manner…

- Implemented by wire wrapping the programmed chips onto a prototyping board.

- The students implemented their design, completed and verified via extensive simulation.

- The components are wired together to implement the 35VEE8 computer.

- Project is intended to provide practical experience in implementation techniques and teamwork.

- Implementing components in the Actel PFGA parts.

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E. ECE 436 Tools

- VHDL and synthesis => state machines, blocks of

combinational logic such as ALUs and decoders

• The same CAD tools in ECE435 are used…

- Schematic capture => registers, to lay out datapaths

- Functional simulation accomplished by..

2. Placement and routing of the complete FPGA

1. Timing simulations of the entire design

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F. ECE 436 Construction

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• Performed at almost every step through the

prototyping process.

G. ECE 436 Functional Testing

• Broad stage without timing values.

• Functional simulations with a fast edit-simulate-chec

k cycle.

• Tested using standard test bench instruments.

• Routed both gate delays and routing delays

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• Over 80% of the groups to get the prototypes to function correctly for a significant portion of the instruction set.

H. ECE 436 Results

• Only one group has failed to complete a virtual prototype.

• The average time from the beginning of construction is about four days.

• Most of the groups have experienced wiring errors and even some microcode mistakes, but all of these problems were resolvedin a minimum of time and without change to the physical design.

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IV. AN EXAMPLE FINAL PROJECTMDR

IR 0

Reg B

ALU

Reg Z Reg CC$0001$0002

Inc. / Dec.

Mem . Addr. Reg.

Program Counter

SPHSPL

Reg EReg D

IR 1 IR 2

Reg C

Reg AReg X

8 Bit Bus 16 Bit Bus

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IV. AN EXAMPLE FINAL PROJECT

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V. CONCLUSION• The two-course sequence based on virtual prototypi

ng was considered to be a success.

• Student opinion of these courses was very good with many students commenting on the great satisfaction that they enjoyed when they were able to run a program on a computer of their own construction.

• The education of students in simulation-based design is becoming increasingly important.

• A few commented that they gained a much greater understanding of computer architecture fundamentals through this extended design effort.

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DISCUSSION

• The limitation on the number of available Actel FPGAs and the difficulty in making design changes in a wire wrapped board demands extensive simulation to remove functional bugs before construction

• Reducing design cost and time-to-market while allowing a greater exploration of the design space makes it required technology for remaining competitive in today’s digital system market.

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