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Team W1Team W1Design Manager: Rebecca MillerDesign Manager: Rebecca Miller
1. 1. Bobby Colyer (W11)Bobby Colyer (W11)2. Jeffrey Kuo (W12)2. Jeffrey Kuo (W12)3. Myron Kwai (W13)3. Myron Kwai (W13)4. Shirlene Lim (W14)4. Shirlene Lim (W14)
Stage VIStage VI: : February 25February 25hh 2004 2004
COMPONENT SIMULATIONCOMPONENT SIMULATION
Presentation #6: Rijndael Presentation #6: Rijndael EncryptionEncryption
Overall Project Objective:Implement the new AES Rijndael algorithm on
chip
18-525 Integrated Circuit Design Project
StatusStatus
Design Proposal Architecture Proposal Size Estimates/Floorplan Gate Level Design
Schematic Design (Fixed)Input/Output Logic to SBOX Changed and TestedTop Level Schematic Verified – Pipeline Works!
Layout Component Layout (Done—Continually Changing) Simulations (50% Due to Changes in Major Blocks)
To be Done Optimizations Everything else…
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Design Decisions & Design Decisions & ProblemsProblems
DECISIONS Removed XORs from hardcoded values found within:
Round Permutation MixCol XTimeKey Expand
Changed ROM to allow for PrechargingNMOS Pass-Gates Added to Inputs of ROM: Gate Tied to Clock
Added Input and Output Flip-Flops to keep a clean signal
PROBLEMSNeed to Size Gates More Aggressively
ROMDFFXOR (Implemented Using Pass-Transistors!)
New Layout of ComponentsNeed to Be Finalized—Can’t change them everyday!
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ELIMINATION- Eliminate 5 rounds
- Eliminate 1 SBOX & control logic
- Reduce transistor count to 27k
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Old Schematic
(10 Rounds)
New Schematic (5 Rounds)
Mux used in both In and Out logic, moved outside and shared
Mux used in both In and Out logic, moved outside and shared
Verilog Simulation ResultsVerilog Simulation Results
e0 e0 34 34 e7 e7 8b8b
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Schematic Simulation Schematic Simulation ResultsResults
Problems!Problems!
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Schematic Simulation Schematic Simulation Pipelined!Pipelined!
~One Output Per Clock Cycle~~One Output Per Clock Cycle~
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reg [4:0] counterx; always #5 clk = ~clk;initialbegin counterx = 0;end always@(posedge clk) begin counterx = counterx + 1; if (counterx == 21) begin counterx = 0; end end initialbegin clk = 1'b1; rst = 1'b1; #10 rst = 1'b0; #10 rst =1;
@(posedge valid_in); text_in1[31:0] = 32'h00000000; // Expected: 1B3E9EDF key1[31:0] = 32'hFB473859; vin = 1; @(posedge valid_in); key1[31:0] = 32'b00000000000000000000000000000000; text_in1[31:0] = 32'h08f273e6; // Expected: 2DF5C18E vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h10174E72; // Expected: 87FE42E7 vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h30C42168; // Expected: 0BD9AFAC vin = 1; @(posedge valid_in); key1[31:0] = 32'h2F764A41; text_in1[31:0] = 32'h00000000; // Expected: 43B28B72 vin = 1;
@(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h91f0aca1; // Expected: c913f5ed vin = 1; @(posedge valid_in); key1[31:0] = 32'h851b64d9; text_in1[31:0] = 32'h00000000; // Expected: 30d0299b vin = 1;
@(posedge valid_in); key1[31:0] = 32'hc0000000; text_in1[31:0] = 32'h00000000; // Expected: ec4b0b60 vin = 1; @(posedge valid_in); key1[31:0] = 32'hfff80000; text_in1[31:0] = 32'h00000000; // Expected: b3adb97e vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h9b0cb284; // Expected: 69551ee1 vin = 1; #10000 $finish; end
Old Floorplan
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ROM and Control
ROM and Control
Key Expand no pipe
In Logic & Out Logic
In Logic & Out Logic
Round Permutations
Key Expand
Text & Key Output
345 um x 325 um
Updated Floorplan325 um x 330 um
Metal 3
Metal 2
Metal 1
Metal 4
SBOX and Control Logic
Text DFFs and Add RoundKey
5th Round Key Expand
Input to SBOX Logic & SelectOutput and Input Logic
4 Rounds of Key Expand
4 Rounds of Round Permutation
Input/Output Logic
CLKDivider
Select & Input Logic
SBOX and Control LogicFinal Text Out
Key DFFs and Input Logic
Updated Floorplan325 um x 330 um
Key[32]
Text[32]
Metal 3
Metal 2
Updated Floorplan325 um x 330 um
Key[32]
Text[32]
Metal 3
Metal 2
Multiple
Metal 4
Direction
(Where Things Have Already
Been Wired Up – No Global
Routing)
Updated Floorplan325 um x 330 um
Key[32]
Text[32]
Metal 3
Metal 2
Multiple
Metal 4
Direction
(Where Things Have Already
Been Wired Up – No Global
Routing)
Output
ROM Schematic
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ROM Control with PMOS
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Old ROM and Control Logic
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ROM
Control Logic
Control Logic
New ROM and Control Logic (New Row of NMOS: Gates Tied to Clock
to Control Inputs—Allows Precharging)
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ROM
Control Logic
Control Logic
Round Permutation
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Old Round Permutation
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Updated: Round Permutation
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DFFsXORs XORs
Inputs
Key Expand
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Key Expand Layout (Will Be Changed)
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Inputs (M2 Down, M3 Across)
Outputs (M4)
DFFs DFFs1st Level
XORs
SBox Mux Tree In-Logic
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8 x Mux5Previous Logic To ROM
SBOX Select Tree In-Logic
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Current Logic
SBOX Select Tree In-Logic
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Current Logic
Tree Structure Difficult to Implement in Layout
• Needed to finalize wiring from other modules in order to be more efficient in arranging in-logic
•Now: Decided to put next to its corresponding stage
SBox Mux Tree In-Logic
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Current Logic
SBox Mux Tree Out-Logic
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Changes To…XTime (Found in MixCol of RoundPermutations)
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Changes To…XTime (Found in MixCol of RoundPermutations)
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5XORs *
2 XTime
per MixCol *
2 MixCol
Per Round * 4
Rounds = 80 XORs
Changes To…KeyExpand (The Hardcoded RCON Value)
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Changes To…KeyExpand (The Hardcoded RCON Value)
One Row of XORs Eliminated
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16 XORs per KeyExpand * 5 KeyExpands = 80 XORs
Waves D-FlipFlop Layout
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Waves D-FlipFlop Propagation Time
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624.832 ps
Waves D-FlipFlop Rise Time
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1.08073 ns
Waves D-FlipFlop Fall Time
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1.15726 ns
Waves XOR Propagation Time
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174.371 ps
Waves XOR Rise Time
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245.367 ps
Waves XOR Fall Time
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205.155 ps
Waves 4-XOR Propagation Time
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751.512 ps
Waves ROM Propagation Time
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869.757 ps
Waves ROM Control Propagation Time
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124.267 ps
Waves ROM Control Fall Time
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215.59 ps
Waves Longest Logic Path (Not Including
ROM)
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762.727 ps
Current Speed Estimation200 MHz
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18-525 Integrated Circuit Design Project
COMPONENTSCOMPONENTS AREA ESTIMATE (AREA ESTIMATE (umum22))
Key Schedule Registers & XORs 80 um x 40 um x 4 um + 35 um x40 um =
14,200 um2
ROM SBOX and Control Logic (2) 60 um x 250 um x 2 = 30,000 um2
Transformation Register & XORs 70 um x 70 x 4 = 19,600 um2
Add Round Key & Final Text Out
70 um x 15 um x 2 = 2100 um2
Others Buffers & Wiring 10% = 6,590 um2
CURRENT AREA CURRENT AREA DIMENSIONSDIMENSIONS
Total: 330 um x 325 um (taken from current floorplan)
Current Transistor Count with 5 Rounds of Current Transistor Count with 5 Rounds of Encryption Encryption
(Assuming(Assuming 32-bit Implementation) 32-bit Implementation)
Clock Divider 165 Add Round Key 256 Valid Out DFFs (5) 136 SBoxMuxTreeIn (Text) 2336 SBoxMuxTreeIn (Key) 1056 SBoxMuxTreeOut (Text) 3992 SBoxMuxTreeOut (Key) 2038 ROM with New Control Logic (3)
7332 Key Expansion (5) 1920 Round Permutation (4) 5312 Final Text Out 256
Total: 24799Total with Buffer Estimate (10%)
27278
New Total: (From LVS) 25, 23718-525 Integrated Circuit Design Project
Questions?Questions?
18-525 Integrated Circuit Design Project