Technology Roadmap of DRAM for Three Major manufacturers · PDF fileSTT-RAM has to be at least 6F2 to be ... Technology Roadmap of DRAM for Three Major manufacturers ... Technology

Technology Roadmap of DRAM for Three Major manufacturers: Samsung, SK-Hynix and Micron May 2013

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2 I Technology Roadmap of DRAM for Three Major manufacturers: Samsung, SK-Hynix and Micron

Table of Contents 1. Challenges of DRAM and Future of DRAM (ITRS) 2. Different types of scaling 3. JEDEC’s Perspective 4. Industry Status from DRAM manufacturers


Challenges of DRAM Reference: World Semiconductor Trade Statics (WSTS) http://WWW.WSTS.org/

DRAM continues to play a major role in the semiconductor industry. However, DRAM continues to face its three perennial challenges…

http://www.wsts.org/


Industry has been tackling these 3 issues by various methods

Challenges of DRAM

Reduce Power

Consumption


Challenges of DRAM

Bandwidth is the biggest challenge of DRAM Infrastructure includes server, storage and networking.


Challenges of DRAM

Currently process “scaling” option is running out of steam…


The figure was taken from Denali MemCon 2009, in a speech by Samsung's Dr. S. Kadivar

Challenges of DRAM Memory systems are not only the bottle neck of higher system performance due to bandwidth and addressing issues, but also the biggest power consumer in a server.


Challenges of DRAM

What does process scaling do? • Process scaling reduces the cost by decreasing the cell

size

• Process scaling reduces power by lowering operating voltage

• Process scaling combined with right interface increases bandwidth


Challenges of DRAM Process challenges as defined by IITRS roadmap 2011 The challenges for DRAM devices are: • Adequate storage capacitance with reduced feature size, • High-κ dielectrics implementation, • Low leakage access device design • Low sheet resistance materials for bit and word lines. • Higher bit density requires transition from 6F2 to 4F2 which is

challenging as high aspect ratio vertical transistor has to replace recess channel field effect transistor (FET).

International Technology Roadmap for Semiconductors (ITRS). http://public.itrs.net

http://public.itrs.net/


Challenges of DRAM (from ITRS)

“DRAM capacitor technology is now more seriously challenged than any other previous period due to the accelerated scaling of cell size”


Challenges of DRAM (ITRS)

Aspect ratio (A/R) of storage node (SN) is increasing with every technology node. A/R of storage node is calculated as (SN height) / F where is the minimum feature size. A/R of SN (out) is calculated as (SN height) /(F- 2 x t); where t= physical high k dielectric layer thickness.

Pillar type structure


Challenges of DRAM (from ITRS) Source ITRS

All DRAM makers (Samsung, SK-Hynix & Micron) are in 3x node All three are still using 6F2 layout, no transition to 4F2 yet All are using buried wordline structure The mask count for all of them are around 40 The process is already very expensive and there are only 3 players


Challenges of DRAM (from ITRS)

Emerging memory is part of DRAM roadmap…


Challenges of DRAM Maintaining the capacitance with smaller surface areas normally involves thinning the dielectric film that impacts leakage. This implies new materials, new processes new precursors, new tools. With razor thin margins, new investment makes little sense DRAM must make metamorphosis from 1 Transistor+ 1 capacitor to one of the following: • Capacitor-less DRAM • Adopt emerging memory like Spin-Torque-Transfer (STT) MRAM • Continue to exist as embedded memory Conventional DRAM will most likely end around 16 nm.


Challenges of DRAM DRAM Alternatives

Capacitor-less DRAM A significant portion of the technology developed for DRAM is not extendible to advanced technology nodes. In order to overcome cell-area scalability and the process complexity issues of traditional DRAM technology, the concept of capacitorless DRAM was introduced in the early 1990s by “Innovative Silicon” and was called Z-RAM. Z stands for zero capacitor. This concept of Z-RAM has the full potential to be developed on silicon-on insulator (SOI) wafers. Z-Ram uses a floating body and stores data through an application of the floating body effect in the SOI substrate. However, apart from conference proceedings and research papers, this integration scheme is not available in any commercial product.



Adopt emerging memory like Spin-Torque-Transfer (STT) MRAM One possible scenario is spin-torque MRAM (STT-RAM) could replace DRAM and SRAM. It has 1 transistor & 1 Metal Tunnel Junction (MTJ). Magnetization orientations in magnetic multilayers are controlled via spin polarized current. But there are still several challenges, one important aspect is the design layout. STT-RAM has to be at least 6F2 to be competitive with DRAM. Other challenges include controlling the switching currents in the MTJ memory cell. At least some commercial products were made in the past by Grandis, Everspin and others. Samsung has suggested that it would be ready around 2014 with this STT-MRAM device.



Continue to exist as embedded memory Embedded DRAM (eDRAM) has high integration density, allows bringing large memory volume close to computing cores. eDRAM has performance benefits with wide I/O and eliminates chip interface delay eDRAM has power saving as no chip to chip data bus or address bus. eDRAM improves quality as there is better control on soft error. eDram can replace SRAM it provides a competitive solution for many system design challenges. This option is mainly pushed by IBM and recently by Intel. In VLSI 2013, there is a paper by Intel entitled. “ A 22 nm High Performance Embedded DRAM SoC Technology Featuring Tri gate Transistors and MIMCAP COB.”


Challenges of DRAM DRAM Alternatives Continue to exist as embedded memory

Back in 2010 IBM had already demonstrated that in 45 nm SOI-CMOS a 64Mb eDRAM with trench capacitor is faster than SRAM In 2012 IBM demonstrated in 32 nm eDRAM with high-k node and feasibility in 22 nm logic process.



Symposium on VLSI Technology Highlight Papers 22-nm Embedded DRAM SoC Technology featuring Trigate Transistors and MIMCAP COB Mass production of high performance CPU with 22 nm generation CMOS devices has been already started in last year. At this year's Symposium on VLSI Technology, Intel will report technical details of their embedded DRAM with 22 nm generation technology on bulk silicon wafer. They realized 0.029 µm2 DRAM cell capable of meeting >100 µs retention at 95 C. The excellent leakage and performance characteristics of Tri-gate transistors have been optimized for the access transistor, while maintaining the performance needed to enable high performance circuits in the same die. A high aspect-ratio, 3-D Capacitor-Over-Bitline(COB) metal-insulator-metal(MIM) capacitor trench has been integrated into the ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks.

Excellent retention capability and yield have been demonstrated.

Intel is strongly present in eDRAM.

Source: Tip_sheet_2013_VLSI_symp_Tech_April102013_English_Version


Different types of Scaling What happens to “scaling”? IITRS discusses other “scalings” Geometrical (constant field) Scaling—refers to the continued shrinking of horizontal and vertical physical feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) Equivalent Scaling (occurs in conjunction with, and also enables, continued geometrical scaling)—refers to 3-dimensional device structure (“Design Factor”) improvements plus other non-geometrical process techniques and new materials that affect the electrical performance of the chip. Design Equivalent Scaling (occurs in conjunction with equivalent scaling and continued geometric scaling)—refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.


Equivalent Scaling and Design Equivalent Scaling include: Wide I/O, DDR and DIMMs Wide I/O concept This concept aims at increasing the bandwidth between the memory and its driving logic IC by increasing a large “high IO count” data bus between the two circuits. Wide I/O includes through-silicon-vias (TSV), interposers and 3D stacking. Hyper Memory Cube (HMC) is also part of the group Wide I/O group. HMC is actively pursued by Micron and Samsung. JEDEC is also pursuing the concept of 3D technology which stacks DRAM on top of a logic device in a master-slave configuration and has high bandwidth.

Different types of Scaling


Equivalent Scaling and Design Equivalent Scaling DDR Thus the "DDR" in DDR DRAM stands for "Double Data Rate," a name that it gets from this ability to transfer twice the data per clock as an SDRAM. A DDR2 transfers its commands and addresses on the on both the rising and falling edges of the clock. Similarly DDR3 and DDR4 would transfer its commands three times and four times in a cycle. High DDR is effective for large bandwidth. Currently, DDR3 is the mainstream, DDR2 has phased out and DDR4 is being introduced. DDR and Wide I/O are complementary technologies for increasing bandwidth.



Equivalent Scaling and Design Equivalent Scaling DIMMs DIMM stands for dual inline memory module and provide two lines of communication paths between the module and the system, one in the front and one in the back. DRAMs are usually build in dual inline memory modules and one or more DIMMs are connected to a memory controller through a shared data bus forming a memory channel. If a DIMM is not properly designed then there is lot of wastage in memory systems because large number of bits are activated per memory access and most of them are stored back with being altered. JEDEC and memory manufacturers have a roadmap for improving their DIMMs configuration.



JEDEC’s Perspective of DRAM

To stay on Moore’s Law, a server from Oracle/Sun must provide an off-chip bandwidth of 300 terabytes per second (Tbps) by 2020 \ about 100x more than current systems.

JEDEC's DRAM Server Roadmap (Source: JEDEC)


JEDEC’s roadmap, DDR3 now comes in two speed grades: 1,333- and 1,600-MHz. Hynix, Micron and Samsung are developing the next-generation interface — DDR4 and are also actively working on wide I/O.

JEDEC’s Perspective

JEDEC's DRAM Server Roadmap (Source: JEDEC)


Low power DDR and combination of Wide I/O is the solution to tackle the large bandwidth problem. Wide I/O and TSV technology are complementary to DDR interface designs.


http://www.jedec.org/sites/default/files/docs/JESD229.pdf

http://semimd.com/wp-admin/LPDDR4 enters mobile DRAM picture (Source: JEDEC)





JEDEC is advocating the advance of 3D integration, which includes TSV as a major alternative for DRAM impasse, but 3D integration has many challenges too...


Industry Status from DRAM manufacturers

2012 Micron Fall Analyst Conference

MICRON

DRAM consumption is continuously increasing only the focus is changing from PC to mobile and servers. Micron is supporting all segments. Infrastructure (Servers, storage and networking) take 46% of DRAM share.



With every new technology node the cost per bit decreases probably after two more generations, a new memory technology will take the relay.


MICRON

DRAM current status from Micron



Micron has low power DDR3 and has already started shipping DDR4. DDR4 may give 35% power savings and increased speeds compared to DDR3.


MICRON

DDR4

Currently available


Industry Status from DRAM manufacturers MICRON: FUTURE

Micron will introduce the Hybrid Memory Cube (HMC) this year 2013


Industry Status from DRAM manufacturers MICRON: FUTURE

Micron’s HMC will be supported by traditional PCB and advanced Si-interposers

HMC will demonstrate the success of TSV as a reliable and cost effective solution for bandwidth and power reduction


Industry Status from DRAM manufacturers SK-HYNIX

Hynix DRAM is strongly present in the PC sector and mobile devices. Hynix is also active in graphics DRAM.


Industry Status from DRAM manufacturers SK-HYNIX Mobile DRAM

Hynix also like other manufacturers has application specific low-power DRAM.


Hynix is also working in wide I/O and TSV technologies. Hynix is also part of the hybrid-memory consortium. Hynix joined Sematech 3D Interconnect program in 2011

SK Hynix 16 Gb DRAM SK Hynix High Bandwidth Memory (HBM)

Industry Status from DRAM manufacturers SK-HYNIX High Bandwidth Memory (HBM)



Samsung’s 20 nm DDR3 DRAM is already in the market in 2013. Samsung is also transitioning to DDR4 soon. Samsung like Micron is active in the server space and is reducing. Power consumption and increasing bandwidth.

SAMSUNG DRAM


Industry Status from DRAM manufacturers SAMSUNG

Samsung will have wide IO DRAM (Non-JEDEC type ball interface) ready for customer sample in early 2013 and will also have JEDEC standard wide IO DRAM.

Design Automation conference 2012



Samsung is has a strong participation in mobile DRAM

SAMSUNG



Samsung is also a member in hybrid memory cube consortium. Samsung also has a several alternative memories in advanced stage.

SAMSUNG

Samsung product catalogue (Source: Intel developer

Forum 2011)


Process 3x node

Process 2x node

DDR3 DDR4 Wide I/O TSV

Micron 2012 Coming sometime in 2013

Yes Yes HMC in 2013

SK-Hynix 2012 Coming sometime in 2013

Yes ---- HBM 2013-2014

Samsung 2012 Available in 2013

Yes ---- Wide I/O with TSV in 2013


It is difficult to compare across the companies because each of these companies have their primary focus like server, mobile DRAM or thin Notebook and have various products with different voltage and bandwidth specs… Also along with the product the interface with DIMM have to be taken in account.


Industry Status from DRAM manufacturers All manufacturers are designing DRAM for specific applications. There is no universal DRAM for all applications starting from server to mobile DRAM. Interfacing with DRAM and packaging is becoming more important than process technologies. All memory makers are working in parallel with DDR4 and wide I/O-TSV. So packaging and interfacing will improve bandwidth and reduce power consumption. As far process technology is concerned , all memory will most likely transit from conventional DRAM to an emerging memory in the 1x node.


Industry Status from DRAM manufacturers Carry away message Reduction of power consumption and improving bandwidth has become more important than shrinking the process node.

Wide I/O with TSV in DRAMs is coming in the near future 2013-2014

The three perennial challenges of DRAM still remain…

Documents

Technology Roadmap of DRAM for Three Major manufacturers · PDF fileSTT-RAM has to be at least 6F2 to be ... Technology Roadmap of DRAM for Three Major manufacturers ... Technology