Test Benching

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    Simula

    torOperation

    Advance

    dTestbenching

    SimulatorOperation

    FileI/O,A

    utomatedTesting

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    Brie

    fAsidePicoblaze

    Interrupts

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    In

    terrupts

    1ExternalInterruptSource.

    Activehigh,

    leveltrigge

    red.

    Interruptscan

    beenabledanddisabledontheproce

    ssor.Bydefaulton

    power-up

    Orreset,theinterruptsaredisabled(ignored)

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    Inte

    rruptFlow

    Forcestheprocessortojumptoaddress

    0xFFSavestheretur

    naddress

    Savesthez,cflags

    Dis

    ablesfurtherinterrupts

    Presumablyata

    ddress0xf

    fyouhave

    locat

    edajump

    instruction

    whichjumps

    toan

    interruptserviceroutine:i.e.what

    willt

    heprocess

    ordotoha

    ndlethis

    even

    t

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    InterruptTimin

    g

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    R

    ETURNI

    Atthe

    endoftheinterruptserviceroutine,codem

    ust

    haveaRETURNIinstructionsothatflagsare

    restored.

    RET

    URNIEnable

    Enablesinterrupts

    RET

    URNIDisable

    Leavesthemoff

    Notet

    hatinterrupts

    shouldneverb

    eallowedto

    happe

    nwhileservicinganinterrupt(i.e.thereisonly

    a1-d

    eepstackfor

    savingtheflag

    s)

    Notea

    lsothatregistersarenotpre

    served,soyou

    are

    responsibleforyour

    ownrun-timemodel.E.g.if

    an

    ISRdestroysregistercontents,the

    restofthe

    progra

    mmustnotusethoseregisters.

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    EventDr

    ivenSimu

    lation

    TheV

    HDLsimulatorisaneventdriven

    simulator(veryco

    mmonfordigital

    simulation)

    Thesimulatorhas

    aqueueoftransactions

    sch

    eduledforthe

    future,which

    areprocessed

    in

    chr

    onologicalorder

    Eac

    htransactioncanschedulefuturetransactions,

    whichareaddedtothequeue

    d

    0at

    t=3

    f1at

    t=

    6

    g

    0at

    t=6

    d

    1a

    t

    t=8

    Tsim=6

    Future

    transactions

    scheduled

    execute

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    VHDLSimulationTime

    There

    isonesimu

    lationtimefortheentire

    simulatedsystem

    (onemasterclock).

    Simulationisinde

    xedbyanintegerTc.

    Units

    areinsecon

    ds

    Ad

    efaultresolutionisspecifiedwhenthe

    sim

    ulatorisinvokedoften1nsforfunctional

    sim

    ulationand10

    0psfortiming

    simulation

    (de

    pendingontheresolutionof

    themodelsus

    ed).

    Simulationtimebeginsat0s

    Simulationtimeis

    advancedb

    ytheexecution

    ofthesimu

    lationcycletothetimeofthen

    ext

    queuedevent.

    Atransactioncan

    bescheduledimmediately

    using

    de

    lta

    time.

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    VH

    DLSimulationTerminology

    Allsig

    nalshavea

    currentvalu

    eassociated

    withthematalltimesduringasimulation

    Atransact

    ionisanupdateofthecurrent

    value

    ofasignal

    Durin

    gasimulatio

    ncycleinw

    hichasignal

    experiencesatransaction,the

    signalissaidto

    beac

    tive

    Anev

    entisatran

    sactionthat

    resultsina

    changeofvalue

    Proce

    ssescansch

    eduletransa

    ctionstotak

    e

    place

    ontheirout

    putsignals,bothatfuture

    times

    orimmediately.

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    VHDLSimulationCycle

    Thes

    imulationcyclegovernsexecutionofthesimulation.

    Thes

    imulationcycleis

    repeateduntilsim

    ulationterminates.

    Steps

    inthesimulation

    cycle.

    1.Th

    ecurrenttimeTCisassignedthenext

    schedulesimulationtime

    TN.

    2.Ea

    chactivesignalisupdatedwithitsnewvalue.

    3.Processesthataresensitivetosignalsth

    athavejustexperie

    nced

    ev

    entsaremarkedto

    resumeduringthe

    currentsimulation

    cycle,

    as

    wellasprocessesscheduledtoresumeatthecurrenttim

    e.

    4.Ea

    chprocessthatism

    arkedtoresumeisexecuted(innodefined

    orderofprocesses)until(if)itsuspends.

    5.Th

    enextsimulationtimeTNiscalculated

    accordingtothenext

    tim

    easignalissched

    uletobecomeactiv

    eoraprocessis

    scheduledtoresume.

    IfTN=

    TCthenthenext

    simulationcycleiscalledade

    ltacycle.

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    VHD

    LSimulat

    ionCycle,Simplified

    Update

    current

    va

    luesdue

    to

    transitions

    at

    current

    simulationtime

    D

    etermine

    w

    hichsignal

    upd

    atescaused

    events.

    Evaluate

    processes

    sensi

    tiveto

    currentevents,

    schedulingnew

    transact

    ions

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    De

    ltaTime

    Infinitesimallysmall()advan

    ceintime

    Thec

    urrenttimeTCdoesnotadvance

    Aninfinitenumbe

    rofdeltatim

    estepscan

    occur

    betweentagsinthecurrenttimeTC

    Whichdeltacycleisnotacce

    sibleinthe

    langu

    age;dosom

    ethingimm

    ediatelyme

    ans

    doit

    duringthenextcycle,wh

    ichwillbea

    delta

    cycle

    Providesameans

    ofordering

    aneventand

    theeventsthatre

    sultfromit

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    More

    DeltaTim

    e

    . . x