10
Testing and Configuration for VMM1 on the mini-MMFE at Brookhaven National Lab Sarah Jones (Arizona), Jessica Metcalfe (BNL), Charlie Armijo (Arizona)

Testing and Configuration for VMM1 on the mini-MMFE

  • Upload
    pravat

  • View
    49

  • Download
    0

Embed Size (px)

DESCRIPTION

Testing and Configuration for VMM1 on the mini-MMFE. at Brookhaven National Lab Sarah Jones (Arizona), Jessica Metcalfe (BNL ), Charlie Armijo (Arizona). Testing the mini-MMFE. Adapter card, v1. TDO and PDO. FPGA. VMM1 ASIC. USB connection. Timing E xample for New S etup. - PowerPoint PPT Presentation

Citation preview

Page 1: Testing and Configuration for VMM1 on the  mini-MMFE

Testing and Configuration for VMM1 on the mini-MMFE

at Brookhaven National LabSarah Jones (Arizona), Jessica Metcalfe (BNL),

Charlie Armijo (Arizona)

Page 2: Testing and Configuration for VMM1 on the  mini-MMFE

Testing the mini-MMFE

2

VMM1 ASIC

TDO and PDO

USB connection

FPGA

Adapter card, v1

Page 3: Testing and Configuration for VMM1 on the  mini-MMFE

Timing Example for New Setup

3

At peak, ramp begins for timing between peak and readout signals. Slope of ramp gives conversion from voltage to time. Ideally, slope = constant

TAC Slope measurement

y = 0.634x + 189.1

0

100

200

300

400

500

600

700

800

900

0 200 400 600 800 1000 1200

peak to enable time (ns)

TD

O (

mV

)

Timing Measurements, CHN 5

935.000

940.000

945.000

950.000

955.000

960.000

965.000

125 175 225 275 325

Ouput Pulse Amplitude (PDO-BL) [mV]

TD

O t

ime [

ns]

Page 4: Testing and Configuration for VMM1 on the  mini-MMFE

Noise Measurement Example

4

Gain Noise Measurement, CHN 64unmasked nearby channels

0.000

0.100

0.200

0.300

0.400

0.500

0.600

0 50 100 150 200 250

peaking time (ns)

RM

S (

mV

)

Gain 0.5 mV/fC

Gain 1 mV/fC

Gain 3 mV/fC

Gain 9 mV/fC

Noise measurements with RMS vs peaking time for various Gains (0.5, 1, 3, 9 mV/fC)

CHN 64 noise:

Page 5: Testing and Configuration for VMM1 on the  mini-MMFE

PlansTesting of the mini-MMFE was

successful with only minor issuesNext steps are to:

Assemble remaining 10 mini-MMFE (left-handed) this week and begin testing at BNL late next week

Fabricate V2 adapter card (with LVDS to RSDS conversions) this week May not be needed but will have it anyway

Begin layout of right-handed mini-MMFE Few day job 5

Page 6: Testing and Configuration for VMM1 on the  mini-MMFE

Issues with Current Boards

6

Digital ground and digital signal switched

ena and wen signal pins switcheda0-a5 address pins switched in orderTDO and PDO signal connectors

switchedRibbon cables (for 60 to 60 pin) are

difficult to constructSilkscreen issues

Page 7: Testing and Configuration for VMM1 on the  mini-MMFE

VMM1 Readout Plan

7

Page 8: Testing and Configuration for VMM1 on the  mini-MMFE

New “C-Card”

8

AZ Adapter Card (V1)

AVNET LX9 with Spartan 6 FPGA for ethernet connection to switch

Existing BNL DAQ board with ADCs and Cyclone IV for readout, configuration

Page 9: Testing and Configuration for VMM1 on the  mini-MMFE

DAQ Status and PlansUDP datagram sent between client and

server at Arizona Can be used for testing with Mamma

DAQUDP datagram sent from LX9 at Harvard

Will be tested at Arizona this weekCommunication between Jack’s BNL

DAQ board and LX9 progressing well Integration at BNL 7/2 – 7/11 including

George Iakovidis et al.Need meeting with Marcin on Mamma

DAQ end 9

Page 10: Testing and Configuration for VMM1 on the  mini-MMFE

UDP Client

UDP Server

UDP Datagram

ACK

UDP client and server are running on a LAN.

We have sent a big-endian datagram via the UDP client on the laptop, which is a sample event in the current format.

We have received the datagram on a desktop computer and unpacked three 32-bit words of the event to correctly obtain each address, timing, and amplitude included.

The server sends an ack, which in this case completes the transaction.

The Spartan6 LX9 will replace the laptop as soon as we get the compiled image.