EE501 Lab3 Exploring Transistor Characteristics and Design Common-Source

Amplifiers Lab report due on September 22, 2016

Objectives:

1. Be familiar with characteristics of MOSFET such as gain, speed, power,

transconductance, output impedance and etc.

2. Explore how MOSFET I-V curves, gm, gds and Vth vary with device

parameters and operation conditions. 3. Explore the MOSFET speed and gain in term of device parameters and operations

conditions 4. Practice the design of Common-Source Amplifier.

5. Examine trade-off between Gain Bandwidth Product (GBW), open loop gain

(Av0), power (Id), area (transistors size) and linear output range.

Pre-labs: Assuming: transistors operate only in three possible regions: cut-off region, linear

region or saturation region and follow square law in saturation region.

,

.

0.68

0.85

27

110 /

25 /

th NMOS

th PMOS

n ox

p ox

V V

V V

Temp C

C S V

C S V

Derive the following relationships and plot them for both a NMOS and PMOS transistor

with size of W/L=N*1.5um/0.9um, N=1, 4, 16

1. gm vs. VGS , assuming 0 ~ 5 , 5GS DSV V V V

2. vs./

m D

D

g I

I W L

3. You could use MATLAB to build your own MOSFET model to plot the relationship in subthreshold region and saturation region. For those who are interested in compact model for MOSFET, you could refer to the instruction files and MATLAB codes posted on our lab homepage. However, it is not required, just for you to understand the characteristics of MOSFET

Attention:

1. Please carefully read this instruction and there are tips and examples at the end of

this instruction about efficient simulation of multiple parameters.

2. You should study hard and quickly. Do not waste time on repeated and tedious

simulations because that is not the purpose of this class. Try to search through Google

or ask the TA and there must be a simple way to get all required outcome correctly and

quickly.

3. Discipline yourself to work with the correct setup of circuits. If you find anything that

does not cohere with the actual, please tell the instructor or TA.

4. For Tasks A1, 2 and 3, the circuit is usually not biased simply by a single voltage source.

It is just made for you to understand the characteristics of transistors.

Tasks:

A. NMOS transistor

1. With VDS 2V , 3V , 5V , sweep VGS from 0 to 5V, generate ID , gm , gm gds , rds vs. VGS

curves fora. W 6m , L N 0.6 m , N 1, 2, 4

b. W N 1.5m , N 1, 4,16 , L 0.6m

c. W N 1.5m , L N 0.6 m , N 1, 2, 4 (Optional)

d. W 6m 4Multiplier , L 0.6m , Temp 30, 0, 27, 85C

2. With Vgs 0.8V ,1V ,1.7V , sweep Vds from 0 to 5V to generate I

D , g

m , g

m gds , rds

vs. Vds

curves. Repeat a and b in Step 1.

3. Sweep VGS from 0 to 3V, plot ln id vs. vgs v

th and id vs. vgs v

th for

(W 6m 4Multiplier , L 0.6m )

a. VS 0V , 0.5V ,1V (voltage at source node)

b. Temp 30, 0, 27, 85C

4. Sweep drain current ID

from 1nA to 100uA by log scale, generate gm

, gm I

D , g

m gds vs.

current density I D

W L

curves ( VDS

2.5V , VSB

0V ). Repeat a and b in Step 1.

5. Sweep drain current ID

from 1nA to 100uA by log scale, generate unit-gain frequency

(UGF), gain-bandwidth product (GBW) vs. I D curves for W L

a. W 6m , L N 0.6 m , N 1, 2, 4 with 100fF load

b. W N 1.5m , N 1, 4,16 , L 0.9m with 100fF load

c. W 6m 4Multiplier , L 0.6m , load capacitance: CL 100 fF ,1pF ,10 pF ,100 pF

B. Common-Source Amplifier Design a simple current source loaded common source amplifier to complete the

following sub-tasks.

VDD 2.5V ,VSS 2.5V

Output DC voltage: VDC ,OUT 0V (It is for good output swing performance. If it is hard for

you to tune this voltage, you can ignore it.)

1. Given biasing current is Ibias 100 A , manipulate with transistors size to let all transistors

work in saturation.

a. Explain your sizing and biasing strategies.

b. Generate frequency response plot (1~10GHz with AC simulation).

c. Indicate bandwidth, gain bandwidth product, and phase margin in your plot.

2. Given slew rate SR 100V / s, you can select different Ibias and CL (1pF~100pF)

a. Explore the relationship between GBW and transistor size and gm.

b. Summarize in a table.

c. Select one size and summarize the following parameters in a table:

Sizes, Ibias, VGS , VTH , VDS , C L , g m , C g s , DC gain (dB), -3dB bandwidth and GBW

3. Given load capacitance CL=1pF, vary the drain current in a reasonable range (transistors

operate in saturation or weak-inversion region)

Evaluate the variations of slew rate (SR), gm, GBW. Tabulate all the data for different

current.

4. With general requirement:

CL 1pF , Ibias 200 A , GBW 240MHz, and DC Gain>40dB.

a. Design a low power common source amplifier.

b. Design a high speed common source amplifier.

c. Tabulate DC gain, gm, GBW and UGF for a and b including the transistor’s sizes.

Suggestions for this lab:

There are some demos and videos that I made to help you understand how to use

Cadence to do the simulation. The videos will be posted on the homepage. If they are not

available when you want to see them, please let me know so that I can fix the problem.

Task A.

1. For Task A.1

It is better to use “Parametric Analysis” simulation to generate the outputs

together.

i. Set up three circuits simultaneously to cover a, b and c terms.

()

You can use some variables (here is “Np”) for the device’s width and length. As shown in

above figure, for Task A.1.a, the length is “(2**Np)*600n” which means L=2Np 600nm. For

Task A.1.b, the width is “(4*Np)*1.5u” which means W=4Np 1.5 m .

ii. Type the variables in the “Analog Design Environment” as shown below.

iii. Open “Analog Design Environment” from the schematic and click on “Tools”. There it is the “Parametric Analysis” option.

iv. Set up the “Parametric Analysis” as shown below.

The Inclusion List contains all the points required and you may also use different Step Mode and Total Steps (Step Size) to change your sweep. The parameter at the bottom will be the horizontal axis in the output wave window.

If details are to be acquired, the total step of “vgs” in this simulation should be large

enough (101 would be a good choice which indicates 100 intervals, and 201 or 401, etc, for

better details).

However, in this situation the simulation will cause more time. To compromise, more

circuits can be drawn to help get rid of any parameter (for example in this simulation Np or

vds).

2. For Task A.3

“Y vs Y” will be used. For example, plot ln id vs. vgs v

th (Np=0, Vds=2V).

i. First plot ln id and vgs vth with respect to VGS simultaneously.

ii. In the wavescan window, click on “Axis”

iii. Choose the “vgs-vth” output you typed in,

iv. Click OK. 3. For Task A.1.4.a

You can use the following kind of circuits.

Parametric sweep the biasing current and acquire the output waveform.

4. For Task A.1.5 The schematic is shown below.

5. For Task A. 4 and 5, you may use current density as the parameter. It will be easy for you to plot

the results. (As shown in above figure)

6. For Task A.1.d, Step A.3 and Step A.5.d, the width is set as single finger length timing multiplier.

In the actual design, the ratio of width to length of transistor is usually in the range of 0.1 to 10.

Over this range, multiplier will be used to generate larger ratios.

7. Please check docs along with cadence software and there are many good references there. For

example, there are lots of techniques for using wavescan window. You can also find that document

on lab webpage.

Task B

1. For the circuit, you can design by your own experience or use the following circuits as

shown,

2. All bias current refers to the current biasing the common source amplifier which does not include

that in the biasing circuits.

3. For task B.1, since there is no other requirement, you can begin with the biasing current and assign

a reasonable over-drive voltage to solve the transistor’s ratio.

4. For task B.2, after choose the load capacitance, biasing current can be determined by slew rate

(SR). SR can be simply calculated as,

bias

L

ISR

C

5. For Task B.3, two sizes can be chosen to make the common source transistor in saturation and sub

threshold region. You can also use other size to explore the common-source amplifier’s

performance.

6. It is a good choice to set the lengths of transistors to 0.9um which is a commonly used size for

analog circuit designer.

7. Gain Bandwidth Product (GBW) can be viewed as speed indicator.

8. For the low power design, you may begin with the speed requirement.

9. For the high speed design, try to make the speed as high as possible.

10. This kind of common source amplifier is often used as output stage of an operating

amplifier’s differential output. However, because of its characteristics, it is not used as the output

stage by itself but with common mode feedback (CMFB) circuit (Why?). In this lab, the CMFB

circuit’s function is realized by a low pass filter followed by a “vcvs” (CMFB amplifier). It is only

half of the fully differential output.

11. Although the biasing current of the common source amplifier is 100uA, it is better to mirror it from

a relatively small current source which is the typical setup of real circuit design. The current ratio

between branches of current mirror circuits is always less than 10.

Reports 1. Briefly state why you did the lab (purpose).

2. Briefly describe the main tasks and how you did them (what and how)

3. Briefly describe the results (with graphs, tables, explanatory captions)

Present the circuit and the results following the task sequences and present the curves and

tables in ways easy to interpret

4. Briefly state what you have learned

5. Explain all the observations, such as methods to optimize GBW, sizing strategies for high speed or

low power common source amplifier. You may need to provide analysis, theoretical equations to

support your explanations.