The Application in Digital Circuit Teaching of Scicos-HDL

The Application in Digital Circuit Teaching of Scicos-HDL

Dong Zhang , Cai Kang , Jian Guo He

School of Physics & Electrical Information, Ningxia

University, Ningxia, 750021, R.P. China

Email:[email protected]

Abstract. This paper shows the application in digital circuit teaching of Scicos-HDL,including three

main parts : 1)Combinational logic circuit design and Sequential logic circuit design; 2) Circuit

simulation which integrates the Scicos-HDL virtual blocks and the original Scicos blocks; at last, how

Hardware Description Language generated by Scicos-HDL is introduced.

Keywords: VHDL , Verilog , Digital circuit design, SCILAB/SCICOS , Scicos-HDL

release documents:

1 Introduction

Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit,

algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and

Hardware Description Language generation. It is a open source project under LGPL

protocol,its license is under the Scilab ‗s license, the release vision 0.4 can help to design and

simulate some small-scale digital circuit system with its Hardware Description Language

generated. We will make it as a tool for teaching digital circuit design .We have been trying to

improve Scicos-HDL; we expect that Scicos-HDL can be as a Digital signal processing (DSP)

system design tool in the future. Now it supports VHDL&Verilog Languages.

2 Circuit design in Scicos-HDL

At present, Scicos-HDL has three libraries: sequential logic library, combinational logic

library and IPcore library. With these blocks, we can design some circuits and mix-circuits.

The flow of Circuit design In Scicos-HDL environment is that: first ,select the blocks

according what function you want to have in you circuit(ref.3.5); second you can link every

blocks to be as a compete circuit with its functions, and simulate to view the output of your

circuit; then start the two Hardware Description Language compiler to generate

VHDL&Verilog codes of you design. With the Hardware Description Language of you circuit,

you can download them into a FPGA and CPLD.

2.1 Combinational logic circuit design

2.1.1 Combinational logic block

Combinational logic blocks in Scicos-HDL：

name time author

Design and Implementation of EDA Tool Based on Scilab OSSS2005 Dong Zhang ,Zhi-Li Zhang, Cai

Kang ,and Zhen-Zhong Hei

Targeting the Scicos Code Generator HDL Model Example OSSS2006 Dong Zhang and Cai Kang

Table 1: Combinational logic blocks

picture name pins&function

Andgate And gate

The input port can be form 2 to 4

Nandgate Nand gate


Orgate Or gate


Norgate Nor gate

The input port can be form 2 to

Notgate Not gate

De multiplexer De multiplexer 2-1 Pin 1--> control pin

pin 2--> data1

pin 3--> data2

led driver led driver

when input is '0000', the out put will be '1111110'

De multiplexer De multiplexer 4-1

Pin 1,2--> control pin

pin 3--> data1 ,pin 5--> data3 pin 4--> data2 ,pin 6--> data4

encoder4_2 Encoder4_2

this is the truth table of this block: ['1000','0100','0010','0001';'00','01','10','11']

note: pay attention to its input .

Encoder:

8421BCD code

8421BCD Encoder

2_4 decoder

Decoder2_4:

ref to the truth table of this block.

decoder7442 Decoder7442:


4 input ports,10 out put ports

LineDemux LineDemux

The output port can be form 1 to 8 When input port is ‗1‘, the out put is ‗1…‘

When input port is ‗0‘, the out put is ‗0…‘

Encoder

16_4

16 bit – 4 bit encoder.

16 input ports. 4 out put ports

adder8 8 bit adder:

the input (1-8) is for the ‗a‘, and the input(9-16) is for the

‗b‘, inpur(17) is the cin, output(1-8) is for the ‗sum‘, output(9) is the

‗cout‘ .

Till now, we can design small-scale digital circuit in Scicos-HDL, furthermore,Scicos-HDL

allow users to add new blocks designed by themselves .

2.1.2 A Combinational logic circuit design

Description

This is a 16-bit adder circuit, we have two 8-bit adders with 'cin' pin and another adder to be as

a 16-bit adder, we use two LED to show the high bits and the low bits of the output, and the

output 'cout' of the two adders into one 'or gate', to show the result.

8-bit adders : ref. table1. Combinational logic.

LED driver : ref. table1. Combinational logic.

The circuit diagram

16-bit adder circuit,This is the circuit diagram in Scicos-HDL .

Fig. 1. The circuit diagram in Scicos-HDL

Simulation

this is the simulation rezult of the design.

Fig. 2. the simulation rezult of the design

The VHDL&Verilog codes generated by the two compilers:

VHDL Code

`include "adder8nxu.v"

include "led7_4_7.v"

include "orgate_2_1.v"

timescale 1ns/1ns

modulejiafa(NXUin_1,NXUin_2,NXUin_3,NXUin_4,NXUin_5,NXUin_6,NXUin_7,NXUin_8,NXUin_9,

NXUin_10,NXUin_11,NXUin_12,NXUin_13,NXUin_14,NXUin_15,NXUin_16,NXUin_17,NXUin_18,

NXUin_19,NXUin_20,NXUin_21,NXinput

NXUin_1,NXUin_2,NXUin_3,NXUin_4,NXUin_5,NXUin_6,NXUin_7,NXUin_8,NXUin_9,NXUin_10,NXUin_11,

NXUin_12,NXUin_13,NXUin_14,NXUin_15,NXUin_16,NXUin_17,NXUin_18,NXUin_19,NXUin_20,NXUin_21,

NXUin_22,NXUin_23,NXUin_24,NXUin_25,NXUin_26,NXUin_27,NXUin_28,NXUin_29,NXUin_30,NXUin_31,

NXUin_32,NXUin_33,NXUin_34,NXUin_35,NXUin_36;

output

NXUout_1,NXUout_2,NXUout_3,NXUout_4,NXUout_5,NXUout_6,NXUout_7,NXUout_8,NXUout_9,NXUout_10

,NXUout_11,NXUout_12,NXUout_13,NXUout_14,NXUout_15,NXUout_16,NXUout_17;

NXU_s321,NXU_s322,NXU_s323,NXU_s324,NXU_s325,NXU_s326,NXU_s327,NXU_s328,NXU_s329,NXU_s330,

NXU_s331,NXU_s332,NXU_s333,NXU_s334,NXU_s335,NXU_s336,NXU_s340;

wire NXU_s338,NXU_s339;

wire NXU_s346,NXU_s347,NXU_s348,NXU_s349;

wire NXU_s366;

adder8nxuNXUmap1(.in_1(NXU_s154),.in_2(NXU_s155),.in_3(NXs160),.in_8(NXU_s

adder8nxNXUmap3(.in_1(NXU_s213),.in_2(NXU_s214),.in_3(NXU_s215)

adder8nxuNXUmap4(.in_1(NXU_s321),.in_2(NXU_s322),.in_3(NXU_s32

orgate_2_1NXUmap5(.in_1(NXU_s338),.in_2(NXU_s339),.out_1(NXU_s3

led7_4_7 NXUmap6(.in_1(NXU_s346),.in_2(NXU_s347),.in_3(NXU_s34

assign NXUout_1 = NXU_s300;

assign NXUout_2 = NXU_s301;

Verilog Code library IEEE;

use ieee.std_logic_1164.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_unsigned.ALL;

entity jiafa is

port(

NXUin_1: in std_logic;






end jiafa;

architecture NXU_beh of jiafa is

component adder8nxu

port(

in_1,in_2,in_3,in_4,in_5,in_6,in_7,in_8,in_9,in_10,in_11,in_12,in_13,in_14,in_15,in_16,in_

17: in std_logic;

out_1,out_2,out_3,out_4,out_5,out_6,out_7,out_8,out_9: out std_logic);

end component;

component led7_4_7

port(

in_1,in_2,in_3,in_4: in std_logic;

out_1,out_2,out_3,out_4,out_5,out_6,out_7: out std_logic);

end component;

component orgate_2_1

port(

in_1,in_2: in std_logic;

out_1: out std_logic);

..........

The codes above-mentioned is the VHDL and Verilog codes of you circuit, you can import

those codes into other EDA software to compile and simulate, even download them into

FPGA and CPLD chip;

Simulation in MUX PLUS 10.2

Fig. 3. Simulation in MUX PLUS II

2.2 Sequential logic circuit design

2.2.1 Sequential logic circuit design

Sequential logic blocks in Scicos-HDL：

Table 2: Sequential logic blocks


D_trigger D_trigger,

input port 1: clock ; input port 2:D(in put port)

Dtriggers_cr Dtriggers_cr

input port 1: clock input port 2:cr

input port 3:D

JK_trigger JK_trigger

input port 1: clock ; input port 2:J;

input port 3:Kk;

JK_trigger_cr JK_trigger_cr input port 1: clock ; input port 2:cr;

input port 3:J;input port 4:K;

RS_trigger RS_trigger

input port 1: clock ;

input port 2:S;

input port 3:R.

RS_trigger_cr RS_trigger_cr

input port 1: clock ; input port 2:cr;

input port 3:s; input port 4:r

Switch left 8 bit shift left

Switch right 8 bit shift right

counter In port 1：clock input；

In port 2：CR ，‘1‘ is effective；

Out ports 1—4：From high bits to low, binary bit Red input port：

Used in the simulation

Counter auto

set-up

In port 1：clock input；

In port 2：CR ，‘1‘ is effective；

Out ports 1—4：From high bits to low, binary bit Red input port：Used in the simulation;

self-setup


allow users to add new blocks designed by themselves

2.2.2 Sequential logic circuit design

Description

This is a 4-bit binary counter with self-setup.

We use the trigger to design this circuit, all the blocks' parameters please ref. Table2.

Sequential logic blocks.

The circuit diagramThis is the circuit diagram in Scicos-HDL.

Fig. 4. the circuit diagram in Scicos-HDL

simulation

This is the simulation rezult of the design.



Fig. 6. Simulation in MUX PLUS 10.2

2.3 Ipcore blocks in circuit design

2.3.1 Ipcore blocks

IPcore blocks in Scicos-HDL:

Table 3: IPcore blocks picture name pins&function

Hamgen

decoder

Hamgen decoder


Hamdec

encoder

Hamdec encoder


reverse code reverse code

complemental code

complemental code

absolute value computing

block

absolute value computing block

decoder 74138 Decoder 74138:

Input port 1—3 is the : g1,g2 and g3 to control this block.

Input port 4—6 is the :input date pins

Parity check Parity check


priority

encoder

priority encoder :

IP core.

De multiplexer De multiplexer 2-1:

Pin 1--> control pin

pin 2--> data1 , pin 3--> data2

dynamic filter dynamic filter

Its out put is depend on its input date.

Filter Filter

pin 1-8: you can put a scale for maximum; pin 9-16: input data ;

pin 16-23: you can put a scale for minimum.

demuxBUS_3 DemuxBUS_3:

input(1—2): ‗00‘->data1input(3-10), ‗01‘->data2input(10-17),

others –>data3input(18-25).

muxBUS_2 MuxBUS_2:

input(1): ‗0‘->out(u2-u9),

‗1‘->out(u10-u17).

demuxBUS_2 DemuxBUS_2:

input(1): ‗0‘->data1(u2-u9),

‗1‘->data2(u10-u17)

muxBUS_3

muxBUS_3:

uinput(1-2): ‗00‘->out(u3-u10),

‗01‘->out(u10-u17), others –>out(u19-u25)


allow users to add new blocks designed by themselves .

2.3.2 Ipcore circuit design

Description

This is a complex circuit with encoder and decoder, in this circuit we have Hamdec

encoder,Hamgen decoder,Parity check,74138decoder and priority encoder ,all the parameters

please ref.table3.IPcore blocks in Scicos-HDL

The circuit diagram

This is the circuit diagram in Scicos-HDL.


simulation

This is the simulation rezult of the design.




3 Circuit Simulation in Scicos-HDL

3.1 Scicos-HDL simulation library

Simulation blocks and simulation interface blocks in Scicos-HDL:

Table 3: Simulation blocks and simulation interface blocks


Scicos-HDL

INput

This is the input port of Scicos-HDL，the number of the block is equal

to the one of the whole system input ports，each in-signal must

through this block, it must be in every model file.

Scicos-HDL

OUTput

This is the output port of Scicos-HDL，the number of the block is

equal to the one of the whole system output ports，each out-signal

must through this block, it must be in every model file.

Scicos-HDL clock

Scicos-HDL clock，used in sequential logic circuit

4 bit DEC-

BIN

decimal bit �� Binary bit converter 0~16

4 bit BIN-DEC Binary bit decimal bit converter 0~16

electric level

input

Scicos-HDL electric level input，

high level―1‖，low level―0‖

Scicos-HDL

numerical value

Scicos-HDL numerical value

bit converter Binary bit�� decimal bit converter -127~+127

bit converter decimal bit � Binary bit converter -127~+127

8 bit DEC-

BIN

Binary bit� decimal bit converter 0~255

8 bit

BIN-DEC

decimal bit �� Binary bit converter 0~+255

Verilog

compiler

Scicos-HDL Verilog HDL compiler

VHDL compiler

Scicos-HDL VHDL compiler

3.2 Circuit Simulation in Scicos-HDL

Scicos-HDL offer a Virtual block library to simulate the digital circuit. But users often need

more powerful simulation function. Scicos-HDL support mix-simulation with both the its

own Virtual library and the original blocks in Scicos. In the following performing, we will

show you this.

3.3 Circuit Design Case

Description

This is a dynamic filter circuit, we use Scicosh-HDL Virtual block and riginal blocks in

Scicos to simulate.

The circuit diagram

This is the circuit diagram in Scicos-HDL.


simulation

this is the simulation rezult of the design.


3.4 Rules of design

Make sure you have put the block Scicos-HDL IN as the input ports, signals are

transferred in through this block;

Make sure you have put the block Scicos-HDL OUT as the output ports, signals are

transferred out through this block;

Self-connected is not allowed in every block;

If one output port is needed to be connected with many other blocks ,use the block

LineDemux of HDL_Combinational_Lib library;

Make sure the path and name of model file are correct (ref.scicosHdl-handbook );

Make sure the directory of saving VHDL / Verilog code file is correct, empty or at

least without the same name of the model file you will compile;

Make sure no super block in the model file.

For more details, please refer to the documents in the install package.

4 Hardware Description Language Compiler in Scicos-HDL

4.1 Introduction

The compilers: VHDL Compiler and Verilog Compiler, are the vital blocks of Scicos-HDL,

their main functions are to convert circuit model in Scilab/Scicos to standard VHDL/Verilog

codes. And you can load these VHDL/Verilog codes to FPGA.

The VHDL/Verilog codes generated by compilers can be used in following EDA tools.

Synplify Pro 7.6, Quartus® II,Mux+plus II ,ISE, Modelsim, etc.

4.2 VHDL Compiler and Verilog Compiler Applications

VHDL Compiler will convert you circuit in Scicos-HDL to VHDL codes; and Verilog

Compiler will convert to Verilog codes;

In the following circuit, we will show how to start VHDL Compiler. This is a peripheral circuit

for a single Chip; it has an A/D interface, LED interface, key board interface, D/A interface,

with a flip-latch integrated, decoders and encoders, designed by Scicos-HDL . You will see the

Two Hardware Description Language generated by the two compilers.This is the circuit

diagram in Scicos-HDL.


4.2.1 How to start VHDL Compiler

Click the red Vhdl block in your model file, there will be a Scicos-HDL Compiler dialog

box, click “YES”, next doing, “NO” return.

Fig. 13. start VHDL Compiler

file *.Cos Path selection

this must be the file you saved as a .cos file.

Fig. 14. saved as a .cos file

Select a path to save the VHDL codes generated by compiler.

Successfully compiled dialog box.

Indicate that your VHDL code has been saved here.

Fig. 15. Indicate that your VHDL code has been saved

The VHDL code of this circuit

VHDL codes of MCU.COS

architecture NXU_beh of mcu is

component demuxBUS_2nxu

port(

in_1,in_2,in_3,in_4,in_5,in_6,in_7,in_8,in_9,in_10,in_11,in_12,in_13,in_14,in_15,in_16,in_

17: in std_logic;

out_1,out_2,out_3,out_4,out_5,out_6,out_7,out_8: out std_logic);

end component;

component decoder74138nxu

port(

in_1,in_2,in_3,in_4,in_5,in_6: in std_logic;

out_1,out_2,out_3,out_4,out_5,out_6,out_7,out_8: out std_logic);

end component;

component D_trigger_2_1

port(

in_1,in_2: in std_logic;

library IEEE;

use ieee.std_logic_1164.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_unsigned.ALL;

entity mcu is

port(


NXUout_35: out std_logic;

NXUout_36: out std_logic;

NXUout_37: out std_logic);

end mcu;

architecture NXU_beh of mcu is

......

VHDL codes of a sub file of MCU.COS library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

entity decoder74138 is

port( g1,g2,g3: in std_logic;

datain: in std_logic_vector(0 to 2);

y: out std_logic_vector(0 to 7));

end decoder74138;

architecture one of decoder74138 is

begin

kcpp: process(g1,g2,g3)

variable outda: std_logic_vector(0 to 7);

begin

if g1='0' then

y<="11111111";

elsif g2='1' then

y<="11111111";

elsif g3='1' then

y<="11111111";

else

case datain is

when "000" => outda:="01111111";

when "001" => outda:="10111111";

when "010" => outda:="11011111";

when "011" => outda:="11101111";

when "100" => outda:="11110111";

when "101" => outda:="11111011";

when "110" => outda:="11111101";

......

The codes above-mentioned is the VHDL and Verilog codes of you circuit, you can import

those codes into other EDA software to compile and simulate, even download them into

FPGA and CPLD chip;

Simulation in MUX PLUX 10.2


The file list of this circuit in MUX PLUS 10.2

Fig. 17. The file list of this circuit in MUX PLUS 10.2

The way to start Verilog Compiler is as the same as the way using the VHDL Compiler,

but this compiler will generate Verilog codes.

More details please ref.scicosHdl-handbook.

5 Conclusion

Thank Simone Mannori and Ramine Nikoukhah for great guidance .

We introduce a Digital System Design tool based on Scicos,Scicos-HDL which makes Scicos

has hardware design and simulation function. As open-resource software, Scicos-HDL has a

unique meaning in the filed of open-resource EDA tools. We hope it contribute to our China‘s

IC design.

At present Scicos-HDL is free. You can download Scicos-HDL vision 0.4.

Download address: https://scicoshdl.sourceforge.net/

Your suggestion is Welcome! contact us: [email protected]

References

1. Scilab, INRIA, http://www-rocq.inria.fr/scilab.

2. Fang Yu, Huang Jianwen.,―Application of Scilab/Scicos in Hardware/Software Co-design‖, Computer Engineering

Vol.28 June 2002,pp.227-229.

3. Hu BaoGang, ZhaoXing, KangMengzhen,‖Introduction to Scientific Computing Software‖, Tsinghua University Press

2003.1, pp.165-203.

4. SjoholmS,LindhL, VHDL for

designers.[M].BianJinian,XueHongxitransl.Beijing:TsinghuaUniversityPress,2000.(in Chinese).

5. Synplify Pro http://www.Synplicity.com/support.

Appendix: Springer-Author Discount

Ningxia University

Ningxia

China

Fax: +86 0951 2061003

Phone: +86 0951 2061006

Preferential orders can also be placed by sending an email to

[email protected], [email protected], [email protected]

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The Application in Digital Circuit Teaching of Scicos-HDL