1

The Bleak Future of

NAND Flash Memory

Laura M. Grupp*, John D. Davis , Steven Swanson*

*Non-volatile Systems Laboratory Department of Computer Science and Engineering University of California, San Diego

Microsoft Research

2

Flash’s Future: Bright

Reliability Performance

Cost Per Capacity

3

Performance

Cost Per Capacity

Flash’s Future: Bright Bleak

D

ecr

eas

ing

W

rite

Bu

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t

Increasing Density

Reliability

4

0

1000

2000

3000

4000

5000

6000

7000

8000

Low DensityFlash

Disk Drives

Wri

te L

ate

ncy

(µ

s)

Cost Per Capacity

D

ecr

eas

ing

W

rite

Bu

dge

t

Increasing Density

Reliability

Flash’s Future: Bright Bleak

Performance

Exp

ect

ed

Pe

rfo

rman

ce G

ap

5

0

1000

2000

3000

4000

5000

6000

7000

8000

Low DensityFlash

Disk Drives High DensityFlash

Wri

te L

ate

ncy

(µ

s)

Cost Per Capacity

D

ecr

eas

ing

W

rite

Bu

dge

t

Increasing Density

Reliability

Will the price decline be enough?

Flash’s Future: Bright Bleak

Performance

Exp

ect

ed

Pe

rfo

rman

ce G

ap

What performance & scaling trends can we expect from our SSDs?

6

Predicting Future Flash-Based SSDs

Model’s Equations

Fixed SSD Architecture Flash Chip Trends

SSD Trends

7

PCIe Link

The Constant-Die-Count SSD (SSD-CDC)

• Represents High-End (FusionIO, Virident, OCZ)

• Baseline – 96 dies

– 320 GB

– 34nm, MLC

• Assumptions – Constant die count

– Unlimited PCIe Link

– Channel Speed: 400MB/s

Flash Die 0

Flash Die 1

Flash Die 2

Flash Die 3

Flash Die 0

Flash Die 1

Flash Die 2

Flash Die 3

Channel 23

Channel 0

. . .

. . .

. . .

Controller Flash Die 0

Flash Die 1

Flash Die 2

Flash Die 3

Channel 1

. . .

8

The Metrics

• Capacity

• Latency

• Throughput

9

Increasing Density: Multi-bit Cells

SLC Single-Level Cell

(1 bit)

MLC Multi-Level Cell

(2 bits)

TLC Triple-Level Cell

(3 bits)

Floating Gate (modifies VTH)

“0”

“1”

“00”

“01”

“10”

“11” VTH

Ran

ge

VTH

Ran

ge

VTH

Ran

ge

10

0

5

10

15

20

25

30

35

40

2009 2014 2019 2024

Feat

ure

Siz

e (

nm

)

Year

ITRSTechnologyTrend Target

Time

Increasing Density: Moore’s Law

25nm-34nm

6.5nm

11

16

64

256

1024

4096

16384

020406080100

SSD

Cap

acit

y (G

B)

Feature Size (nm)

TLC-3

MLC-2

SLC-1

Capacity

43x

SSD-CDC

Best Possible by 2024

12

The Metrics

• Capacity: 43x

• Latency

• Throughput

13

Collecting Flash Latency Trends

• In-house flash testing rig • XUP Virtex-II

• Daughter board

• 10ns resolution

• Chip Collection • 45 chips

• 6 companies

• 25nm-72nm

• SLC, MLC, TLC

14

Empirical Data

0.0

1.0

2.0

3.0

832128512

Ch

ip W

rite

Lat

en

cy (

ms)

Feature Size (nm)

TLC-3

MLC-2

SLC-1

15

0.0

1.0

2.0

3.0

832128512

Ch

ip W

rite

Lat

en

cy (

ms)

Feature Size (nm)

SLC-1

MLC-2

TLC-3

Scaling Trends in Empirical Data

2x

2x

16

0.0

1.0

2.0

3.0

16 64 256 1024 4096 16384

SSD

-CD

C W

rite

Lat

en

cy (

ms)

SSD Capacity (GB)

TLC-3

MLC-2

SLC-1

Write Latency of SSD-CDC

2.6x

17

The Metrics

• Capacity: 43x

• Latency: 2.6x

• Throughput

18

0

500

1000

1500

2000

2500

3000

3500

16 64 256 1024 4096 16384

SSD

-CD

C W

rite

Ban

dw

idth

(M

B/s

)

SSD Capacity (GB)

SLC-1

MLC-2

TLC-3

Increased Page Size MLC: 4kB, TLC 8kB

0.7x

Reduced Bandwidth

19

0

200

400

600

800

1000

16 64 256 1024 4096 16384

SSD

-CD

C W

rite

kIO

Ps

SSD Capacity (GB)

SLC-1

MLC-2

TLC-3

IOPs – 512B Random Accesses

Fastest HDD: 0.2 kIOPs Our Slowest SSD: 32.0 kIOPs

0.4x

20

The Metrics

• Capacity: 43x

• Latency: 2.6x

• Throughput: 0.7x, 0.4x

21

Conclusion

• Chip Scaling: A Mixed Bag

– Improved: Density and Cost

– In Decline: Performance and Reliability

• SSDs: Not always a perfect replacement for disks

– Do Get: High Capacity & High IOPs

– Don’t Get: Low Cost & Low Latency

22

Questions?

The Bleak Future of

NAND Flash Memory

Laura M. Grupp, John D. Davis , Steven Swanson

23

The Model’s Equations

Metric Equation

Capacity CapacityBaseline×𝑩𝒊𝒕𝒔𝑷𝒆𝒓𝑪𝒆𝒍𝒍𝒑𝒓𝒐𝒋𝒆𝒄𝒕𝒆𝒅

𝑩𝒊𝒕𝒔𝑷𝒆𝒓𝑪𝒆𝒍𝒍𝒃𝒂𝒔𝒆𝒍𝒊𝒏𝒆×

𝑭𝒆𝒂𝒕𝒖𝒓𝒆𝑺𝒊𝒛𝒆𝒃𝒂𝒔𝒆𝒍𝒊𝒏𝒆

𝑭𝒆𝒂𝒕𝒖𝒓𝒆𝑺𝒊𝒛𝒆𝒑𝒓𝒐𝒋𝒆𝒄𝒕𝒆𝒅

2

Latency 𝑪𝒉𝒊𝒑𝑳𝒂𝒕𝒆𝒏𝒄𝒚 + 𝑶𝒗𝒆𝒓𝒉𝒆𝒂𝒅𝑳𝒂𝒕𝒆𝒏𝒄𝒚

Bandwidth 𝑪𝒉𝒂𝒏𝒏𝒆𝒍𝑪𝒐𝒖𝒏𝒕 ×𝒅𝒊𝒆𝒔𝑷𝒆𝒓𝑪𝒉𝒂𝒏𝒏𝒆𝒍 − 1 × 𝑷𝒂𝒈𝒆𝑺𝒊𝒛𝒆

𝑪𝒉𝒊𝒑𝑳𝒂𝒕𝒆𝒏𝒄𝒚, 𝑂𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛 ≫ 𝐵𝑢𝑠 𝑆𝑝𝑒𝑒𝑑

IOPs 𝑪𝒉𝒂𝒏𝒏𝒆𝒍𝑪𝒐𝒖𝒏𝒕 ×𝒅𝒊𝒆𝒔𝑷𝒆𝒓𝑪𝒉𝒂𝒏𝒏𝒆𝒍 − 1

𝑪𝒉𝒊𝒑𝑳𝒂𝒕𝒆𝒏𝒄𝒚, 𝑂𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛 ≫ 𝐵𝑢𝑠 𝑆𝑝𝑒𝑒𝑑

Measured Value Baseline SSD Design

Projected SSD Design Constant SSD Parameter

24

Lifetime

25

Error Rates

26

Price

27

Read Latency

28

Read Bandwidth

29

Read IOPS – 512B Random Access

30

0.0

1.0

2.0

3.0

8108208308408508

Ch

ip W

rite

Lat

en

cy (

ms)

Feature Size (nm)

SLC-1

MLC-2

TLC-3

Scaling Trends in Empirical Data

31

Increasing Density: Multi-bit Cells

SLC Single Level Cell

(1 bit)

MLC Multi-Level Cell

(2 bits)

TLC Triple-Level Cell

(3 bits)

“MLC-1”

Native Technology

Number of Stored Bits

Lower Price per Bit

Floating Gate (modifies VTH)

“0”

“1”

“0x”

“1x”

“00”

“01”

“10”

“11” VTH

Ran

ge

VTH

Ran

ge

VTH

Ran

ge

VTH

Ran

ge