The NA60 Experiment Readout Architecture M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for the NA60 Collaboration 13 th IEEE- NPSS Real Time

The NA60 Experiment Readout Architecture

M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for

the NA60 Collaboration

13th IEEE- NPSS Real Time Conference 2003,Hotel Omni Mont Royal, Montreal, Canada,

May 18 – 23 2003

May 18-23 2003 13th IEEE-NPSS Real Time Conference 2003 2

The NA60 Experiment

Fixed target experiment at CERN SPSHeavy Ion / Dimuon experiment

Open charm and prompt dimuon production

Talk Outline: Apparatus DAQ Architecture Readout Electronics Conclusions

NA60

SPS

LEP/LHC


Detector Concept and Layout

4 Detectors: Muon Spectrometer

(MWPCs, Trigger hodoscopes)

ZDC Beam Tracker Vertex Detector

Tracking MWPCs

Trigger hodoscopes

Toroidal Magnet

FewallMuon filter

ZDC and Quartz Blade

TARGET AREA

MUON SPECTROMETER~1m

MUON FILTER

BEAMTRACKER

TARGETBOX

TELESCOPE

Dipole field2.5 T

BEAM

IC


DAQ Overview

DetectorDetector DetectorDetectorDetectorDetector

LDC

GDC Castor/CDRburst

interburst

burst

events - trigger

DATEALICE

System is organized in indipendent partitions


PCI System

Many partitions A General-purpose PCI

card Many detector-specific

mezzanines


Readout Chain Overview

MEZZANINE 1

MEZZANINE 2

MEZZANINE 3

MEZZANINE 4

PCI Card

PCI Card

PCI Card

PCI Card

LDC

LDCPC

I B

US

Acquisition software(DATE)

DET.1

DET.2

DET.3

DET.4

BURST

INTERBURST


10

Hardware/Software Handshake

#0#1#2#3

10 1011 11 11

AcquisitionSoftware

00: idle10: burst11: interburst

bits 0-1: SPS statusbit 2: R/O statusbit3: timeout

timeout

At the end of the burst

HW sets bit 2

SW starts as soon as bit 2 is set and resets it at the end

If a new burst arrives while SW is still reading bit

3 is set

BURST


PCI Card Architecture

PCIinterface

application

RAM

Registers

Controllogic

mez.

PCICTRL

BURST

INTERBURST

det.

PCI Card

• FPGA

• Large memory buffer

• Mezzanine Cards

• Registers

Light blue: blocks inside FPGA


First Implementation – PCI-FLIC

Developed by EP/ED-DTb CERN Division

PCI core embedded in ORCA FPGA

Successfully used in test beams in 2001/2002 Readout architecture validated

Has some limitations Slow FPGA Maintenance problems

A new card has been developed...


Final Implementation – PCI-CFD

New and faster ALTERA FPGAExternal PCI bridge (PLX 9030)X4 bandwidth

FPGA(APEX/20K100)

PLX9030PCI bridge

PMC connectors

for mezzanine

cards

64 MBytesRAM

Will be used in next NA60 run


CFD – FPGA Application

Readout

Event Formatting

RAM Writing

PCI Interface

BURST

INTERBURST

# total words (8bit)

readout time

# total words (8bit)

# event# burst

time of arrival

data 5

data 3

data 1

data 4

data 2

data N - 2data N - 1

data N

marker word

# data words (8bit)

errors

Data

Header

Trailer

31 0


Mezzanine 1 – VME-Like & CAMAC Protocols

Very simple mezzanine Level conversion ECL/NIM => TTL Protocol itself implemented in PCI Card FPGA

BURSTWARNINGTRIGGER

BUSY

Protocol control signals & data

PCICard


Mezzanine 1 – Protocols

2 different protocols implemented on this mezzanine: RMH Protocol (Muon Spectrometer MWPCs &

Hodoscopes) Fera (CAMAC) protocol (Beam Tracker & ZDC)

trigger

start_read

encodedflagdata

end_of_read

RMH Protocol


Mezzanine 2 - Pixel Detector

Alice PILOT chip, radhard, Pixel chip configuration and readout, GOL

interfacing

ALICE1LHCb Pixel chip, radhard, 256x32 cells (425 m x 50 m)

GOL, radhard high speed serial

link (GLink)

GOL (Pix DATA)

Pixel/PILOT (JTAG Conf.)

thanks…alice


Mezzanine 2 – Mezzanine Features

Complex mezzanine Can be interfaced to 2 pixel

planes R/O implemented in local

FPGA Zero Suppression Event formatting Error detection

PCI accesses FIFOs Detector configuration


Mezzanine 2 – Pixel Conf&Test Software

Mezzanine & pixel-chip configuration (JTAG)

Settings databaseDetector & R/O

Chip test Threshold scan Noisy and dead

pixelUsed by DATE at

run startup


Conclusions

A new readout system based on the PCI bus has been developed for a HEP experiment

High performances and flexibility, low costs Roadmap:

Muon spectrometer electronics commissioned October 2001

Beam Tracker and ZDC electronics used for the first time June 2002

Pixel Telescope intermediate system working on beam June & October 2002

Final system working in lab, will be used in data taking August 2003


Acknowledgements

The authors would like to thank the following people: CERN EP/ED-DTb group and in particular Hans

Muller for their contributions and suggestions in the early stages of the project

The Alice Pixel group and in particular F.Formenti, G.Stefanini, K.Wyllie, A.Kluge and M.Burns for their constant support to the NA60 pixel project


NA60 Collaboration

50 people, 12 institutes, 7 countries

Lisbon

CERN Bern

Torino

Yerevan

Cagliari

LyonClermont

BNLRiken

Stony Brook

Palaiseau

R. Arnaldi, K. Banicz, K. Borer, J. Buytaert, J. Castor, B. Chaurand, W. Chen, B. Cheynis,C. Cicalò, A. Colla, P. Cortese, A. David, A. de Falco, N. de Marco, A. Devaux, A.

Devismes,A. Drees, L. Ducroux, H. En’yo, A. Ferretti, M. Floris, P. Force, A. Grigorian, J.Y. Grossiord,

N. Guettet, A. Guichard, H. Gulkanian, J. Heuser, M. Keil, L. Kluberg, Z. Li, C. Lourenço,J. Lozano, F. Manso, A. Masoni, A. Neves, H. Ohnishi, C. Oppedisano, G. Puddu,

E. Radermacher, P. Rosinský, E. Scomparin, J. Seixas, S. Serci, R. Shahoyan, E. Siddi, P. Sonderegger, G. Usai, H. Vardanyan and H. Wöhri

Documents

The NA60 Experiment Readout Architecture M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for the NA60 Collaboration 13 th IEEE- NPSS Real Time