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2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 1

Improved Mixed Digital-Analog Nearest-Match Circuit for Fully Parallel Associative Memories

Research Center for Nanodevices and Systems, Hiroshima University1-4-2 Kagamiyama, Higashi-Hiroshima 739-8527, Japan

Email: {kmr,kamimura,koide,hjm}@sxsys.hiroshima-u.ac.jp

Kazi Mujibur Rahman, Kazuhiro Kamimura, Tetsushi Koide and Hans Jürgen Mattausch

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HIROSHIMA UNIVERSITY

2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 2HIROSHIMA UNIVERSITY

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The Nearest Match Network

l Functional blocks in a fully parallel associative memory based search networkl Memory cells to store the word patternsl Word comparators to generate current proportional to mismatch

between stored pattern and search wordl Nearest match circuit consisting of a Winner Lineup Amplifier (WLA)

and Winner Take All (WTA) networks to decide the winnerl Output buffers to generate binary level decision

l The nearest match network is implemented using analog circuitry to reduce the complexity and space

l Nearest Match Circuit Functionalityl Sufficiently amplify the distance between the winner and the

nearest loserl Insensitive to noise in harsh environmentl Less sensitive to fabrication scattering

2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 3HIROSHIMA UNIVERSITY

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WLA Circuit With Pre-charged Capacitors in the Match Lines

l Capacitances C1, .. , CRadded to the match lines

l pMOS transistors M21, ... M2R in the match lines charges the match line capacitances to VDD when the Enable signal is Lowl The noisy inputs to the

distance amplification circuit filtered out by the match line capacitances

Pre-charge circuit

WLA-A

2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 4HIROSHIMA UNIVERSITY

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WLA Network (WLA-B) with Pre-Charge Supply of VDD-Vthreshold

l New pre-charge circuit added using MP1/MN1, .. , MPR/MNR transistors l Pre-charging pMOS

transistors M21, .. , M2Rdisconnected from VDD and connected to the new charging circuit

l New charging circuit output voltage = 2.5V (VDD=3.3V and Vthreshold=0.8V)

Pre-charge supply source circuit

Pre-charge supply lineVDD-Vthreshold

WLA-B

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2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 5HIROSHIMA UNIVERSITY

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Reset Circuit Added to the Feedback Line of WLA-B

l Pre-search input voltage of the voltage follower circuit equals to VDD

l The nMOS transistors (M41, .. , M4R) of the distance amplification circuit have zero initial gate voltages

l WLA-C circuit has same initial condition for all search configurations

Transistors MPu and MNL resets the feedback line before a search starts

WLA-C

2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 6HIROSHIMA UNIVERSITY

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Simulation Results à Search Times

Nearest Loser set at 1-bit apart of the winner and other losers set at a distance of 20-bits

100

150

200

250

300

350

0 64 128 192 256 320 384 448 512

Winner input distance (bits)

Sea

rch

tim

e (n

s)

WLA-A (Match Lines Precharged to VDD)WLA-B (Match Lines Precharged to VDD-Vth)WLA-C (Match Lines Pre-Charged to VDD-Vth and Reset Feedback Line)

Nearest Loser set at 5-bit apart of the winner and other losers set at a distance of 20-bits

100

150

200

250

300

350

0 64 128 192 256 320 384 448 512

Winner input distance (bits)

Sea

rch

tim

e (n

s)

WLA-A (Match Lines Precharged to VDD)WLA-B (Match Lines Precharged to VDD-Vth)

WLA-C (Match Lines Pre-Charged to VDD-Vth and Reset Feedback Line)

• Average search times WLA-A → 170 nsWLA-B → 137 nsWLA-C → 136 ns

Search time in WLA-B improves by 29.4% as compared to WLA-A

For larger winner input distances (above 256 bits), search time slope becomes more as the nearest loser comes very close to the winner

2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 7HIROSHIMA UNIVERSITY

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Simulation Results à Power Consumption

Nearest loser set at 1-bit apart of the winner and other losers set at a distance of 20-bits

100

120

140

160

180

0 64 128 192 256 320 384 448 512

Winner input distance (bits)

Ave

rage

pow

er (

mW

)

WLA-A (Match Lines Precharged to VDD)WLA-B (Match Lines Precharged to VDD-Vth)

WLA-C (Match Lines Pre-Charged to VDD-Vth and Reset Feedback Line)

Nearest Loser set at 10-bit apart of the winner and other losers set at a distance of 20-bits

100

120

140

160

180

0 64 128 192 256 320 384 448 512

Winner input distance (bits)

Ave

rage

pow

er (

mW

)

WLA-A (Match Lines Precharged to VDD)WLA-B (Match Lines Precharged to VDD-Vth)WLA-C (Match Lines Pre-Charged to VDD-Vth and Reset Feedback Line)

• Average power dissipation in WLA-B more than WLA-A implementation by 27-mW• WLA-C consumes more power (about 3-mW on the average) than WLA-B

• Average power consumptionWLA-A → 137 mW, WLA-B → 164 mW, WLA-C → 167 mW

2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, 30 January 2004 8HIROSHIMA UNIVERSITY

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Conclusions and Future Work

l Average search time of 137 ns achieved by introducing the new pre-charge circuit

l Average search time improves by about 33 ns (29.4%) by pre-charging the match lines to VDD-Vthreshold instead of to VDD

l For worst case search (winner input distance = 512), WLA-A has search time of 340 ns, whereas, for the same case WLA-B has a search time of 206 ns (about 40% improvement in speed)

l Introduction of the pre-charge circuit (WLA-B) increases average power consumption by about 27-mW

l Introduction of reset circuit in the feedback line improves the search speed by about 1 ns at the cost of about 3-mW more power consumption

l FUTURE WORKS

l Investigate the possibilities of further reduction in search time with relatively smaller capacitors in the match lines

l Design the test chip and evaluate the practical performance