The Serial Communication Interface (SCI)MC9S12-C32

Lecture L4.9

Reference

HCS12 Serial Communications Interface

(SCI)

Block Guide

V02.08

S12SCIV2.pdf

PIM_9C32

Block Diagram

SCI module

SCI

• Asynchronous Serial I/O

• The 68HCS12 SCI Interface

• Programming the SCI

• SCI Interface Using Interrupts

MARK

SPACESTART

STOP

PARITY

D0 D1 D2 D3 D4 D5 D6 D7

ASCII code 54H = 1010100 ("T") sent with odd parity

Common Asynchronous Serial Baud Rates

Baud rate Bit time (msec)

No. of STOP bits

Char. time (msec.)

Char./sec.

110 9.09 2 100.00 10 300 3.33 1 33.3 3 30 600 1.67 1 16.67 60

1200 0.833 1 8.33 120 2400 0.417 1 4.17 240 4800 0.208 1 2.08 480 9600 0.104 1 1.04 960

14400 0.069 1 0.69 1440 19200 0.052 1 0.52 1920 28800 0.035 1 0.35 2880 38400 0.026 1 0.26 3840

SCI

• Asynchronous Serial I/O

• The 68HCS12 SCI Interface

• Programming the SCI

• SCI Interface Using Interrupts

SCI Registers in the MC9S12-C32 Name Register Addr Description SC0BDH 00C8 SCI Baud Rate Control Register High SC0BDL 00C9 SCI Baud Rate Control Register Low SC0CR1 00CA SCI Control Register 1 SC0CR2 00CB SCI Control Register 2 SC0SR1 00CC SCI Status Register 1 SC0SR2 00CD SCI Status Register 2 SC0DRH 00CE SCI Data Register High SC0DRL 00CF SCI Data Register Low

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

Receive Data Register (RDR)

Transmit Data Register (TDR)

SCI Status Register 1 (SCxSR1)

SCI Baud Rate Control H (SCxBDH)

SCI Control Register 2 (SCxCR2)

Transmit Shift Register

Receive Shift Register

Serial Data Out

Serial Data In

TxD

RxD

SCI Control Register 1 (SCxCR1)

D8

D8

SCxDRL

PS1 (PS3)

PS0 (PS2)

SCI Status Register 2 (SCxSR2)

SCI Baud Rate Control L (SCxBDL)

SCI Data Register H (SCxDRH)

Functional diagram of the Serial Communications Interface (SCI)

7 6 5 4 3 2 1 0 $00CF

R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SC0DRL

Read: Reads the receive data buffer Write: Writes to the transmit data buffer

The SCI Data Register Low

7 6 5 4 3 2 1 0 $00CC

TDRE TC RDRF IDLE OR NF FE PF SC0SR1

TDRE: Transmit Data Register Empty Flag 0 – SCxDR busy 1 – Transmit data can be written to SCxDR

TC: Transmit Complete Flag 0 – Transmitter busy 1 – Transmitter is idle

RDRF: Receive Data Register Full Flag 0 – SCxDR empty. Cleared by SCxSR1 read with RDRF set, followed by SCxDR read 1 – SCxDR full. Received character can be read from SCxDR

IDLE: Idle Line Detected Flag 0 – RxD line is idle 1 – RxD line is active

OR: Overrun Error Flag 0 – No overrun 1 – Overrun detected

NF: Noise Error Flag 0 – Unanimous decision 1 – Noise on a valid start bit, any data bit, or the stop bit

FE: Framing Error Flag 0 – Stop bit detected 1 – Zero detected instead of a stop bit

PF: Parity Error Flag 0 – Correct parity 1 – Incorrect parity

The SCI Status Register 1

7 6 5 4 3 2 1 0 $00CA

LOOPS WOMS RSRC M WAKE ILT PE PT SC0CR1

LOOPS: SCI Loop Mode/Single Wire Mode Enable 0 – Normal operation of TxD and RxD 1 – LOOP mode or single wire mode enabled

WOMS: Wire-Or Mode for Serial Pins 0 – Pins operate in normal mode 1 – Pins declared as outputs operate in open drain fashion

RSRC: Receiver Source (LOOPS = 1) 0 – Receiver input connected to transmitter internally (not TxD pin) 1 – Receiver input connected to TxD pin (single wire mode)

M: Mode (Select Character Format) 0 – 8-bit data 1 – 9-bit data

WAKE: Wakeup by Address Mark/Idle 0 – Wakeup by IDLE line recognition 1 – Wakeup by address mark (most significant data bit set)

ILT: Idle Line Type 0 – Short idle line mode 1 – Long idle line mode

PE: Parity Enable 0 – Parity is disabled 1 – Parity is enabled

PT: Parity Type 0 – Even parity 1 – Odd parity

The SCI Control Register 1

7 6 5 4 3 2 1 0 $00CE

R8 T8 0 0 0 0 0 0 SC0DRH

R8: Receive Data Bit 8 If M bit in SCxCR1 is set, R8 stores the ninth bit of the received data

T8: Transmit Data Bit 8 If M bit in SCxCR1 is set, T8 stores the ninth bit of the transmitted data

The SCI Data Register High

7 6 5 4 3 2 1 0 $00CB

TIE TCIE RIE ILIE TE RE RWU SBK SC0CR2

TIE: Transmit Interrupt Enable 0 – TDRE interrupts disabled 1 – TDRE interrupts enabled

TCIE: Transmit Complete Interrupt Enable 0 – TC interrupts disabled 1 – TC interrupts enabled

RIE: Receiver Interrupt Enable 0 – RDRF interrupts disabled 1 – RDRF and OR interrupts enabled

ILIE: Idle-Line Interrupt Enable 0 – IDLE interrupts disabled 1 – IDLE interrupts enabled

TE: Transmitter Enable 0 – Transmitter disabled 1 – Transmitter enabled

RE: Receiver Enable 0 – Receiver disabled 1 – Receiver enabled

RWU: Receiver Wakeup Control 0 – Normal SCI Receiver 1 – Wakeup enabled and receiver interrupts inhibited

SBK: Send Break 0 – Break generator off 1 – Break codes generated as long as SBK = 1

The SCI Control Register 2

7 6 5 4 3 2 1 0 $00C8

BTST BSPL BRDL SBR12 SBR11 SBR10 SBR9 SBR8 SC0BDH

7 6 5 4 3 2 1 0 $00C9

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SC0BDL

SBR[12:0]: BR divisor; SCI Baud Rate = MCLK / (16 x BR )

The SCI Baud Rate Control Register

Table 11.3 Baud Rate SelectionDesired

SCI Baud RateBR Divisor for

MCLK = 8.0 MHz110 4545300 1667600 8331200 4172400 2084800 1049600 5214400 3519200 2638400 13

SCI

• Asynchronous Serial I/O

• The 68HCS12 SCI Interface

• Programming the SCI

• SCI Interface Using Interrupts

sci.asm

; SCI0SC0BDH EQU $C8 ;baud rate controlSC0CR1 EQU $CA ;SCI control reg 1SC0CR2 EQU $CB ;SCI control reg 2SC0SR1 EQU $CC ;SCI status regSC0DRL EQU $CF ;SCI data regRDRF EQU $20 ;SCSR mask

; INITIALIZE SCIsci0_init

CLR SC0CR1 ;8 bitLDD #52STD SC0BDH ;9600 baudLDAA #$0CSTAA SC0CR2 ;enable tx & rx

RTS

; INPUT BYTE FROM SERIAL PORT INTO AINCHAR

LDAA SC0SR1 ;check statusANDA #RDRF ;check rdrfBEQ INCHAR ;wait for charLDAA SC0DRL ;get char in ARTS

; OUTPUT BYTE IN A TO SERIAL PORTOUTPUT TST SC0SR1

BPL OUTPUT ;loop until tdreSTAA SC0DRL ;send ARTS

Communicating with a PC

loop: if key has been pressed then send character to remote computer if remote computer has sent character then display character repeat loop

Algorithm for a dumb terminal

sciecho.asm

; echo char to PC

org $4000sci_echo

bsr sci0_initse1 bsr inchar

bsr outputbra se1

#include sci.asm

SCI

• Asynchronous Serial I/O

• The 68HCS12 SCI Interface

• Programming the SCI

• SCI Interface Using Interrupts

; SCI Interface using interrupts File: SCIINT.WHP; display characters from PC keyboard on LCD display

SC0BDH EQU $C8 ;baud rate controlSC0CR1 EQU $CA ;SCI control reg 1SC0CR2 EQU $CB ;SCI control reg 2SC0SR1 EQU $CC ;SCI status regSC0DRL EQU $CF ;SCI data regRDRF EQU $20 ;SCSR maskSCI0.IVEC EQU $0FD8 ;SCI0 user vector address + 2

ORG $4000main

jsr spi_init ;initialize spijsr lcd_init ;initialize lcdjsr initq ;initialize queuejsr sci0_init ;initialize sci

mn1 jsr checkq ;if queue is emptybcs mn1 ; waitjsr data8 ;store char on LCDldy #3jsr ms_delay ;delay ~10 msbra mn1

; INITIALIZE SCIsci0_init

SEI ;disable interruptsCLR SC0CR1 ;8 bitLDD #52STD SC0BDH ;9600 baudLDAA #$2CSTAA SC0CR2 ;enable tx & rx, RX INTLDD #SCI_INTSERSTD SCI0.IVEC ;set sci int vectorCLI ;enable interrupts

RTS

; Interrupt service routine: get char and store in queue SCI_INTSER

LDAA SC0SR1ANDA #RDRFBEQ SI1 ;if RDRF setLDAA SC0DRL ;read data (clears RDRF flag)JSR QSTORE ;and store it in queue

SI1 RTI

#INCLUDE QUEUE.ASM#INCLUDE LCD.ASM