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The Verilog Hardware Description Language. GUIDELINES. How to write HDL code:. GUIDELINES. How NOT to write HDL code:. Think Hardware NOT Software. Poorly written HDL code will either be: Unsynthesizable Functionally incorrect Lead to poor performance/area/power results. Conventions. - PowerPoint PPT Presentation
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The Verilog Hardware The Verilog Hardware Description LanguageDescription Language
GUIDELINESGUIDELINES
How to write HDL code:How to write HDL code:
Q
QSET
CLR
D
Q
QSET
CLR
D
GUIDELINESGUIDELINES
How NOT to write HDL code:How NOT to write HDL code:
if a=b thenx=a^b
else if a>b then...
Think Hardware NOT Think Hardware NOT SoftwareSoftware
Poorly written HDL code will either Poorly written HDL code will either be:be:– UnsynthesizableUnsynthesizable– Functionally incorrectFunctionally incorrect– Lead to poor performance/area/power Lead to poor performance/area/power
resultsresults
ConventionsConventions
Verilog IS case sensitiveVerilog IS case sensitive– CLOCK, clock and Clock are differentCLOCK, clock and Clock are different
Syntax is based on CSyntax is based on C– but is interpreted differentlybut is interpreted differently
Verilog code basic structureVerilog code basic structure
module module module_name module_name (ports);(ports);
inputinput input_signals;input_signals;
output output output_signals;output_signals;
inout inout bidirectional signals;bidirectional signals;
wire wire wire_signals;wire_signals;
reg reg register_type_variables;register_type_variables;
primitive/component primitive/component (ports);(ports);
concurrent/sequential assignmentsconcurrent/sequential assignments
endmoduleendmodule
Port typesPort types
PORT DIRECTIONPORT DIRECTION- IN- IN
-OUT-OUT
-INOUT-INOUT
SIGNAL TYPESIGNAL TYPE– scalar ( input x; )scalar ( input x; )– Vector (input [Vector (input [WIDTH -1 WIDTH -1 : 0] x): 0] x)
Module port declaration example Module port declaration example (1/2)(1/2)
module module and_gate (o, i1, i2);and_gate (o, i1, i2);
output output o;o;
inputinput i1; i1;
inputinput i2; i2;
endmoduleendmodule
Module port declaration example Module port declaration example (2/2)(2/2)
module module adder (carry, sum, i1, i2);adder (carry, sum, i1, i2);
output output carry;carry;
output output [3:0] sum;[3:0] sum;
input input [3:0] i1, i2; [3:0] i1, i2;
endmoduleendmodule
ExampleExample
COUNTER
EN
PRESET
5
COUNT
5
CLK RST
Verilog PrimitivesVerilog Primitives
Verilog primitives are models of Verilog primitives are models of common combinational logic common combinational logic gatesgates
Their functionality is built into the Their functionality is built into the language and can be instantiated language and can be instantiated in designs directlyin designs directly
The output port of a primitive The output port of a primitive must be first in the list of portsmust be first in the list of ports
Structural description exampleStructural description example
i0i1
i2i3
o
S1
S2
module gates (o,i0,i1,i2,i3); output o; input i0,i1,i2,i3; wire s1, s2; and (s1, i0, i1); and (s2, i2, i3); and (o, s1, s2);endmodule
Verilog operatorsVerilog operators
• ArithmeticArithmetic++, - , *, , - , *, SynthesizableSynthesizable
/, %/, % Non-synthesizableNon-synthesizable• BitwiseBitwise& AND& AND| OR| OR~ NOT ~ NOT ^ XOR^ XOR~^ XNOR~^ XNOR• RelationalRelational=, <, >, <=, >==, <, >, <=, >=
User-Defined User-Defined Primitives Truth Table Primitives Truth Table
ModelsModelsprimitive primitive my_UDP (y, x1, x2, x3);my_UDP (y, x1, x2, x3); outputoutput y; y; //the output of a primitive cannot be a //the output of a primitive cannot be a
vector!!vector!! inputinput x1, x2, x3; x1, x2, x3;
tabletable //x1 x2 x3 : y//x1 x2 x3 : y 0 0 0 : 0;0 0 0 : 0; 0 0 1 : 1;0 0 1 : 1; 0 1 0 : 0;0 1 0 : 0; 0 1 1 : 0;0 1 1 : 0; 1 0 0 : 1;1 0 0 : 1; 1 0 1 : 0;1 0 1 : 0; 1 1 0 : 1;1 1 0 : 1; 1 1 1 : 0;1 1 1 : 0; endtableendtableendprimitiveendprimitive
Truth tables with don’t Truth tables with don’t carescarestabletable //? Represents a don’t care condition//? Represents a don’t care condition // on the input// on the input //i1 i2 i3 : y//i1 i2 i3 : y 0 0 0 : 00 0 0 : 0 0 0 1 : 10 0 1 : 1 0 1 0 : 00 1 0 : 0 0 1 1 : 00 1 1 : 0 1 ? ? : 11 ? ? : 1endtableendtable
variable assignmentvariable assignment
variable_name = variable_name = value; //blocking assignmentvalue; //blocking assignmentvariable_name <= variable_name <= value; //non-blocking assignmentvalue; //non-blocking assignment
ExamplesExamplesoutput a;output a;output [6:0] b;output [6:0] b;reg [3:0] c;reg [3:0] c;wire [2:0] d;wire [2:0] d;
CorrectCorrect IncorrectIncorrecta = 1;a = 1; a <= 3;a <= 3;b <= 7’b0101001;b <= 7’b0101001; b = 9’b000011011;b = 9’b000011011;b[1] = 0;b[1] = 0;c <= 0;c <= 0; d <= 0;d <= 0;d <= {b , c};d <= {b , c};b <= {c, d};b <= {c, d};b[5:2] <= c;b[5:2] <= c;
Propagation delayPropagation delay
Used to assign variables or primitives with Used to assign variables or primitives with delay, modeling circuit behaviourdelay, modeling circuit behaviour
# 5 and (s, i0, i1); -- 5 ns and gate delay-- 5 ns and gate delay #5 assign s = i0 & i1; -- 5 ns and gate delay#5 assign s = i0 & i1; -- 5 ns and gate delay #1 assign a = b;#1 assign a = b; --1 ns wire delay--1 ns wire delayNot synthesizableNot synthesizable, is ignored by synthesis , is ignored by synthesis
toolstoolsUseful in testbenches for creating input signal Useful in testbenches for creating input signal
waveformswaveforms always #20 clk = ~clk -- 40 ns clock periodalways #20 clk = ~clk -- 40 ns clock period #0 rst_n = 0;#0 rst_n = 0; #10 rst_n = 1;#10 rst_n = 1;
Concurrent statements Concurrent statements –delta time–delta time
b = ~ a;b = ~ a; (a = 1, b = 1, c =0)(a = 1, b = 1, c =0)
c = a ^ b;c = a ^ b;
TimeTime aa bb cc
00 11 11 00
δδ 11 00 00
22δδ 1 0 1 1 0 1
Continuous Continuous assignmentassignment Multiple driver errorMultiple driver error
assign c = a & b;assign c = a & b;
……..
assign c = d | e;assign c = d | e;
ab
de
c
Combinational circuit Combinational circuit descriptiondescription
modulemodule gates (d, a, c); gates (d, a, c);
outputoutput d; d;
inputinput a, c; a, c;
////regreg b; b;
assignassign d = c ^ (~a); d = c ^ (~a);
// // assignassign b = ~a; b = ~a;
// // assignassign d = c ^ b; d = c ^ b;
endmoduleendmodule
ab
c
d
Arithmetic unit Arithmetic unit descriptiondescription(full-adder)(full-adder)
modulemodule add1 (cout, sum, a, b, cin); add1 (cout, sum, a, b, cin); inputinput a, b; a, b; inputinput cin; cin; outputoutput sum; sum; outputoutput cout; cout;
assignassign {cout,sum} = a + b + cin; {cout,sum} = a + b + cin;endmoduleendmodule
ExampleExample
Describe a 5-bit multiplier in Describe a 5-bit multiplier in VerilogVerilog..
Conditional assignment - Conditional assignment - describing MUXsdescribing MUXs
assign assign = select_signal ? assignment1 : = select_signal ? assignment1 : assignment1assignment1
module module mux (o, s, i0, i1);mux (o, s, i0, i1); output output o; o; input input i0, i1;i0, i1; input input s;s;
assign assign o = s ? i1 : i0; o = s ? i1 : i0; //if s =1 then o = i1, else o =i0//if s =1 then o = i1, else o =i0endmoduleendmodule
Cyclic behaviorCyclic behavior
• Statements in cyclic behavior execute Statements in cyclic behavior execute sequentiallysequentially
• Can be used to describe either Can be used to describe either combinational circuits (optional) or combinational circuits (optional) or sequential circuits (only way)sequential circuits (only way)
always & (always & (sensitivity listsensitivity list))
beginbegin
sequential statementssequential statements
endend
Combinational Circuit Combinational Circuit Description using Cyclic Description using Cyclic
BehaviorBehavior
always @ always @ (a or b or c)(a or b or c)beginbegin d = (a &d = (a & b) |b) | c;c;endend
ALL input signals must be in ALL input signals must be in sensitivity list or latches will sensitivity list or latches will be produced!be produced!
If statement If statement (sequential)– (sequential)–
describing MUXsdescribing MUXsif (if (condition1) begincondition1) begin signal1signal1 <= value1; <= value1; signal2 <= signal2 <= value2;value2; endendelse if (else if (condition2) condition2)
beginbegin signal1signal1 <= value3; <= value3; signal2 <= signal2 <= value4;value4; end end … … elseelse beginbegin signal1signal1 <= valuen-1; <= valuen-1; signal2 <= signal2 <= valuen;valuen; endend
module module mux (o, s, i0, i1);mux (o, s, i0, i1); output output o; o; reg o;reg o; input input i0, i1;i0, i1; input input s;s;
always @ (i0 or i1 or s)always @ (i0 or i1 or s) beginbegin if (s == 0)if (s == 0) o = i0;o = i0; elseelse o = i1;o = i1; endendendmoduleendmodule
CASE statement CASE statement (sequential)– describing (sequential)– describing
MUXsMUXscase case (signal)(signal) value1:value1: signal1 <= signal1 <= value2;value2; signal2 <= signal2 <= value3;value3; value2 :value2 : signal1 <= signal1 <= value4;value4; signal2 <= signal2 <= value5;value5; . . . . . . default:default: signal1signal1 <= valuen-1; <= valuen-1; signal2 <= signal2 <= valuen;valuen;endcaseendcase
module module mux (o, s, i0, i1);mux (o, s, i0, i1); output output o; o; reg o;reg o; input input i0, i1;i0, i1; input input s;s;
always @ always @ (i0 or i1 or s)(i0 or i1 or s) beginbegin case case (s)(s) 0: o = i0;0: o = i0; 1: o = i1;1: o = i1; default: o= 1’bx;default: o= 1’bx; endcaseendcase endendendmoduleendmodule
ExampleExample
Describe a 3-bit 4-to-1 MUXDescribe a 3-bit 4-to-1 MUX
CLOCKED PROCESSCLOCKED PROCESS(Latch with asynchronous (Latch with asynchronous
reset)reset)always @ (clk or rst_n)always @ (clk or rst_n)
beginbegin
if (rst_n == 0)if (rst_n == 0)
q <= 0;q <= 0;
else if (clk == 1)else if (clk == 1)
q <= d;q <= d;
endend
CLOCKED PROCESSCLOCKED PROCESS(Latch(Latch with synchronous with synchronous
reset)reset)always @ (clk or rst_n)always @ (clk or rst_n)
beginbegin
if (clk == 1)if (clk == 1)
q <= d;q <= d;
else if (rst_n == 0)else if (rst_n == 0)
q <= 0;q <= 0;
endend
CLOCKED PROCESSCLOCKED PROCESS(Flip-flop with asynchronous (Flip-flop with asynchronous
reset)reset)always @(posedge clk or negedge rst_n)always @(posedge clk or negedge rst_n)
beginbegin
if (rst_n == 0)if (rst_n == 0)
q <= 0;q <= 0;
elseelse
q <= d;q <= d;
endend
CLOCKED PROCESSCLOCKED PROCESS(Flip-flop with synchronous (Flip-flop with synchronous
reset)reset)always @(posedge clk)always @(posedge clk)
beginbegin
if (rst_n == 0)if (rst_n == 0)
q <= 0;q <= 0;
elseelse
q <= d;q <= d;
endend
for loop statement – shift for loop statement – shift registerregister
module shift_reg (o, clk, rst_n, i);output o;input i;input clk, rst_n;reg [3:0] d;integer k;
always @ (posedge clk or negedge rst_n) begin if (rst_n ==0) d <= 0; else begin d[0] <= i; for (k=0; k <2; k=k+1) d[k+1] <= d[k]; end endassign o = d[3];endmodule
CLOCKED VS CLOCKED VS COMBINATIONAL PROCESS COMBINATIONAL PROCESS
(1/2)(1/2)
MUX2X1
a
b
c
q
always @ always @ (a or b or c)(a or b or c) beginbegin case case (c)(c) 0: q = a;0: q = a; 1: q = b;1: q = b; default: q= 1’bx;default: q= 1’bx; endcaseendcase endend
always @ always @ (posedge clk or negedge (posedge clk or negedge rst_n)rst_n) beginbegin if (rst_n == 0) if (rst_n == 0) q <= 0;q <= 0; elseelse case case (c)(c) 0: q = a;0: q = a; 1: q = b;1: q = b; default: q= 1’bx;default: q= 1’bx; endcaseendcase endend
MUX2X1
a
b
c
q
Q
QSET
CLR
D
clk
rst
CLOCKED VS CLOCKED VS COMBINATIONAL PROCESS COMBINATIONAL PROCESS
(2/2)(2/2)always @ always @ (a or b or c)(a or b or c)
beginbegin
d = (a d = (a & & b) b) | | c;c;
endenda
b
c
d
always @ always @ (posedge clk)(posedge clk)beginbegin if (rst_n == 0)if (rst_n == 0) d <= 0;d <= 0; elseelse d <= (a d <= (a & & b) b) | | c;c;endend
a
b
c
d
Q
QSET
CLR
D
clk
rst
EXAMPLEEXAMPLE
DESCIBE A BINARY UP/DOWN DESCIBE A BINARY UP/DOWN COUNTER WITH ENABLE THAT COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZEROSTARTS AGAIN FROM ZERO
TESTBENCHTESTBENCH`timescale 1ns / 100ps`timescale 1ns / 100ps
module module testbench_name ();testbench_name (); reg ….; reg ….; //declaration of register variables for DUT inputs//declaration of register variables for DUT inputs wire …;wire …; //declaration of wires for DUT outputs //declaration of wires for DUT outputs
DUT_name(DUT ports);DUT_name(DUT ports);
initial $monitor(); initial $monitor(); //signals to be monitored (optional)//signals to be monitored (optional)initial begininitial begin #100 $finish; //end simulation#100 $finish; //end simulationendend
initial initial begin begin clk = 1’b0; //initialize clkclk = 1’b0; //initialize clk #10 a = 0;#10 a = 0; #10 a = 1;#10 a = 1; … … endend
always # 50 clk = ~clk; //50 ns clk period (if there is a clock)always # 50 clk = ~clk; //50 ns clk period (if there is a clock) endmoduleendmodule
TESTBENCH EXAMPLETESTBENCH EXAMPLE
`timescale 1ns / 100ps`timescale 1ns / 100ps modulemodule mux_tb (); mux_tb (); reg reg i0, i1, s;i0, i1, s; wire wire o;o; mux M1 (o, s, i0, i1);mux M1 (o, s, i0, i1);
initial begininitial begin #100 $finish; #100 $finish;
//end simulation//end simulation endend
initial begin initial begin //stimulus pattern//stimulus pattern #10 i0 = 0; i1=0; s=0; #10 i0=1; #10 i0 = 0; i1=1; #10 i0=1; #10 i0=0; i1= 0; s=1; #10 i0=1; #10 i0 = 0; i1=1; #10 i0=1; endendmodule
FINITE STATE FINITE STATE MACHINESMACHINES
FINITE STATE MACHINE FINITE STATE MACHINE IMPLEMENTATIONIMPLEMENTATION
COMBINATIONAL LOGIC
Q
QSET
CLR
D
Q
QSET
CLR
D
...
STATE MEMORY
OUTPUT LOGIC
CLK
INPUTS
PREVIOUS STATE
NEXT STATE
OUTPUTS
(MEALY ONLY)
Mealy machines (1/5)Mealy machines (1/5)
module fsm (y, clk, rst_n, x);
output y;
input clk, rst_n, x;
reg [1:0] state_pr, state_nx;
reg y;
parameter a = 0,
b = 1,
c = 2,
d = 3,
dont_care_state = 2’bx,
dont_care_out = 1’bx;
Mealy machines (2/5)Mealy machines (2/5)
always @ (posedge clk or negedge rst_n) always @ (posedge clk or negedge rst_n) //state memory//state memory
beginbegin if (rst_n == 0)if (rst_n == 0) state_pr <= a; //default statestate_pr <= a; //default state elseelse state_pr <= state_nx;state_pr <= state_nx; endend
Mealy machines (3/5)Mealy machines (3/5)
always @ (x or state_pr) //combinational partalways @ (x or state_pr) //combinational partbeginbegin CASE (state_pr)CASE (state_pr) a: if (x == 1) begina: if (x == 1) begin state_nx = b;state_nx = b; y=0;y=0; endend else if (x == 0) begin else if (x == 0) begin state_nx <= a; --optionalstate_nx <= a; --optional y=0;y=0; endend
Mealy machines (4/5)Mealy machines (4/5)
b: if (x == 1) beginb: if (x == 1) begin state_nx = c;state_nx = c; y=0; --Mealy machiney=0; --Mealy machine endend else if (x==0) beginelse if (x==0) begin state_nx <= a; state_nx <= a; y=0; --Mealy machiney=0; --Mealy machine endend c: if (x == 1) beginc: if (x == 1) begin state_nx = c; --optionalstate_nx = c; --optional y=0; --Mealy machiney=0; --Mealy machine endend else if (x==0) beginelse if (x==0) begin state_nx <= d; state_nx <= d; y=0; --Mealy machiney=0; --Mealy machine endend
Mealy machines (5/5)Mealy machines (5/5)
d: if (x == 1) begind: if (x == 1) begin state_nx = b;state_nx = b; y=1; --Mealy machiney=1; --Mealy machine endend else if (x==0) beginelse if (x==0) begin state_nx <= a; state_nx <= a; y=0; --Mealy machiney=0; --Mealy machine endend
default: begin default: begin state_nx = dont_care_state;state_nx = dont_care_state; y <= dont_care_out;y <= dont_care_out; endend endcaseendcaseendendendmoduleendmodule
Moore machinesMoore machines
always @ (x or state_pr) --combinational partalways @ (x or state_pr) --combinational partbeginbegin CASE (state_pr)CASE (state_pr) s0: y = <value>; --Moore machines0: y = <value>; --Moore machine if (x == 1)if (x == 1) state_nx = s1;state_nx = s1; elseelse state_nx = s0; --optionalstate_nx = s0; --optional
MOORE MACHINESMOORE MACHINES
S1: y = <value>; --Moore machineS1: y = <value>; --Moore machine
if (x == 1)if (x == 1)
state_nx = S0;state_nx = S0;
elseelse
state_nx = S1; --optionalstate_nx = S1; --optional
endcaseendcase
endend
EXAMPLE: OUT-OF-EXAMPLE: OUT-OF-SEQUENCE COUNTERSEQUENCE COUNTER DESCRIBE A COUNTER WITH THE DESCRIBE A COUNTER WITH THE
FOLLOWING SEQUENCE:FOLLOWING SEQUENCE:– ““000” => “010” => “011” => 000” => “010” => “011” =>
“001” => “111” => “000”“001” => “111” => “000”
ROM description (1/2)ROM description (1/2)
module rominfr (data, en, addr);
output [3:0] data;
input en;
input [4:0] addr;
reg [3:0] ROM [31:0];
assign data = ROM[addr];
ROM description (2/2)ROM description (2/2)initial begin ROM[0] = 4’b0001; ROM[1] = 4’b0010; ROM[2] = 4’b0011; ROM[3] = 4’b0100; ROM[4] = 4’b0101; ROM[5] = 4’b0110; ROM[6] = 4’b0111; ROM[7] = 4’b1000; ROM[8] = 4’b1001; ROM[9] = 4’b1010; ROM[10] = 4’b1011; ROM[11] = 4’b1100; ROM[12] = 4’b1101; ROM[13] = 4’b1110; ROM[14] = 4’b1111; ROM[15] = 4’b0001; ROM[16] = 4’b0010; ROM[17] = 4’b0011; ROM[18] = 4’b0100; ROM[19] = 4’b0101; ROM[20] = 4’b0110; ROM[21] = 4’b0111; ROM[22] = 4’b1000; ROM[23] = 4’b1001; ROM[24] = 4’b1010; ROM[25] = 4’b1011; ROM[26] = 4’b1100; ROM[27] = 4’b1101; ROM[28] = 4’b1110; ROM[29] = 4’b1111; ROM[30] = 4’b0000; ROM[31] = 4’b0001;endendmodule
DUAL –PORT RAM (1/2)DUAL –PORT RAM (1/2)
module v_rams_12 (clk1, clk2, we, add1, add2, di, do1, do2);
input clk1; input clk2; input we; input [5:0] add1; input [5:0] add2; input [15:0] di; output [15:0] do1; output [15:0] do2; reg [15:0] ram [63:0]; reg [5:0] read_add1; reg [5:0] read_add2;
DUAL –PORT RAM (2/2)DUAL –PORT RAM (2/2)
always @(posedge clk1) begin if (we) ram[add1] <= di; read_add1 <= add1; end assign do1 = ram[read_add1]; always @(posedge clk2) begin read_add2 <= add2; end assign do2 = ram[read_add2];endmodule
Include filesInclude files
`include "timing.vh"`include "timing.vh"module counter1(count, reset, clk) ;module counter1(count, reset, clk) ; output [output [77:0] count;:0] count; input reset, clk;input reset, clk; reg [reg [77:0] count;:0] count; always @(posedge clk or posedge reset)always @(posedge clk or posedge reset) if(reset)if(reset) count <= #(`REG_DELAY)count <= #(`REG_DELAY) 8 8'b0;'b0; elseelse count <= #(`REG_DELAY) count + count <= #(`REG_DELAY) count + 88 'b1; 'b1;. . .. . . //contents of ”timing.vh” file//contents of ”timing.vh” file
`timescale Ins/Ins`timescale Ins/Ins`define REG_DELAY 1`define REG_DELAY 1
Parametric modelsParametric models
`include “rominfr_pkg.vh”module rominfr (data, en, addr); output [`wordlength-1:0] data; input en; input [`addr_size-1:0] addr; reg [`wordlength-1:0] ROM [`ROM_size-1:0];. . .
//contents of “rominfr_pkg.vh”`define`define wordlength 8`define`define addr_size 5`define`define ROM_size 32
ExampleExample
Create an ALU with parametric wordlength, Create an ALU with parametric wordlength, and the following function tableand the following function table
S2S2 S1S1 S0S0 FUNCTIONFUNCTION 00 00 00 A + BA + B 00 00 11 A – BA – B 00 11 00 A + 1A + 1 00 11 11 B + 1B + 1 11 00 00 A AND BA AND B 11 00 11 A OR BA OR B 11 11 00 A XOR BA XOR B 11 11 11 NOT ANOT A
Blocking vs Non-Blocking vs Non-Blocking AssignmentsBlocking Assignments Blocking (=) and non-blocking Blocking (=) and non-blocking
(<=) assignments appear in (<=) assignments appear in sequential (procedural) code only. sequential (procedural) code only.
Both are not allowed in the same Both are not allowed in the same blockblock
The assign statement in non-The assign statement in non-procedural code is non-blockingprocedural code is non-blocking
Blocking VS Non-Blocking VS Non-blocking in Simulationblocking in Simulation
module block();module block();reg a, b, c; // Blocking assignments reg a, b, c; // Blocking assignments initial begininitial begin
a = #10 1'b1;// assign 1 to a at time 10a = #10 1'b1;// assign 1 to a at time 10b = #20 1'b0;// assign 0 to b at time 30 b = #20 1'b0;// assign 0 to b at time 30 c = #40 1'b1;// assign 1 to c at time 70 c = #40 1'b1;// assign 1 to c at time 70
endendendmoduleendmodule
module nonblock(); // Nonblocking assignmentsmodule nonblock(); // Nonblocking assignmentsreg a, b, c; // non-blocking assignments initial beginreg a, b, c; // non-blocking assignments initial begininitial begininitial begin
a <= #10 1'b1;//assign 1 to a at time 10a <= #10 1'b1;//assign 1 to a at time 10b <= #20 1'b0;//assign 0 to b at time 20b <= #20 1'b0;//assign 0 to b at time 20c <= #40 1'b1;//assign 1 to c at time 40c <= #40 1'b1;//assign 1 to c at time 40
end end endmodule endmodule
Blocking VS non-Blocking VS non-blocking in Hardwareblocking in Hardware Non-blocking assignments are Non-blocking assignments are
closer to hardware behavior and closer to hardware behavior and should be preferred when should be preferred when describing flip-flops and registers.describing flip-flops and registers.
ExampleExample
Design an 8-bit shift register. Use Design an 8-bit shift register. Use first blocking and then non-first blocking and then non-blocking assignments for the flip-blocking assignments for the flip-flops. Synthesize your flops. Synthesize your descriptions. Which type of descriptions. Which type of assignment corresponds to assignment corresponds to correct hardware?correct hardware?
Tasks and FunctionsTasks and Functions
A task begins with keyword task A task begins with keyword task and ends with keyword endtask and ends with keyword endtask
Inputs and outputs are declared Inputs and outputs are declared after the keyword task. after the keyword task.
Local variables are declared after Local variables are declared after input and output declaration. input and output declaration.
Coding tasks separately allows Coding tasks separately allows them to be called from several them to be called from several modulesmodules
Task exampleTask example
module FP_task();module FP_task();task conv2FP;task conv2FP;input [15:0] binary;input [15:0] binary;output [31:0] fp;output [31:0] fp;reg sign;reg sign;reg [7:0] exponent;reg [7:0] exponent;reg [22:0] significand;reg [22:0] significand;integer i;integer i;integer dp;integer dp;integer flag;integer flag;
beginbeginflag=0;flag=0;
for (i=15; i>-1; i=i-1) beginfor (i=15; i>-1; i=i-1) begin if (binary[i]== 1 && flag==0) beginif (binary[i]== 1 && flag==0) begin dp=i;dp=i;
flag=1;flag=1; endend elseelse
significand[i]=binary[i];significand[i]=binary[i]; endend
exponent=127+15-dp;exponent=127+15-dp;significand[8:0]=0; significand[8:0]=0; sign=0;sign=0;
fp={sign,exponent,significand};fp={sign,exponent,significand};
endendendtaskendtask endmoduleendmodule
Calling a TaskCalling a Task
module FP_task_tb ();module FP_task_tb ();
FP_task UUT ();FP_task UUT (); wire [15:0] number;wire [15:0] number;reg [31:0] fp_out;reg [31:0] fp_out;assign number=9;assign number=9;always @ (number)always @ (number)
conv2FP (number, fp_out);conv2FP (number, fp_out);
endmoduleendmodule
FunctionsFunctions
Very similar to tasksVery similar to tasks Can only have one outputCan only have one output Can call other functions but not tasksCan call other functions but not tasks Timing delays are not allowed in Timing delays are not allowed in
functionsfunctions A function begins with keyword A function begins with keyword functionfunction
and ends with keyword and ends with keyword endfunctionendfunction inputsinputs are declared after the keyword are declared after the keyword
function. function. They can be called with an assignmentThey can be called with an assignment
Common Verilog Common Verilog PitfallsPitfalls
Name inconsistencyName inconsistency
Compile: errorCompile: error Severity: TrivialSeverity: Trivial
modulemodule wrong_name (o, i0, i1, i2); wrong_name (o, i0, i1, i2);
outputoutput o; o;
inputinput i1, i2, i3; i1, i2, i3;
assignassign o = i0 & i1 ^ i2; o = i0 & i1 ^ i2;
endmoduleendmodule
Multiple unconditional Multiple unconditional concurrent concurrent assignmentsassignments Simulation: ‘X’ valueSimulation: ‘X’ value
Synthesis: ERROR: signal is multiply drivenSynthesis: ERROR: signal is multiply driven Severity: SeriousSeverity: Serious
module …
assign x = a & b;
...
assign x = b ^ c;
always @ (b or c)
begin
x <= b | c;
end
Incomplete sensitivity Incomplete sensitivity list list
Simulation: Unexpected behaviorSimulation: Unexpected behavior Synthesis: Warning: Incomplete sensitivity listSynthesis: Warning: Incomplete sensitivity list Severity: SeriousSeverity: Serious Solution: complete sensitivity listSolution: complete sensitivity list
always @ always @ (a or b)(a or b)
beginbegin
d <= (a &d <= (a & b) |b) | c; //c is missing from sensitivity list!!!c; //c is missing from sensitivity list!!!
endend
Not assigning all outputs Not assigning all outputs in combinational always in combinational always blockblock Simulation: Simulation: Synthesis: Warning: Signal not always assigned, Synthesis: Warning: Signal not always assigned,
storage may be neededstorage may be needed Severity: SeriousSeverity: Serious Solution: assign all signalsSolution: assign all signals
always @ always @ (a or b or c)(a or b or c)beginbegin if (c == 0) thenif (c == 0) then d <= (a d <= (a & & b) |b) | c; //d assigned only first time, c; //d assigned only first time, else if (c == 1) else if (c == 1) e <= a; //e assigned only second e <= a; //e assigned only second
time!!! time!!! endend
Unassigned signalsUnassigned signals Simulation: Undefined value (‘U’)Simulation: Undefined value (‘U’) Synthesis: Warning: Signal is Synthesis: Warning: Signal is
never used/never assigned a valuenever used/never assigned a value Severity: ModerateSeverity: Moderatemodule …
output y;
input input1, input2;
reg s;
assign y = input1 & input2; //s never assigned
endmodule
Output not assigned or Output not assigned or not connectednot connected Simulation: UndefinedSimulation: Undefined Synthesis: Error: All logic Synthesis: Error: All logic
removed from the designremoved from the design Severity: SeriousSeverity: Seriousmodule my_module (o, input1, input2); output o; input input1, input2; reg s; assign s = input1 & input2; //output never assignedendmodule
Using sequential Using sequential instead of concurrent instead of concurrent processprocess Simulation: Unexpectedly delayed Simulation: Unexpectedly delayed
signalssignals Synthesis: More FFs than Synthesis: More FFs than
expectedexpected
