The Xilinx UltraScale Architecture · I/OPins 832 1,456 ⇓ ... . TheXilinx UltraScale Architecture Stephanie Rupprich Additional

The XilinxUltraScaleArchitecture

StephanieRupprich

FPGA Basics

FPGAGenerationsand ExamplesXilinx Virtex-7

Altera Stratix 10

The XilinxUltraScaleArchitectureFoundation forSuccess

Market Requirements

Device Portfolio

Features

Applications

Evaluation

Summary andConclusion

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The Xilinx UltraScale Architecture

Stephanie Rupprich

Heidelberg University, Ruperto Carola

9th July, 2014


StephanieRupprich

FPGA Basics


Altera Stratix 10


Market Requirements

Device Portfolio

Features

Applications

Evaluation


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Agenda

1 FPGA Basics

2 FPGA Generations and ExamplesXilinx Virtex-7Altera Stratix 10

3 The Xilinx UltraScale ArchitectureFoundation for SuccessMarket RequirementsDevice PortfolioFeaturesApplications

4 Evaluation

5 Summary and Conclusion


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FPGA

• Field-Programmable Gate Array• General-purpose semiconductor

device• Programmed after

manufacturing• Opposite: ASIC, ASSP, etc.

− Application-specific− predefined HW function Figure 1 : Nexys 3 Spartan-6

FPGA Board [1]

• Applications: Audio, Security, Video/Imaging• Markets: Automotive, Aerospace/Defense, Broadcast,

Consumer Electronics, Medical, Wireless/WiredCommunication

[2–4]


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FPGA Architecture

Figure 2 : FPGA Structure [5]

Building Blocks• CLBs/LEs• I/O• Interconnect• Special Functions:

− Memory− DSP− Serial

Transceivers− Clocking

+ ConfigurationMemory

[2–4, 6–11]


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FPGA Building Blocks

Figure 3 : Spartan-6 FPGA Architecture [12]

[2–4, 6–11] Figure 4 : Functionality of a SerDes [13]


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FPGA Generations

Figure 5 : FPGA Generations [14–22]

• Low-Cost: Spartan/Artix, Cyclone• Mid-Range: Kintex, Arria• High-End: Virtex, Stratix

[14, 16–18, 22–34]


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Example 1: Xilinx Virtex-7Architecture

Figure 6 : Comparison of Standard and HKMG Transistors [35]

• 28nm HKMG HPL process technology• Unified architecture in whole 7 series:

− AMBA AXI interconnect standard− ASMBL architecture

[26, 32, 33, 35–43]Figure 7 : The ASMBLArchitecture [40]


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Example 1: Xilinx Virtex-7Performance and Power

• 2x systemperformance or50% lower power:up to 600MHz orless than 2W

• 1.8x DSPperformance: up to5, 335GMAC/s, upto 3, 600 DSP Slices Figure 8 : Performance and Power Consumption

Compared to Last-Generation Devices [26]

• 1.6x I/O bandwidth: up to 2, 784Gb/s, up to 96high-speed serial transceivers

• 2x memory bandwidth: 1, 866Mb/s (DDR3)• 2x density: almost 2 million logic cells

[26, 36–38]


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Example 2: Altera’s Stratix 10 FPGAArchitecture

Figure 9 : Effective Channel Widths of Planar and TriGate Transistor Structures[14, 44]

• Intel 14-nm TriGate process technology• HyperFlex architecture• Heterogeneous 3D solutions possible

[18, 44–50]


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Example 2: Altera’s Stratix 10 FPGAPerformance and Power

• 2x core performance(> 1GHz) or up to 70% lesspower

Figure 10 : Stratix 10 Performance [46]

• DSP performance:> 10TFLOP/s at 100GFLOPs/W

• 4x transceiverbandwidth (up to8, 064Gb/s, up to 144transceivers)

• Memory bandwidth:e.g. DDR4 at3, 200MB/s

• Largest monolithicFPGA: > 4 millionlogic elements

[18, 44–49]


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The 7 Series as "Foundation for Success"

Silicon ProcessTechnology

• partnershipwith TSMC

Generations:1 28nm HPL2 20nm 20SoC

planar3 16nm FinFET

Stacked SiliconInterconnect(SSI) Technology

• 3D ICs

Generations:1 7 series2 UltraScale

Vivado DesignSuite

• better designplacementand routing

• improvedsoftwareruntime

• co-optimiza-tion withdevices

[37, 51–55]


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Market RequirementsResulting from the "More is Better Mindset"

Figure 11 : High-Performance Systems Require Massive Bandwidth [52, p. 9]

[52]


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Device Portfolio

Maximum Capability Kintex UltraScale Virtex UltraScaleIntroduction 2013Shipment 2014Process Technology 20nm planar 20nm planar,

16nm FinFETLogic Cells 1, 160K 4, 407KBlock RAM 76Mb 115MbDSP48 Slices 5, 520 2, 880Peak DSP Performance 8, 180GMAC/s 4, 268GMAC/sTransceivers 64 104Peak Transceiver Speed 13.6Gb/s 32.75Gb/sPeak Serial Bandwidth 2, 086Gb/s 5, 101Gb/sPCIe Blocks 6 6100G Ethernet Blocks 2 7150G Interlaken Blocks 1 9Memory Interface 2, 400Mb/sI/O Pins 832 1, 456

⇓ ⇓Specialization Signal Processing Processing, Bandwidth,

Throughput

[38, 51, 53, 56–58]


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Features: Scalability

Across the Platform• 7 series: same lowest-level building blocks in different

FPGA families• UltraScale: additional package footprint capability across

Virtex and Kintex familiesFrom 20nm Planar to 16nm FinFET

Figure 12 : Scalability within the Xilinx FPGA Portfolio [59]

[30, 51]


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Features: Data Flow and Routing

Figure 13 : The Effect of Fast Tracks on Routing: More Interconnect Tracks [54]

⇒ over 90% utilization

[30, 51, 53, 54]


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Features: Fast, Smart Processing

I/O Bandwidth• high-speed serial

transceiver (GTY, GTH)• internal gearbox logic

Memory Bandwidth• SDRAM: more

controllers, wider andfaster ports

• hardened SDRAM PHYblocks

• BRAM and FIFOimprovements

DSP Processing• 27x18-bit multipliers• non-DSP computations

possiblePacket Processing

• modified DSP slices• hardened Gigabit

Ethernet MACs andInterlaken chip-to-chipinterfaces

[30, 51, 53, 54, 60–67]


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Other Features

Figure 14 : Other Features of the UltraScale Architecture

[30, 51, 53, 54, 68–70]


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Applications

Figure 15 : Example Application of the UltraScale Architecture in Digital VideoProcessing [54, p. 15]

[30, 54, 71, 72]


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EvaluationXilinx Devices

Maximum Capability Virtex-7 Kintex UltraScale Virtex UltraScaleIntrod./Shipm. 2010/2011 2013/2014Process Technology 28nm planar 20nm planar 20nm planar,

16nm FinFETLogic Cells 1, 955K 1, 160K 4, 407KBlock RAM 68Mb 76Mb 115MbDSP Slices 3, 600 5, 520 2, 880Peak DSPPerformance

5, 335GMAC/s1 8, 180GMAC/s1 4, 268GMAC/s1

Transceivers 96 64 104Peak TransceiverSpeed

28.05Gb/s 13.6Gb/s 32.75Gb/s

Peak TransceiverBandwidth

2, 784Gb/s3 2, 086Gb/s3 5, 101Gb/s3

PCIe Blocks4 1 6 6100G Ethernet 0 2 7150G Interlaken 0 1 9Memory Interface5 1, 866Mb/s 2, 400Mb/sI/O Pins 1, 200 832 1, 456Specialization Overall Performance Signal Processing Overall Performance

[26, 36–38, 51, 53, 56–58]

1based on symmetrical filter implementation2single-precision, hardened floating point DSP performance3Full Duplex4x8 Gen35Virtex-7: DDR3, UltraScale: DDR4


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EvaluationCurrent Generation Devices

Maximum Capability Kintex UltraScale Virtex UltraScale Stratix10Introd./Shipm. 2013/2014 2013/?Process Technology 20nm planar 20nm planar,

16nm FinFET14nm TriGate

Logic Cells 1, 160K 4, 407K > 4, 000KBlock RAM 76Mb 115MbDSP Slices 5, 520 2, 880DSP Performance 8, 180GMAC/s1 4, 268GMAC/s1 > 10, 000GFLOP/s2Transceivers 64 104 144Transceiver Speed 13.6Gb/s 32.75Gb/s 56Gb/sTransceiverBandwidth

2, 086Gb/s3 5, 101Gb/s3 8, 064Gb/s

PCIe Blocks4 6 6100G Ethernet 2 7150G Interlaken 1 9Memory Interface5 2, 400Mb/s 3, 200Mb/sI/O Pins 832 1, 456Specialization Signal Processing Overall Performance

[18, 38, 44–49, 51, 53, 56–58]

1based on symmetrical filter implementation2single-precision, hardened floating point DSP performance3Full Duplex4x8 Gen35DDR4


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Summary and Conclusion

Summary• "More is better Mindset"• Kintex UltraScale, Virtex

UltraScale• 2nd generation 3D ICs• Improvements on former

bottlenecks (i.e.interconnect)

• Special Features (e.g.ASIC-like clocking)

Conclusion• Specialization

− Signal processing(Kintex UltraScale)

− Overall performance(Virtex UltraScale)

• Poorer performancethan competition, butalready available

⇒ Final Evaluation notuntil Stratix 10 is

available!


StephanieRupprich

FPGA Basics


Altera Stratix 10


Market Requirements

Device Portfolio

Features

Applications

Evaluation


21/21

Summary and Conclusion

Summary• "More is better Mindset"• Kintex UltraScale, Virtex

UltraScale• 2nd generation 3D ICs• Improvements on former

bottlenecks (i.e.interconnect)

• Special Features (e.g.ASIC-like clocking)

Conclusion• Specialization

− Signal processing(Kintex UltraScale)

− Overall performance(Virtex UltraScale)

• Poorer performancethan competition, butalready available

⇒ Final Evaluation notuntil Stratix 10 is

available!


StephanieRupprich

AdditionalMaterialEvaluation Details

Application Example

References

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Appendix

6 Additional MaterialEvaluation DetailsApplication Example

7 References


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References

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Evaluation DetailsMaximumCapability

Virtex-7 KintexUltraScale

VirtexUltraScale

Stratix10

Introd./Shipm. 2010/2011 2013/2014 2013/?ProcessTechnology

28nm planar 20nm planar 20nm planar,16nm FinFET

14nm TriGate

Logic Cells 1, 955K 1, 160K 4, 407K > 4, 000KBlock RAM 68Mb 76Mb 115MbDSP Slices 3, 600 5, 520 2, 880DSPPerformance

5, 335GMAC/s1 8, 180GMAC/s1 4, 268GMAC/s1 >10, 000GFLOP/s2

Transceivers 96 64 104 144TransceiverSpeed

28.05Gb/s 13.6Gb/s 32.75Gb/s 56Gb/s

TransceiverBandwidth

2, 784Gb/s3 2, 086Gb/s3 5, 101Gb/s3 8, 064Gb/s

PCIe Blocks 1 4 6100g Ethernet 2 7150G Interlaken 1 9MemoryInterface4

1, 866Mb/s 2, 400Mb/s 3, 200Mb/s

I/O Pins 1, 200 832 1, 456Specialization System

PerformanceSignal

ProcessingOverall Performance

[18, 26, 36–38, 44–49, 51, 56–58]

1based on symmetrical filter implementation2single-precision, hardened floating point DSP performance3Full Duplex4Virtex-7: DDR3, others: DDR4


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ApplicationsSuper Hi-Vision Camera

Figure 16 : Example Application: Super Hi-Vision Camera [73]

[30, 73]


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References I

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[2] Altera Corporation. (2014) Fpgas. Website. Altera Corporation. [Online]. Available:http://www.altera.com/products/fpga.html

[3] Xilinx Inc. (2014) What is a fpga? Website. Xilinx Inc. [Online]. Available:http://www.origin.xilinx.com/fpga/

[4] National Instruments Corporation. (2012, May) Fpga fundamentals. Whitepaper. [Online]. Available:http://www.ni.com/white-paper/6983/en/

[5] M. Abdel-Ghany. (2012, April) Fpga-911. Website. [Online]. Available:http://www.vlsiegypt.com/home/?p=226

[6] F. Castro. (2012, July) Design of a 8051 microcontroller in fpga with reconfigurable instruction set.Article on design-reuse.com. Recife, Brasil. [Online]. Available: http://www.design-reuse.com/articles/29745/8051-microcontroller-with-reconfigurable-instruction.html

[7] J. Weber and M. Chin, “Using fpgas with embedded processors for complete hardware and softwaresystems,” in AIP Conference Proceedings, vol. 868, 2006, p. 187.

[8] J. Tong, I. D. L. Anderson, and M. A. S. Khalid, “Soft-core processors for embedded systems,” inMicroelectronics, 2006. ICM ’06. International Conference on, 2006, pp. 170–173.

[9] B. H. Fletcher, “Fpga embedded processors,” in Embedded Systems Conference, 2005, pp. 1–18.[Online]. Available:http://www.xilinx.com/products/design_resources/proc_central/resource/ETP-367paper.pdf

[10] Xilinx, Inc., “Edk overview,” 2011, xilinx For Academic Use Only.[11] R. Dobai and L. Sekanina, “Towards evolvable systems based on the xilinx zynq platform,” in Evolvable

Systems (ICES), 2013 IEEE International Conference on, 2013, pp. 89–95.[12] Pantech ProLabs India Pvt Ltd. (2014) User manual for spartan-6 tyro kit. Pantech ProLabs India Pvt

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http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3&CFID=5147978&CFTOKEN=a1eef1bbe8fce6f0-C9D41905-5056-0201-02A35B5B30FAD0E8

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3&CFID=5147978&CFTOKEN=a1eef1bbe8fce6f0-C9D41905-5056-0201-02A35B5B30FAD0E8

http://www.altera.com/products/fpga.html

http://www.origin.xilinx.com/fpga/

http://www.ni.com/white-paper/6983/en/

http://www.vlsiegypt.com/home/?p=226

http://www.design-reuse.com/articles/29745/8051-microcontroller-with-reconfigurable-instruction.html

http://www.design-reuse.com/articles/29745/8051-microcontroller-with-reconfigurable-instruction.html

http://www.xilinx.com/products/design_resources/proc_central/resource/ETP-367paper.pdf

https://www.pantechsolutions.net/project-kits/spartan-6-tyro-kit-user-guide


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References II[13] Wikipedia. (2014, January) Serdes. Encyclopedia Entry. Wikimedia Foundation, Inc. [Online]. Available:

http://en.wikipedia.org/wiki/SerDes[14] Altera Corporation, “The breakthrough advantage for fpgas with tri-gate technology,” Altera

Corporation, White Paper 01201, June 2013. [Online]. Available:http://www.altera.com/literature/wp/wp-01201-fpga-tri-gate-technology.pdf

[15] Xilinx Inc. (2014) Virtex ultrascale. Website. Xilinx Inc. [Online]. Available:http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html

[16] Altera Corporation. (2014) About altera’s cyclone fpga series. Website. Altera Corporation. [Online].Available: http://www.altera.com/devices/fpga/cyclone-about/cyc-about.html

[17] ——. (2014) About arria family fpgas and socs. Website. Altera Corporation. [Online]. Available:http://www.altera.com/devices/fpga/arria-fpgas/about/arr-about.html

[18] ——. (2014) About stratix family high-end fpgas and socs. Website. Altera Corporation. [Online].Available: http://www.altera.com/devices/fpga/stratix-fpgas/about/stx-about.html

[19] Xilinx, Inc., “Virtex-4 family overview,” Xilinx, Inc., Data Sheet DS112, August 2010. [Online].Available: http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf

[20] ——, “Virtex-5 family overview,” Xilinx, Inc., Data Sheet DS100, February 2009. [Online]. Available:http://www.xilinx.com/support/documentation/data_sheets/ds100.pdf

[21] ——, “Virtex-6 family overview,” Xilinx, Inc., Data Sheet DS150, January 2012. [Online]. Available:http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf

[22] Xilinx Inc. (2014) Virtex-7 fpga family. Website. Xilinx Inc. [Online]. Available:http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm

[23] ——. (2014) Spartan-6 fpga family. Website. Xilinx Inc. [Online]. Available:http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/index.htm

[24] ——. (2014) Artix-7 fpga family. Website. Xilinx Inc. [Online]. Available:http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm

[25] ——. (2014) Kintex-7 fpga family. Website. Xilinx Inc. [Online]. Available:http://www.xilinx.com/products/silicon-devices/fpga/kintex-7/index.htm

http://en.wikipedia.org/wiki/SerDes

http://www.altera.com/literature/wp/wp-01201-fpga-tri-gate-technology.pdf

http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html

http://www.altera.com/devices/fpga/cyclone-about/cyc-about.html

http://www.altera.com/devices/fpga/arria-fpgas/about/arr-about.html

http://www.altera.com/devices/fpga/stratix-fpgas/about/stx-about.html

http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf



http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/index.htm

http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm

http://www.xilinx.com/products/silicon-devices/fpga/kintex-7/index.htm


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References III

[26] N. Mehta, “Xilinx redefines power, performance, and design productivity with three innovative 28 nmfpga families: Virtex-7, kintex-7, and artix-7 devices,” Xilinx, Inc., White Paper WP373, October 2012.[Online]. Available:http://www.xilinx.com/support/documentation/white_papers/wp373_V7_K7_A7_Devices.pdf

[27] Altera Corporation. (2014) Altera fpgas. Website. Altera Corporation. [Online]. Available:http://www.altera.com/devices/fpga/fpga-index.html

[28] ——, “Altera’s 28 nm device portfolio,” Altera Corporation, Tech. Rep., May 2014. [Online]. Available:http://www.altera.com/literature/br/br-28nm-devices.pdf

[29] ——, “Altera product catalog,” Altera Corporation, Tech. Rep., November 2013, version 13.1.[Online]. Available: http://www.altera.com/literature/sg/product-catalog.pdf

[30] M. Santarini, “Xilinx 20-nm planar and 16-nm finfet go ultrascale,” Xcelljournal, vol. 84, pp. 8–15,2012. [Online]. Available: http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

[31] Wikipedia. (2014, April) Semiconductor device fabrication. Encyclopedia Entry. Wikimedia Foundation,Inc. [Online]. Available: http://en.wikipedia.org/wiki/Semiconductor_device_fabrication

[32] Wikipedia. (2013, November) Low-k dielectric. Encyclopedia Entry. Wikimedia Foundation, Inc.[Online]. Available: http://en.wikipedia.org/wiki/Low-k_dielectric

[33] ——. (2014, March) High-k dielectric. Encyclopedia Entry. Wikimedia Foundation, Inc. [Online].Available: http://en.wikipedia.org/wiki/High-k_dielectric

[34] ——. (2014, June) Moore’s law. Encyclopedia Entry. Wikimedia Foundation, Inc. [Online]. Available:http://en.wikipedia.org/wiki/Moore%27s_law

[35] A. L. Shimpi. (2012, May) The ipad 2,4 review: 32nm brings better battery life. Blog Entry.anandtech.com. [Online]. Available:http://www.anandtech.com/show/5789/the-ipad-24-review-32nm-a5-tested

[36] B. Fienberg. (2010, June) Xilinx 7 series fpgas slash power consumption by 50and reach 2 million logiccells on in-dustry’s first scalable architecture. Press Release. Xilinx Inc. [Online]. Available: http://press.xilinx.com/2010-06-21-Xilinx-7-Series-FPGAs-Slash-Power-Consumption-by-50-and-Reach-2-Million-Logic-Cells-on-Industrys-First-Scalable-Architecture

http://www.xilinx.com/support/documentation/white_papers/wp373_V7_K7_A7_Devices.pdf

http://www.altera.com/devices/fpga/fpga-index.html

http://www.altera.com/literature/br/br-28nm-devices.pdf

http://www.altera.com/literature/sg/product-catalog.pdf

http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

http://en.wikipedia.org/wiki/Semiconductor_device_fabrication

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http://www.anandtech.com/show/5789/the-ipad-24-review-32nm-a5-tested

http://press.xilinx.com/2010-06-21-Xilinx-7-Series-FPGAs-Slash-Power-Consumption-by-50-and-Reach-2-Million-Logic-Cells-on-Industrys-First-Scalable-Architecture

http://press.xilinx.com/2010-06-21-Xilinx-7-Series-FPGAs-Slash-Power-Consumption-by-50-and-Reach-2-Million-Logic-Cells-on-Industrys-First-Scalable-Architecture


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References IV

[37] Xilinx, Inc., “7 series fpgas overview,” Xilinx, Inc., Advance Product Specification DS180, February2014. [Online]. Available:http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

[38] Xilinx Inc. (2014) All programmable fpgas. Website. Xilinx Inc. [Online]. Available:http://www.xilinx.com/products/silicon-devices/fpga/index.htm

[39] Xilinx, Inc. (2014) Axi interconnect. Website. Xilinx, Inc. [Online]. Available:http://www.xilinx.com/products/intellectual-property/axi_interconnect.htm

[40] ——, “Revolutionary architecture for the next generation platform fpgas,” December 2003,presentation. [Online]. Available:http://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf

[41] D. Bursky. (2013, December) Modular fpga architecture spawns multiple silicon optimizations.Website. electronicdesign.com. [Online]. Available:http://electronicdesign.com/dsps/modular-fpga-architecture-spawns-multiple-silicon-optimizations

[42] T. Snowden. (2003, December) Xilinx unveils revolutionary fpga architecture, enables next-generationplatform fpgas. Press Release. Xilinx, Inc. [Online]. Available:http://www.xilinx.com/prs_rls/silicon_vir/03160arch.htm

[43] Wikipedia. (2014, June) Relative permittivity. Encyclopedia Entry. Wikimedia Foundation, Inc.[Online]. Available: http://en.wikipedia.org/wiki/Relative_permittivity

[44] Altera Corporation, “Meeting the power and performance imperative of the zettabyte era withgeneration 10,” Altera Corporation, White Paper 01200, June 2013. [Online]. Available:http://www.altera.com/literature/wp/wp-01200-power-performance-zettabyte-generation-10.pdf

[45] S. Gabriel. (2013, June) Altera announces breakthrough advantages with generation 10. Press Release.Altera Corporation. [Online]. Available:http://newsroom.altera.com/press-releases/nr-altera-generation-10.htm

[46] Altera Corporation. (2014) Stratix 10 fpgas and socs deliver 2x performance gains. Website. AlteraCorporation. [Online]. Available:http://www.altera.com/technology/system-tech/next-gen/fpga-architecture-performance.html

http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

http://www.xilinx.com/products/silicon-devices/fpga/index.htm

http://www.xilinx.com/products/intellectual-property/axi_interconnect.htm

http://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf

http://electronicdesign.com/dsps/modular-fpga-architecture-spawns-multiple-silicon-optimizations

http://www.xilinx.com/prs_rls/silicon_vir/03160arch.htm

http://en.wikipedia.org/wiki/Relative_permittivity

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StephanieRupprich


Application Example

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StephanieRupprich


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