Thermal Measurement and Modeling of Multi-Die Packages

484 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 32, NO. 2, JUNE 2009

Thermal Measurement and Modelingof Multi-Die Packages

András Poppe, Member, IEEE, Yan Zhang, John Wilson, Gábor Farkas, Péter Szabó, John Parry,Márta Rencz, Member, IEEE, and Vladimír Székely

Abstract—Thermal measurement and modeling of multi-diepackages with vertical (stacked) and lateral arrangement becamea hot topic recently in different fields like RAM chip packagingor LEDs and LED assemblies. In our present study, we presentresults for a more complex structure: an opto-coupler device withfour chips in a combined lateral and vertical arrangement. Thepaper gives an overview of measurement and modeling techniquesand results for stacked and multichip module (MCM) structures.It describes actual measurement results along with our structurefunction-based methodology which helps validating the detailedmodel of the package being studied. For stack-die packages, wesuggest an extension of the DELPHI model topology. Also, weshow how one can derive junction-to-pin thermal resistances witha technique using structure functions.

Index Terms—Compact thermal modeling, multi-die packages,stacked-die package modeling, structure functions, thermal tran-sient testing.

I. INTRODUCTION

T HERMAL measurement and modeling of multi-die pack-ages became a hot topic in recent years. A detailed, com-

prehensive overview has been given recently [1] where differentmeasurement and modeling techniques have been referred to.Nowadays, besides IR techniques (e.g., [2]), the mainstreamcharacterization technique seems to be the JEDEC JESD51-1-based electrical test method [3], yielding either thermal resis-tance values only (static characterization – see, e.g., [4], [5])or providing the dynamic description of the packaged multi-diesystem by means of thermal impedances in various forms (fullset of real heating or cooling curves, complex loci—see, e.g.,[6] or structure functions as presented in [7]).

Manuscript received April 25, 2008; revised May 06, 2008. First publishedFebruary 20, 2009; current version published July 22, 2009. This work was rec-ommended for publication by Associate Editor C. Lasance upon evaluation ofthe reviewers comments.

A. Poppe and G. Farkas are with Mentor Graphics MicReD Division(formerly MicReD, Ltd.), Budapest XI, H-1119 Hungary (e-mail: [email protected]).

P. Szabó was with MicReD, Ltd., Budapest XI, H-1119 Hungary.Y. Zhang was with Flomerics, Inc., Santa Clara, CA 95054 USA. She is now

with Tessera, Inc., Santa Clara, CA 95134 USA (e-mail: [email protected]).J. Parry is with Mentor Graphics Mechanical Analysis Division (formerly

Flomerics, Ltd), Hampton Court, Surrey KT8 9HH, U.K. (e-mail: [email protected]).

J. Wilson is with Mentor Graphics Mechanical Analysis Division (formerlyFlomerics, Inc.), San Jose, CA 95131 USA (e-mail: [email protected]).

M. Rencz and V. Székely are with the Department of Electron Devices, Bu-dapest University of Technology and Economics (BME), Budapest XI, H-1111,Hungary, e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAPT.2008.2004578

In many cases, thermal transient measurements are used toderive steady-state metrics for multi-die systems [7], [8] butthere is no agreement yet on what these metrics should be. Oneapproach is to try to derive a single value to represent andmodel a multi-die package [2], [4]. A next step in representingmulti-die packages is to use multiple thermal resistances [5],[7]. A recent tendency is to measure the temperature change onall chips in the package and to report the results of all thesemeasurements. In what format and with what content this re-porting should be done, is still open to discussion [9], but mea-suring and reporting a full thermal resistance matrix[7], [8] orthermal impedance matrix[6], [10] seems to gain wider accep-tance among different thermal research teams.

The attempts to create thermal models out of measurement re-sults include resistor networks with a few elements only [5], [7]or providing the network representation of the complete thermalresistance matrix [8] or providing all the elements of the thermalimpedance matrix by means of time-domain or frequency-do-main functions [6], [10] or even by means of a dynamic com-pact model derived from structure functions [10].

In Section II, we provide an overview of thermal transientmeasurement-based characterization through a few typicalexamples. In Section III, we introduce our recent results inmodeling of single and multi-die packages with a special em-phasis on structure function-based detailed model verification.Section IV presents two case studies: through the example ofa two-die stack, we suggest extensions of the DELPHI modeltopology, and we present test results of an opto-coupler deviceincluding four chips both in lateral and vertical arrangement.Through this case study, we also present our technique toobtain junction-to-pin thermal resistance values from structurefunctions.

II. OVERVIEW OF CHARACTERIZATION OF

TYPICAL MULTI-DIE PACKAGES

Typical multi-die packages contain dies either in a vertical(stacked) arrangement or in a lateral arrangement.

As the silicon technology continues to obey Moore’slaw—according to which, the number of IC elements on a unitsilicon area doubles every 18–24 months—layering the siliconchips on top of each other within a package multiplies the in-crease originated by shrinking transistor size, by the number oflayered dice. 3-D stacked-die packages are especially commontoday in RAM packaging and in handheld devices, especially incell phones and digital cameras, which require fast turnaround,very high level of integration, and low cost that is characteristicin general for system-in-package (SiP) solutions. Another

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POPPE et al.: THERMAL MEASUREMENT AND MODELING OF MULTI-DIE PACKAGES 485

Fig. 1. Two test dies stacked in a 144 LQFP package.

Fig. 2. Thermal impedance matrix of the stacked-die package of Fig. 1. Matrixelements are represented by time-domain transient impedance (��) curves.

typical application is integrating chips realized by differenttechnologies into a single package.

In our first example, we present a stacked arrangement. A 144low-profile quad flat package (LQFP) package containing twotest dies (cross-sectional view in Fig. 1) has been characterizedboth in JEDEC standard still-air environment and in a cold-platesetup [10]. In each test environment, thermal transient measure-ments have been carried out. A power step has been applied onthe top, and later, on the bottom die in a sequential manner andthe transient responses were captured in each case on both dies.This way, for each test environment we obtained all the elementsof the package’s thermal impedance matrix: two driving-pointimpedances (heating and measurement at the same location) andtwo transfer impedances (heating the top die and capturing thetemperature on the bottom die and vice versa).

Fig. 2 presents the measurement results for a cold-plate envi-ronment. As one can see, the thermal impedance matrix ofthe package shows asymmetry. and elements of the ma-trix (thermal transfer impedances between the top and bottomdies) differ in the small time-constant range suggesting, that thetop-to-bottom and bottom-to-top heat transfer differ, due to thedifferent size of the dies.

As an alternate representation, the time-domain re-sponse of the th die when a unit power step is applied at die

can be transformed into the frequency-domain as follows:

(1)

Fig. 3. Frequency-domain representation of the thermal impedance matrix ofthe stacked-die package.

Fig. 4. P-TO263-15-1 package , internal leadframes, footprint, and tab num-bering (H1, H2, H3).

Fig. 3 shows the frequency-domain representation of theimpedance matrix of the 144 LQFP package. Again, the asym-metry can be observed. This asymmetry in the impedancematrix means nonreciprocal behavior which, when a compactmodel is to be constructed, has to be accounted for.

As a next example, we show a lateral arrangement of fourpower DMOS switches in a P-TO263-15-1 package. The centerchip contains two switches; two other chips on separate tabshave single switches [6].

This package (Fig. 4) has also been characterized withthermal transient measurements: all elements of its thermalimpedance matrix have been measured, both in a still-air andin a cold-plate setup.

Measuring the package in still-air setup, we got the fre-quency-domain representation of the impedance matrix plottedin Fig. 5. Driving the larger chip on the H2 center tab theself-impedance ( ) is lower than when driving the smallerchip ( ). Again, the off-diagonal elements show nonrecip-rocal behavior, .

In general, one can say, that in a given test environment, amulti-die package (having any kind of arrangement) is totallyrepresented by its full thermal impedance matrix in the formshown by (2). Here, off-diagonal elements represent thermaltransfer impedances between junctions and ; describes theself-impedance or driving point impedance at the junction of theth die.


Fig. 5. Comparison of complex loci in still-air setup. Curves � , � mea-sured with junction on H1 driven, � , � measured with junction on H2driven.

The impedance matrix elements can be described either bytime-domain functions (impedance curves) or by frequency-do-main functions (e.g., by complex loci) or by network models ofthe impedances. Multiplying this matrix with the vector of anycombination of powers applied at the chips, one can obtainthe corresponding vector of the temperature responses at alldies, as follows:

......

......

(2)

Note that the above impedance matrix reduces to a thermal re-sistance matrix if the steady-state values of the time-domain im-pedances ( ) or if the 0-Hz value of the frequency-domainimpedance values are considered. Such an matrix is pre-sented for multi-die LED assembly in [8], where asymmetry ofthe off-diagonal elements of the matrix has also been reported.

With chips in a package, there are thermal impedancespresent. driving point impedances describe the heat-removalproperties from the junction on a die towards the ambient. Forevery die there are other impedances that describe theproperties of heat transfer from the driven die to any other diein the package.

The matrix elements can be identified by thermal transientmeasurements. In measurement , the th die is excited (a powerstep is applied to it) and the temperature responses on all dies aremeasured and recorded. The measurements can be carried out instandard test environments as prescribed by the JEDEC JESD51series of standards [3]. In this way, the thermal impedance ma-trix concept is a natural, unambiguous extension of the JEDECJESD51-1 concept of a single junction-to-ambient resistance formulti-die packages. It describes steady-state properties and dy-namic behavior of a multi-die package.

III. MODELING ISSUES

A. Compact Modeling

As mentioned in the introduction, there have been several at-tempts to develop compact models of multi-die packages. Manyteams have aimed to create steady-state models by means of a

Fig. 6. Nonreciprocal steady-state compact model of a two-die package.

Fig. 7. Dynamic compact model of stacked-die package.

single or just a few thermal resistances [2], [4], [5], [7] or bymeans of a complete thermal resistance matrix [8]. Our teamhas focused its efforts on developing general models. In one ap-proach to modeling multi-die packages, the matrix representa-tion of the package is used with the aim of developing compactmodels which also exhibit the reported nonreciprocal behavior.Such a model is shown in Fig. 6.

The resistor values are to be taken from the thermal resistancematrix of the package: and (elements of the main diag-onal) describe the self-heating when die 1 and die 2 are heated,respectively. Resistors and describe the coupling be-tween the two dies. The temperature controlled heat-flux gener-ators (framed in the figure) ensure that either or is ef-fective, depending at which die heating is applied, allowing theentire model to reflect the nonreciprocity (asymmetry) shownby the measurement results (see previous section).

If dynamic behavior is to be considered, the element valuesof the impedance matrix need to be represented by a proper ap-proximation (e.g., with more RC elements) and should be usedin the model shown in Fig. 6.

Another compact modeling approach tries to derive dynamiccompact models from measurement results using structure func-tions. Such a model for a stacked-die package is shown in Fig. 7.Element values for this model can be obtained from a step-wise approximation of the cumulative structure function corre-sponding to the driving point thermal impedance measured atthe top die [1], [10].

Boundary condition independent compact models (eithersteady-state or dynamic) have not been widely reported formulti-die packages. At present our team carries out researchin this direction. Our approach tries to extend the DELPHI


Fig. 8. Suggested flow of validation of detailed models with the help of struc-ture functions.

methodology [11], [12] in two directions. One goal is to prop-erly account for multiple dies and the possibly asymmetricalcouplings among them. Another goal is to create dynamicmodels.

B. Structure Functions for Validation of Detailed Models

In the DELPHI methodology and its extension to single dietransient package models creation of boundary condition inde-pendent compact models is based on validated detailed models.For this purpose thermal measurements are carried out in fourdifferent dual cold plate setups [13] and results are comparedagainst simulation results. Now, instead of comparing the rawtransient curves themselves we suggest using structure func-tions for model validation.

The reason behind this is that if a detailed model properlydescribes physical reality, the structure functions derived fromsimulated transient responses should show exactly the same fea-tures as the structure functions derived from the thermal tran-sient measurements of the real physical package. The suggestedflow of model validation is shown in Fig. 8.

This model validation method is of special interest if thedetailed model is to be used for generating dynamic compactmodels since here the distribution of thermal capacitancesand thermal resistances along a given major heat-flow path isessential.

In case of modeling multi-die packages, especially withstacked structures, the proper modeling of the internal parts ofthe package is important. For a stacked-die arrangement, thechip-to-chip couplings have to be properly described, for whichwe should fine tune the detailed models of the various chips anddie attach layers. With the help of the structure functions oneshould be able to differentiate between the dies and optimizethe model of the die attach layers.

IV. CASE STUDIES

A. Testing a Two Die Stack in Different Test Environments

To go forward towards creating compact thermal model ofour simple stacked-die package example (Fig. 1), we carriedout measurements of thermal impedance matrices for all dualcold-plate (DCP) setups used in the DELPHI methodology.

Fig. 9. DCP1 and modified DCP1 setup of the package of Fig. 1.

Fig. 10. Structure functions obtained from DCP1 and modified DCP1 measure-ment results for the stacked-die package shown in Fig. 1.

From the driving-point impedances structure functions havebeen created, also for modeling purposes. The scheme of theapplied test setups is shown in Fig. 8. When pedestals areinserted between the package top or bottom surface and thecold-plate, extra thermal resistance is introduced in the junc-tion-to-ambient heat-flow path. In order to be able to distinguishbetween partial thermal resistances of the heat-flow path insideand outside the package, the principle of the double interfacemethod[6] was applied: a thin thermal insulator (in our case:Mylar) layer was inserted between the package surface andthe pedestal. Fig. 9 shows the original and the modified DCP1setup for our stacked-die package example. Fig. 10 presentsthe measurement results for both DCP1 setups case when thetop die was heated. The structure functions diverge where thestructure was changed, that is, at the bottom surface of thepackage.

From Fig. 10 we can read that the Mylar layer introduced anadditional 10 K/W to the value of the setup and the wecan also see, that the thermal resistance realized by the pedestalwas about 5 K/W. In Fig. 11, these results are compared withthe results obtained when the bottom die was heated. In theseplots too, we can see the thermal resistance of the pedestal and


Fig. 11. Structure functions obtained from DCP1 and modified DCP1 measure-ment results when the top die is heated and when the bottom die is heated.

Fig. 12. Structure functions obtained from DCP1, 2, and 3 measurement resultswhen the top die is heated.

we can also identify the thermal capacitances of the leadframeand the chips. In Figs. 12 and 13, different DCP measurementresults are compared when the top die and the bottom die wereheated (without the Mylar sheet). It is interesting to note in thesefigures that the internal details of the stack shown by these struc-ture functions are independent of the actual set of boundary con-ditions realized by the DCP setups. This suggests that in thisparticular package example the heat generated by the dies leavesthe package through the leadframe and the leads.

Based on these structure functions, one can create a com-pact thermal model for the stack of the dies [10]. Since in ourcase the thermal capacitance/thermal resistance values relatedto the internal details of the stacked-die package did not changewith the different boundaries, the thermal resistance values de-scribing the junction-to-junction couplings identified from thestructure functions are directly applicable in creating BCI com-pact models of stacked dies in LQFP like packages.

B. Extension of the DELPHI Topology to Stacked-DiePackages

When creating a DELPHI like model for stacked-die pack-ages, the single junction node of the original DELPHI model

Fig. 13. Structure functions obtained from DCP1, 2, 3, and DCP4 measurementresults when the bottom die is heated.

Fig. 14. Suggested model topology for DELPHI style BCI compact model forstacked-die packages.

has to be split and—for steady-state—a resistive network needsto be inserted which accounts for the individual junction nodes(corresponding to each die in the stack) and describes the cou-pling among them. Fig. 14 shows the model topology we sug-gest. For example, the value indicated in the figure de-scribes the thermal resistance between the junction of die 1 andthe junction of die 2. This value can be read from the structurefunctions as shown, e.g., in Fig. 12 for the case of the two diestack of Fig. 1 (about 3.6 K/W). For dynamic models thermalcapacitance values of the chips can also be identified from struc-ture functions (see also [10]).

The nonreciprocal behavior of the chosen stacked-die ex-ample was already demonstrated by Fig. 2 (for time-domain)and by Fig. 3 (for frequency-domain). To account for this inthe DELPHI topology, the appropriate network models needto be combined. That is, we suggest inserting a nonreciprocalmodel of the stack into the DELPHI model of the package.Restricting our discussion to the simple two-die example andsteady-state case, this means that a model like shown in Fig. 6is to be inserted. The resulting topology of a nonreciprocalDELPHI-like model of a two-die stack is shown in Fig. 15.

The nonreciprocal network inserted into the original DELPHImodel resembles the boundary condition dependent model of


Fig. 15. Model topology for DELPHI style BCI compact model for stacked-diepackages accounting for nonreciprocal coupling among dies.

Fig. 6. Now, in the boundary condition-independent (BCI) casethe driving point resistances at the junctions of the individualdies ( and in Fig. 6) are replaced by the originalDELPHI model itself. The strength of the coupling betweenthe two dies (top and bottom dies) is described by andin the DELPHI style nonreciprocal stacked-die package model.While in the boundary condition-dependent case, the elementvalues (denoted by and in Fig. 6) were the off-diagonalelements of the thermal resistance matrix of the package; inthe BCI case these are values provided by the model optimizeralgorithm. This is denoted by using the superscript.

C. An Opto-Coupler Device in a Plastic DIL Package

In this second study, we present thermal transient measure-ment and simulation results of dual opto-coupler devices. Theplastic DIL package contained four chips in a nonstandard con-figuration used by one of our industrial clients. A single opto-coupler had its two chips in a vertical arrangement: there was anIR LED (emitter) on the top and a photo-transistor (detector) un-derneath. The package had two leadframes: one containing theemitter chips, another one holding detector chips in a lateral ar-rangement. We had two versions of the opto-coupler: with a low-power detector and with a detector having a power output stage.The general geometry of the studied devices is shown in Fig. 16.We had our samples attached to JEDEC standard thermal testboards with low and high thermal conductivity which were mea-sured in a JEDEC standard 1 ft still-air chamber, and we mea-sured a few samples also in a cold plate environment. The goalof this case study is to present characterization techniques ratherthan describing how to optimize the package design.

D. Test Results

In our study, we were interested in the driving point im-pedances of the emitter and detector chips as well as inthe emitter–detector, emitter–emitter and detector–detector

Fig. 16. Dual opto-coupler devices in a plastic DIL package containing fourchips: cross-sectional view of the package and 3-D axonometric view of thedetailed CAD model.

thermal couplings. We derived JEDEC standard thermal met-rics from structure functions which were obtained by thermaltransient test using the T3Ster equipment. (Since we could notopen the plastic DIL packages, we had no means of identifyingthe radiated power of the emitter LEDs, so the total suppliedelectrical power of the emitters was considered as heatingpower.) First, we validated the detailed model of the packageusing the FLOTHERM program and using cold plate measure-ments. In a next step, this validated model was attached to themodel of the still-air environment. In this way we were able toderive the following:

• junction-to-ambient thermal resistance values for theemitter and detector chips;

• junction-to-case;• junction-to-pin (junction-to-lead) thermal resistance

values for both types of chips;• the transfer conductances between the various chips inside

the packages;• the validated model of the packages;

all from thermal transient measurements using structure func-tions. The term “junction-to-case” here denotes simply the par-tial thermal resistance between the junction and the bottom ofthe package, which has actually no “case,” i.e., exposed tab.We introduced this measurement only to increase the numberof boundaries for modeling.

In Fig. 17, we present some measurement results for the firsttype with low power detector; Fig. 18 shows structure functions.In this figure, the straight thick lines added to the plot corre-spond to the radial heat-spreading in the test boards. So, as sug-gested already by curves one can distinguish the heat-flowinside the package and in the test environment. It is worth notingthat all structure functions coincide in the regions describing theheat-flow in the package and pins, whatever test board is used.Note also that the test environment represents a considerable


Fig. 17. Measured thermal impedances with detector driven in “low power”samples. Still-air environment, low conductance (LCB), and high conductance(HCB) board.

Fig. 18. Cumulative structure functions of driving point thermal impedancesin the same arrangement.

part of the total junction-to-ambient thermal resistance, in caseof the low conductivity board this is almost 50%.

E. Steady-State Thermal Metrics

JEDEC type steady-state thermal metrics have been identi-fied both from the physical test results and from the simula-tion of the validated detailed models. The junction-to-ambientthermal resistance values are read directly from the structurefunctions: the location of the singularity provides thevalue for any test environment. For the identification of junc-tion-to-case thermal resistance values, the so-called dual inter-face method was used [6]. Here, two measurements were carriedout: one with the “case” surface of the package in a direct con-tact with a cold plate and a second with a thermal insulator layerinserted between the package and the cold plate. The resultingstructure functions are shown in Fig. 19.

The junction-to-pin thermal resistance values were identifiedusing a similar method.

• The samples were measured in a JEDEC standard still-airenvironment.

Fig. 19. Identification of� values for the second series of devices (�for the detector chip).

Fig. 20. Cold-plate setups for the identification of the� value for the “highpower” type of devices (� for the detector chip).

• The measurements were repeated with an extra thermalmass attached to the pins. Structure functions were derivedfrom both sets of thermal transient curves.

• As the structural change occurred at the pins, thus the lo-cation where deviation is observed in the structure func-tions gives the value of the junction-to-pin thermal resis-tance (Fig. 20).

V. CONCLUSION

In this paper, we gave an overview on measurement and mod-eling of multi-die packages. Packages with both vertical and lat-eral chip arrangements have been discussed.

Several measurement examples have demonstrated that cou-pling between different chips in multi-die packages may showasymmetry, which has also been reported by other researchteams. This asymmetry necessitates the use of network elementswhich have been unusual in compact thermal models. Temper-ature-controlled heat-flux generators can be used to properlymodel the nonreciprocal behavior observed in measurements.

The use of thermal resistance matrices (steady-state descrip-tion) or thermal impedance matrices (dynamic case) provides


an unambiguous extension of usual single-die thermal metricsto multi-die packages.

When simulation of the detailed model does not fit measure-ments in the physical structure, then structure functions helpidentify parts where deviation occurs. This validation of detailedmodels is of primary importance for stacked-die packages.

As an extension of our earlier suggestion of structure func-tion-based stacked-die package modeling, we suggested an ex-tension of the DELPHI model topology to include a compactmodel of the stack. A second extension of the DELPHI modeltopology has also been suggested which allows accounting forany possible asymmetry of thermal couplings among differentdies in a stacked-die package.

Finally, we presented a case study with four dies both in avertical and lateral arrangement. The elements of the thermalimpedance matrix of that package were identified in the formof thermal impedance curves for different types of test environ-ments. Structure function-based methods were used to obtainsome steady-state thermal metrics of the package: the modifica-tion of the dual interface method was suggested to derive junc-tion-to-pin thermal resistances. Validated by test results, the de-tailed model of the package has been also used to derive thermalmetrics in other standard test environments.

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András Poppe (M’99) received the M.Sc. degree inelectrical engineering and the Ph.D. degree from theFaculty of Electrical Engineering, Technical Univer-sity of Budapest (BME), Budapest, Hungary, in 1986and 1996, respectively.

His first research field was circuit simulation andsemiconductor device modeling. From 1989 to 1990,he spent a year at IMEC, Leuven, Belgium, wherehe was dealing with mobility modeling for the pur-pose of 2-D device simulation. Since 1990, he hasbeen with BME. He participated in the development

of circuit and device simulation programs. From 1991 to 1994, he was activein the field of Monte Carlo simulation of submicrometer MOS devices. Cur-rently, he is an Associate Professor at BME. His recent research activities in-clude electrothermal simulation of integrated circuits as well as thermal tran-sient testing of semiconductor devices and combined thermal and radiometricmeasurement of power LEDs. He was actively involved in European projectssuch as PROFIT, SYTIC, and REASON and in national R&D projects likeINFOTERM or TERALED. He has also been a Principal Investigator in someof these projects. He is one of the cofounders of MicReD (now part of MentorGraphics), Budapest, Hungary. His responsibilities at Mentor Graphics MicReDDivision include product management of thermal transient testing solutions.Currently, he is the representative of MicReD in the NANOPACK IntegratedProject of the 7th Framework Program of the EU. As an author and coauthor,he has published more than 140 technical papers in journals and in confer-ence/workshop proceedings.

Yan Zhang received the undergraduate degree fromShanghai University, Shanghai, China, in 1997 andthe M.S. degree from the National University ofSingapore in 2000 and the Ph.D. degree in electricalengineering from the University of California, SantaCruz, in September 2005.

Through her graduate research work she has au-thored and coauthored over 30 international confer-ence proceedings and over 20 journal papers. In 2006and 2007, she was an Application Engineer in the Mi-cReD North American Test Facility at Flomerics’ Sil-

icon Valley Office, Santa Clara, CA. Currently, she is a Senior R&D Engineerwith Tessera, Inc., where she is dealing with innovative cooling solutions.

Dr. Zhang won the Best Paper Award of the 2006 IEEE TRANSACTIONS ON

COMPONENTS AND PACKAGING TECHNOLOGIES for her paper “On-chip highspeed localized cooling using superlattice microrefrigerators.”

John Wilson received the B.S. and M.S. degreesin mechanical engineering from the University ofColorado, Denver.

Since joining Flomerics, he has worked on ormanaged more than 70 thermal and airflow designprojects. His modeling and design knowledge rangefrom component level to system level, heat sinkoptimization, and compact model development. Hehas extensive experience in IC package-level testand analysis correlation. He is currently the Con-sulting Engineering Manager of Mentor Graphics

Mechanical Analysis Division’s office, San Jose, CA.


Gábor Farkas received his electrical engineeringdegree in 1976 and the Ph.D. degree in 1981, bothfrom the Technical University of Budapest (BME),Budapest, Hungary.

His first research area was computer-aided recog-nition of circuit topologies and development of mi-croprocessors and other circuits. Since 1983, he hasbeen a Senior Lecturer in the Department of ElectronDevices of BME, full time and later part time. He hasdeveloped curricula on programming, semiconductortheory, design of integrated circuits, computer algo-

rithms, and other topics. Since 1990, he took part in several European projectsBARMINT, PROFIT, and most recently in the NANOPACK project of the EU.Since 2000, he has worked for MicReD, Ltd, Budapest. His main field of interesthas been developing hardware and software tools and measurement technolo-gies for thermal characterization of semiconductor devices. Currently, he is theEngineering Manager of Mentor Graphics MicReD Division. He has publishedover 60 technical papers in journals and conference/workshop proceedings.

Péter Szabó, photograph and biography not available at the time of publication.

John Parry received the B.Sc. (1st class honors) de-gree in chemical engineering from the University ofLeeds, Leeds, U.K., and the Ph.D. degree from theUniversity of Birmingham, Birmingham, U.K.

He has been with Flomerics (now Mentor GraphicsMechanical Analysis Division), Surrey, U.K., sincethe company was created in 1989. Prior to that, heworked for CHAM, Ltd., initially as a Consultant En-gineer and later as a Technical Support Manager. Heis now responsible for Flomerics’ research activitiesand education program. His technical contributions

have recently been in electronics cooling, and include the development of com-pact thermal models for fans, heat sinks, and chip packages, publishing sev-eral papers in these areas. He also has expertise in design of experiments andoptimization. As a Project Manager, he coordinated two EC-funded projects(DELPHI, SEED), and he represented Flomerics in the PROFIT project of theEU. He played major role in MicReD’s joining of the Flomerics Group PLC.

Dr. Parry serves on several conference committees and was General Chair ofSEMI-THERM 21.

Márta Rencz (M’95) received the M.S. and Ph.D.degrees in electrical engineering from the TechnicalUniversity of Budapest (BME), Budapest, Hungary,in 1973 and 1980, respectively.

Her first research area was the simulation ofsemiconductor devices. Later she participated inthe development of several CAD programs inmicroelectronics. Her latest research interests in-clude the thermal investigation of ICs and MEMS,thermal sensors, thermal testing, thermal simulation,electrothermal simulation, SOI modeling, and heat

transfer simulation in SOI structures. She was cofounder and CEO of MicReD,Budapest. She is currently the Director of Mentor Graphics MicReD Division.She has published her theoretical and practical results in more than 200technical papers.

Dr. Rencz received the Harvey Rosten Award of Excellence from the elec-tronics thermal management community for her research results in thermal mod-eling. She is a Member of IMAPS. She is Organizing Committee and ProgramCommittee member of several international conferences and workshops.

Vladimir Székely received the Ph.D. degree in elec-trical engineering from the Technical University ofBudapest (BME), Budapest, Hungary, in 1964.

He joined the Department of Electron Devices,BME, in 1964. Currently, he is a Full-Time Pro-fessor at BME and a corresponding member of theHungarian Academy of Sciences. He is one of thecofounders of MicReD, Budapest, Hungary. Hisearlier research interests were mainly in the areaof computer-aided design of integrated circuits,with particular emphasis on circuit simulation,

thermal simulation, and device modeling. He conducted the development ofseveral CAD programs in the field of integrated circuit design and simulation.Other areas of his technical interest are the theory of distributed networksand the problems of computer-graphics and image processing. He has beenengaged in the investigation of thermal properties of semiconductor devicesand integrated circuits for the last 25 years. This resulted in the developmentof novel thermal-based IC elements and thermal IC simulator programs. Hehas published his theoretical and practical results in more than 300 technicalpapers and 15 books or book chapters.

Documents

Thermal Measurement and Modeling of Multi-Die Packages