Three-Level Single-Phase Bridgeless PFC Rectifiers

0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TPEL.2014.2322314, IEEE Transactions on Power Electronics

1

Three-Level Single-Phase BridgelessPFC Rectifiers

Andre De Bastiani Lange, Thiago B. Soeiro, Member, IEEE, and, Marcio S. Ortmann, Member, IEEE,Marcelo L. Heldwein, Senior Member, IEEE

Abstract—This work presents new three-level unidirectionalsingle-phase PFC rectifier topologies well-suited for applicationstargeting high efficiency and/or high power density. The char-acteristics of a selected novel rectifier topology, including itsprinciples of operation, modulation strategy, feedback controlscheme, and a power circuit design related analysis are presented.Finally, a 220-V/3-kW laboratory prototype is constructed andused in order to verify the characteristics of the new converter,which include remarkably low switching losses and single ac-side boost inductor, that allow for a 98.6% peak efficiency witha switching frequency of 140 kHz.

Index Terms—PWM rectifier, Power factor correction, multi-level converter, high efficiency rectifier, ac-dc converter, PWMmodulation.

I. INTRODUCTION

AN unidirectional high power factor single-phase ac-dcsystem assembled by cascading a single-phase diode

bridge and a boost dc-dc converter is shown in Fig. 1(a).This converter system, known as conventional single-phasepower factor correction (PFC) boost-type rectifier, has manyinteresting features that justify its extensive use in industryfor power conversion below 1 kW, namely: it requires onlyone fast-switched diode, Db; it employs a single switch, Sb;the gate signal of Sb and the measurement circuits for theinput/output voltages can be referenced to the same potential,i.e., the negative output voltage terminal; the inductor Lbcurrent can be measured with a shunt resistor also referencedto the negative output voltage terminal; it can be operated withrelatively low complexity modulation and control strategies,where low cost dedicated analog integrated circuits can beemployed; it displays relatively low common mode (CM)emission levels. As a result, this ac-dc converter typicallyfeatures low production cost. Unfortunately, the current acrossLb is carried through three semiconductor devices in everyoperation stage, causing relatively high conduction losses.

Manuscript received December 31, 2013. Accepted for publication April15, 2014.

Copyright c©2013 IEEE. Personal use of this material is permitted. How-ever, permission to use this material for any other purposes must be obtainedfrom the IEEE by sending a request to [email protected] .

A. D. B. Lange is with the Power System Operation Department, CentraisEletricas de Santa Catarina (CELESC), Florianopolis, SC, 88034-900, Brazil(e-mail: [email protected]).

T. B. Soeiro is with the Power Electronics Group, ABB Corpo-rate Research, CH-5405, Baden-Daettwil, Switzerland (e-mail: [email protected]).

M. S. Ortmann and M. L. Heldwein are with the Electronics and Elec-trical Engineering Department (EEL), Federal University of Santa Catarina(UFSC), Florianopolis, SC, 88040-970, Brazil (e-mail: [email protected];[email protected]).

Additionally, in order to achieve high power density and/orlow input current total harmonic distortion (THD), this circuitneeds to operate at high switching frequencies, which can leadto unacceptably high switching losses since the switch anddiode must commutate the full dc-link voltage.

Unidirectional single-phase PFC rectifier topologies fea-turing low conduction losses were proposed in [1]–[18].Comparison among this type of topologies was performedin [19]–[22], while appropriate control techniques and elec-tromagnetic compatibility solutions to this type of converterswere discussed in [23]–[27] and [28]–[31], respectively. Someof the mentioned low conduction losses PFC rectifiers arepresented in Fig. 1(b)-(h). These ac-dc topologies, which areexamples of the bridgeless rectifier technology, have only twodevices conducting current in at least one of their currentconduction states. This characteristic can expressively enhancethe conduction loss performance in such systems especiallyfor power conversion levels above 1 kW. The circuits shownin Fig. 1(b)-(g) present a similar operating principle, indeedthe main difference is found in the implementation of thebidirectional four quadrant switch, i.e., the active switches Si,Aand Si,N with i = 1 or 2 in Fig. 1(b)-(d) are implemented witha single switch S1 in Fig. 1(e)-(g). The converter conceptsillustrated in Fig. 1(h) is recommended when aiming for highpower density. This circuit can be modulated in such a waythat the current ripple across the boost inductor displays twicethe frequency of the one achieved with the conventional circuitshown in Fig. 1(a) [3] for a given switching frequency. Hence,the required inductance to fulfill a maximum current rippledesign criteria for a given switching frequency will be halfthe value of the one necessary for the conventional system[18].

In this context, bridgeless PFC rectifiers are appropriatesolutions regarding conduction losses. However, the powersemiconductor devices in these converters must typically with-stand and commutate the full dc-link voltage and, thus, presentappreciable switching losses. To improve this characteristicand enable the use of higher switching frequencies, multilevelconverters can be employed to build PFC rectifier topologies.With this, the switched voltage steps are reduced and also theresulting switching losses.

This work presents new three-level unidirectional single-phase high power factor rectifier topologies that combinemany features of the bridgeless rectifiers shown in Fig. 1.The proposed converter topologies are shown in Fig. 2(d)-(i). The topologies shown in Fig. 2 present three distinctdc voltage levels per converter arm for controlling the input



2

(c)(b)

ig

A

N

D1,A

V+

o

D1,N

S2,AS2,N

vA,N

(h)

V+

oig

A

N

D1,A

DS1,ADS1,N

S1D1,N

D2,A

DS2,ADS2,N

S2D2,N

vA,N

(e)

V+

oig

A

N

D1,A

DS1,ADS1,N

S1

D1,N

D2,ADS2,ADS2,ND2,N

vA,N

(g)

V+

oig

A

N

D1,A

DS1,ADS1,N

S1D1,N

D2,AD2,N

vA,N

(f)

V+

oig

A

N

D1,AD1,N

D2,A

DS1,ADS1,N

S1D2,N

vA,N

V+

o

D1,N

D2,N

ig

A

N

vA,N

S1,A

S2,A

(d)

V+

oig

A

N

D1,AD1,N

1,N

D2,A

S 1,AS

D2,N

vA,N

(a)

A

N

C+

oSbvA,N v

p

n

o

io

ig

vg

Lb Db

Figure 1: Single-phase unidirectional PFC rectifiers: (a) conventional system; and bridgeless technology rectifiers: (b)-(c)standard version; (d)-(g) employing bidirectional four quadrant switch; and, (h) multiplying the effective switching frequencyacross the input inductor.

current, which not only leads to a substantial volume reductionof the boost inductor, but also to lower switching losseswhen compared to the conventional two-level PFC rectifiersdepicted in Fig. 1. In addition, the proposed converters canalso achieve lower conduction losses than the conventionalsystem (see Fig. 1(a)), as in some conduction states only twosemiconductor devices carry the inductor current and someof the semiconductors are rated for one half of the dc-linkvoltage. These characteristics make the new rectifiers well-suited for applications aiming for high efficiency and/or highpower density.

This paper is organized as follows. Initially, new multilevelunidirectional single-phase PFC rectifiers are introduced inSection II and compared with other well known systems.Additionally, the explanation of the structural characteristicsof a remarkable converter, including a suitable modulationstrategy and feedback control method, guaranteeing PFC op-eration, is presented. The analytical equations for calculatingthe power semiconductors stresses with dependency on theinput current amplitude and the voltage transfer ratio of theconverter are given in Section III. Finally, in Section IV, a 3-kW hardware prototype is designed to attest the feasibilityof the presented converter. Experimental results with suchprototype are presented including measured efficiency levels.

II. SINGLE-PHASE THREE-LEVEL BOOST-TYPE PFCRECTIFIERS

Known single-phase three-level1 boost-type rectifiers [19],[20], [32]–[45] are shown in Fig. 2(a)-2(c). Six new rectifiercircuits are proposed in Fig. 2(d)-2(i), where the dc-load plusthe dc-link capacitors are replaced by two dc voltages (Vo/2)and the single-phase power grid plus filters and ac-side boostinductor are replaced by bidirectional current sources (ig).These rectifier concepts are suitable solutions for increasingthe efficiency of wide input voltage range single-phase high

1This works considers the synthesizable number of voltage levels perconverter leg as the defining factor to define the number of levels of a staticconverter.

switching frequency PFC rectifiers because of the inherentvoltage doubling capability that is achieved through a propermodulation pattern.

The derivation of the topology shown in Fig. 2(d)-(i) canbe understood considering the single-phase three-level rectifiertopology depicted in Fig. 3. This can be seen as a variationof the circuit shown in Fig. 2(a) [19] or single-phase versionof a Vienna-type rectifier [46]. Redrawing this and integratingthe switching network composed of D1,N , D2,N , D1,A, D2,A,S1,N , S2,N , S1,A and S2,A leads to the topology shown inFig. 2(h), which has half the number of turn-off switches. Theother topologies are generated by replacing discrete diodes byMOSFETs in Fig. 2(h) or by changing or incorporating thebidirectional four quadrant switch across the terminal A andN.

As seen in the comparison characteristics compiled in Tab. Ithe new topologies present a lower number of semiconductorsin the current paths when compared with the conventionalthree-level circuits, i.e., the rectifiers in Fig. 2(a)–(c). Addition-ally, the proposed rectifiers avoid the use of selective switchesand allow low conduction losses for wide operation range.Furthermore, even though some of the semiconductors are tobe rated to withstand the full dc-link voltage, all commutationsoccur under half of the dc-link voltage. This leads to reducedswitching losses when compared to the converters in Fig. 1.

A relative cost analysis for the considered three-level rec-tifier is presented in the last row of Tab. I. This considersonly power semiconductor devices, boost inductor and dc-capacitors. The values were obtained from Digi-Key Cor-poration online in February 2014 considering the price for1000 pieces of each device according to the example givenin Tab. IV and normalized to the cost of the topology inFig. 2(b). Even though the number of semiconductors issubstantially increased for the proposed ac-dc converters whencompared to two-level solutions (see Fig. 1), these topologiesare indicated where very high efficiency and/or switchingfrequencies are required. As the circuits are symmetric andpresent reduced voltage steps, the generated CM voltages



3

(e)

V /2+ o

V /2+ o

igN

MP

A

D1,ADS1,A

DS1,N SMP,1

SAN

SMP,2

D1,N i ≥ 0o

D2,ADS2,A

DS2,N

D2,N

vA,N

(h) (i)

V /2+ o

V /2+ o

igN

MP

A

D1,ADS1,A

DS1,N SMP,1

SMP,2

D1,Ni ≥ 0o

D2,ADS2,A

DS2,N

D2,N

vA,N

V /2+ o

V /2+ o

ig

MP

D1,A

DS1,ADS1,N

SMP,2

SN SA

SMP,1

D1,N i ≥ 0o

D2,A

DS2,ADS2,N

D2,N

N AvA,N

V /2+ o

V /2+ o

ig

MP

D1,A

SMP,2

SMP,1

D1,Ni ≥ 0o

D2,A

DMP,ADMP,N

SN SAD2,N

N AvA,N

(g)

(a)

V /2+ o

V /2+ o

MPig

igig

ig ig

A

N

D1,AD1,N

D2,AD2,N

i ≥ 0o

vA,N

S1,A S2,AS1,N S2,N

(b)

V /2+

o

V /2+

o

MPig

A

N

D1,AD1,N

D2,AD2,N

i ≥ 0o

vA,N

S1

S2

D1

D2

(f)(d)

(c)

V /2+ o

V /2+ o

MPig

A

N

D1,AD1,N

D2,AD2,N

D4,AD4,N

D3,AD3,N

i ≥ 0o

vA,N

S1,A

S2,A

S1,N

S2,N

DS1,N

DS2,N

S2,A

S1,A

D1,A

SMP,2

SMP,1

SN SA

V /2o

V /2o

DS1,A

DS2,A

DS1,N

DS2,N

i ≥ 0o+

+

igN AvA,N

ig

MPD1,A

D1,N

V /2+ o

V /2+ o

ig

MP

D1,A

SMP,2

SMP,1

D1,Ni ≥ 0o

D2,AD2,N

N AvA,N

ig

Figure 2: Single-phase three-level boost-type PFC rectifiers: (a)-(c) conventional circuits; and (d)-(i) new topologies.

are reduced. The CM voltage steps are one quarter of thefull dc-link voltage in contrast to one half of the full dc-link voltage in typical two-level bridgeless rectifiers. Thepassive components losses are typically dominated by theboost inductor. With the three-level topologies these losses aretypically much lower since the voltage steps over the boostinductor are only one half of the dc-link voltage. Thus, theinductance and the size of the boost inductor are reduced.The circuits in Fig. 2(d)-(i) present redundant switching statesfor levels 0, ±Vo/2 that allows the distribution of lossesamong the turn off devices. Lower conduction losses can beachieved with the topologies in Fig. 2(d), (f), (g) and (i),where only two semiconductors are in the current path whileimposing the 0 level. From Tab. I, it can be observed thatthe topology depicted in Fig. 2(g) is a very promising PFCsolution due to lower conduction losses, and the lower numberof diodes and gate driver potentials. This circuit, which isredrawn in Fig. 4 to include the main passive components, isexplained and analyzed in the following sections. Finally, thetopology in Fig. 2(h) reduces the number of turn off devices

to only two at the expense of higher conduction losses duringthe level 0. This can be a much lower cost circuit sinceswitches SMP,1 and SMP,2 are rated for only half of the dc-link voltage. The rectifier in Fig. 2(i) is a hybrid option thatincorporates the proposed topology and a conventional two-level bridgeless converter. It can be assembled with D1,A andSN being exchanged by the gray devices. The disadvantages ofthe proposed topologies in comparison to two-levels bridgelessones are: the increased number of power semiconductors; thehigher number of isolated gate driver potentials; the increasedmodulation complexity due to the larger number of possibleswitching states; and the necessity of splitting the dc-linkcapacitance into two capacitors.

Comparing the rectifiers in Fig. 2(a)-(c) exemplarily withthe one proposed in Fig. 2(g) leads to the following con-clusions. The boost inductor ripple for a given switchingfrequency is also the same since the topologies in Fig. 2(a)-(c) and Fig. 2(g) can be modulated in a similar way and,thus, ideally apply a five-level voltage at the ac-side terminals.The same is valid for the dc-link capacitors current, i.e., the



4

Table I: Comparison of single-phase three-level PFC concepts.

Parameter TopologyFigure 2 (a) (b) (c) (d) (e) (f) (g) (h) (i)

Semiconductors in the current path to generate voltage level Vo = 0 4 4 4 2 3 2 2 4 2Semiconductors in the current path to generate voltage level ±V0/2 3 4 4 3 3 3 3 3 3

Semiconductors in the current path to generate voltage level ±V0 2 4 4 2 2 2 2 2 2Total number of MOSFETs 4 2 4 4 3 4 4 2 4

MOSFETs rated to Vo 0 0 0 2 1 2 2 0 2MOSFETs rated to Vo/2 4 2 4 2 2 2 2 2 2

Total number of diodes 4 6 8 6 8 8 6 8 6Diodes rated to Vo 4 4 0 6 8 8 6 8 6

Diodes rated to Vo/2 0 2 8 0 0 0 0 0 0Slow diodes 0 4 4 0 0 0 0 0 0Fast diodes 4 2 4 6 8 8 6 8 6

Diodes with reduced reverse recovery 4 2 4 4 4 4 4 4 2Gate drivers insulated potentials 2 2 3 3 2 3 2 2 3/4Power components relative cost 1.23 1.00 1.09 1.33 1.29 1.37 1.33 1.22 1.19

V /2+

o

V /2+

o

igN

MP

A

DA1SA1

SA2 DA2

DN1

DN2

S

Integrated to form the switching

network shown in Fig. 2(h)

N1

SN2

vA,N

ig

Figure 3: Single-phase three-level rectifier.

N1,D A1,D

N2,DA2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2oV

N,SD A,SD

MP

opC

onC

bL

gv

AN

NS

gi

oi

vo

v ≈op

2oV

v ≈on

MPi

Figure 4: New unidirectional high-efficiency multilevel single-phase bridgeless rectifier.

dc-side terminals currents are generated in the same way. Insummary, the external characteristics of these topologies areequivalent. However, the efficiency of the proposed topologytends to be higher since conduction losses will be lower. Thisreduction in conduction losses occurs because the proposedtopology presents less power semiconductors in the currentpath, except in the ±Vo states with the topology in Fig. 2(a),which is the same as the proposed PFC circuits. Switchinglosses are approximately unchanged if similar semiconductorsare employed. This is because all switching transitions in theproposed converter occur with just one half of the dc-linkvoltage.

A. Current Conduction States

The single-phase boost-type PFC rectifier depicted in Fig. 4utilizes four active switches (SA, SN , SMP,1 and SMP,2), and six

discrete diodes (DMP,N , DMP,A, D1,N , D1,A, D2,N and D2,A).Diodes D1,N , D1,A, D2,N and D2,A are fast-switched devices,i.e., will be required to commutate under current, while thediodes DMP,N and DMP,A and the body diodes of SN and SA areswitched off by SMP,1 and SMP,2 . Therefore, DMP,N and DMP,Acan be implemented with standard fast or ultrafast silicondiodes with relatively low forward voltage drop, while the fourbridge diodes would benefit from SiC or GaN semiconductortechnology. The intrinsic diodes of the MOSFETs SA and SN(DS,A and DS,N) are used in the circuit operation and can profitfrom the low forward voltage drop body diode characteristicsof super junction MOSFETs. Interestingly, the switches SA, SNand SMP,1 have the same reference for their gate command,which simplifies and reduces the cost of isolated gate drivecircuits. As illustrated in Fig. 4, the dc-link is constructedwith two series connected capacitors that allow the formationof five voltage levels across the terminals A and N (vA,N = 0,±Vo/2, or ±Vo). Fig. 5 and Fig. 6 show the rectifier currentconduction states for positive and negative input currents, iLb,respectively. There are two redundant switching states for theformation of vAN = ±Vo/2 (states 2 and 3), which resultsin different current iMP direction across the midpoint MP ofthe output capacitors Cop and Con. Hence, this feature can beused for balancing the voltages across the dc-link capacitors.Enabling SMP,1 (see Fig. 5(b)) charges Cop and discharges Con,while the opposite occurs if SMP,2 conducts. For improvedconduction losses while implementing the state vA,N = 0 (seeFig. 5(a) and Fig. 6(a)), the switches SMP,1 and SMP2 couldalso be turned on together with SA and SN . In this case, twoparallel paths across the semiconductors are created for theimpressed current. Alternativelly, the state vA,N = 0 could alsobe implemented by solely turning on SMP,1 and SMP,2, whileall the remaining active devices are switched off.

B. PWM Modulation Strategy and Feedback Control SchemeA suitable feedback control scheme able to regulate the

output voltage of the proposed converter, vo, and shape theac-side current iLb, is presented in Fig. 7. Therein, a slowouter control loop is used to regulate the output voltage vo toa constant reference voltage vo* and to generate a referencesignal iLb* for the fast inner current control loop with similarwaveform shape of the rectified input voltage vg. Additionally,



5

State 2:2oV=ANv = 0sel,MPS

State 4: oV=ANvState 3:2oV=ANv = 1sel,MPS

(b)

(d)

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

State 1: = 0ANv

(a)

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

(c)

Figure 5: Rectifier current conduction states for iLb > 0: (a) vA,N = 0; (b) and (c) vA,N = Vo/2; or (d) vA,N = Vo. Note thatthe state vA,N = 0 could also be implemented by solely turning on SMP,1 and SMP,2, while all the remaining active devices areswitched off.

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

(c)

State 2:2o-V=ANv = 0sel,MPS

State 4: o-V=ANvState 3:2o-V=ANv = 1sel,MPS

(b)

(d)

N1,DA1,D

N2,D A2,D

A,MPDN,MPD

,2MPS

,1MPS

AS

2

oV

2

oVN,SD A,SD

MP

oV

+

−oR

opC

onC

gv

AN

Lbi

NS

+−

Lbv +−

MPi

+

State 1: = 0ANv

(a)

Figure 6: Rectifier current conduction states for iLb < 0: (a) vA,N = 0; (b) and (c) vA,N =−Vo/2; or (d) vA,N =−Vo. Note thatthe state vA,N = 0 could also be implemented by solely turning on SMP,1 and SMP,2, while all the remaining active devices areswitched off.



6

sel,MPs

,1MPs

,2MPs

NsANs

MPs

opv

gv

ov *

ov *

ovLbi

Lbi *

onv

m

+

−

MPc +

−

ANc +

−

As

IC (s)UC (s)

|x|

|x|

Figure 7: Appropriate feedback control scheme and PWMmodulator circuit.

,1MPs,2MPs

Ns,As Ns,As

,2MPs ,1MPs ,2MPs

0.00

0.50

1.00

oV0.5

oV

0t

sT

)t(m

tsel,MPs

anV

ANs

MPs

1 2 3 41 2 4 43

)t(ANc

)t(MPc

sT·ANd sT·MPd

t

t

t

t

t

Figure 8: Suggested PWM modulation scheme. Note that foreach switching transition the respective active conduction stateis shown.

a logic signal SMP,sel is used to guide the selection of theredundant current conduction state (state 2 and 3) in orderto balance the partial dc-link voltages, vop and von. The gatecommands for SA, SN , SMP,1 and SMP,2 are guided by the logicsignals sAN and sMP which are generated by comparing thefeedback control signal m with the two interleaved triangularcarriers cAN and cMP. Carriers cAN and cMP are particularlyarranged as shown in Fig. 8.

In the proposed PWM modulator, the transition of the signalsMP,sel is synchronized with the peak of cAN in order to reducethe switching losses across SMP,1 and SMP,2 for m < 1/2. Inthis case, due to the 180 phase-shift between cAN and cMP thetransition between states 2 and 3 occurs after passing throughan intermediate state (state 1), ensuring the commutation ofSMP,1 and SMP,2 under zero current. Although it is possibleto set the converter operation vA,N = 0 by solely switchingSA when iLb is positive or by only gating SN for negativeiLb, these switches are always simultaneously commanded inthe suggested scheme, following the comparison between mand cAN . This logic reduces the conduction losses across the

MOSFETs SA and SN (see Fig. 5(a) and Fig. 6(a)) and alsosimplifies their command circuits. As a result of the suggestedPWM modulator, the duty cycle of SAN and SMP will be givenby

dAN =

1−2m if m≤ 1/20 if m > 1/2 , (1)

which leads to a modulated ac terminal voltage vA,N with atime averaged value within a switching period, Ts, equals

〈vA,N〉Ts= m · 〈vo〉Ts

= m ·Vo. (2)

Considering that the system is fed by a sinusoidal input voltagevg with an amplitude value of Vgp,

vg =Vgp · sin(ωgt) (3)

high power factor operation, where iLb has sinusoidal shapein-phase with vg,

iLb = Igp · sin(ωgt) (4)

and also a negligible voltage drop across Lb at the gridfrequency, the instantaneous terminal voltage value can beapproximated by

vA,N = vg− vLb = vg−Lb ·ddt

iLb, (5)

vA,N =Vgp · sin(ωgt)−ωg ·Lb ·Vgp · cos(ωgt)︸︷︷︸≈0

(6)

vA,N ≈ vg =Vgp · sin(ωgt) = m ·Vo. (7)

Hence, assuming steady state conditions, high power factoroperation and low voltage drop at the mains frequency overthe boost inductor the PWM modulation signal m will be givenby

m =Vgp

Vo· sin(ωgt) , (8)

which, combined with (1) and (2), leads to the duty cyclefunctions for SAN and SMP as follows

dAN =

1− 2Vgp

Vo· sin(ωgt) if |vg| ≤ Vo

20 if |vg|> Vo

2

(9)

dMP =

1 if |vg| ≤ Vo

22− 2Vgp

Vo· sin(ωgt) if |vg|> Vo

2(10)

Fig. 9 illustrates the main waveforms for rectifier operationduring one grid period. Therein, two distinctive converteroperating regions can be observed:• |vg| ≤Vo/2: the system will alternate between the voltage

levels |vA,N |= 0 and |vA,N |=Vo/2 (switching states 1, 2and 3);

• |vg| > Vo/2: the system will operate with the voltagelevels |vA,N |=Vo/2 and |vA,N |=Vo (states 2, 3 and 4).

Note that the angles θ1 and θ2, given in (12), delimit theboundary between these two operating regions:

θ1 = arcsin(

V0

2Vgp

)(11)



7

anv

gi

gv

ANc

m MPc

MPd

ANd

2

oV>gv 2

oV≤gv

0.0

1.0

0.5

0.0

1.0

0.5

oV1.0

oV0.5

0.0

oV1.0−

oV0.5−

π2

π

2

π3 π21θ 2θtgω

tgω

tgω

Figure 9: Idealized main rectifier waveforms for high powerfactor operation.

and

θ2 = π− arcsin(

V0

2Vgp

). (12)

III. PFC RECTIFIER DESIGN GUIDELINES

In this section, means for determining the current andvoltage stresses of the active and passive components of theproposed single-phase PFC rectifier depicted in Fig. 2(g),are given. In order to allow estimation of the converter on-state losses, the current rms and average values have to becalculated. Therefore, simple analytical approximations withdependence on the system operating parameters are derived.For the following calculations, it is assumed that the rectifierpresents: sinusoidal ac-side current; ohmic fundamental gridbehavior; a constant dc voltage Vo; no low-frequency voltagedrop across the inductor Lb; and a switching frequency, fs,which is much higher than the grid frequency fg ( fs fg).

A. Semiconductor Voltage and Current Stresses

The voltage stress on the switches SMP,1 and SMP,2 isdefined by the partial dc-link voltages, which ideally is Vo/2.All the remaining semiconductors (D1,N , D1,A, D2,N , D2,A,DMP,N , DMP,A, SA/DS,A and SN /DS,N ) have to block the fulloutput voltage Vo. The average and rms current values for thetransistors and diodes can be determined as given in (8)-(24).Therein, the analytical calculations for SA/DS,A and SN /DS,Nconsider that during vA,N = 0 the current iLb is not sharedbetween these devices, as it would be for MOSFETs (see Fig. 5

and Fig. 6).

M =Vgp

Vo(13)

β =

√4− 1

M2 (14)

ID1/2AN,avg =IgpM

4(15)

ID1/2AN ,rms = Igp

√2M3π

(16)

IDSAN ,avg = Igp

[1π− M

4

](17)

IDSAN ,rms = Igp

√14− 2M

3π(18)

ISAN ,avg =

Igp[ 1

π− M

2

]if M ≤ 1

2Igpπ

[1− β

4 −Mθ1

]if M > 1

2(19)

ISAN ,rms =

Igp

√14 −

4M3π

if M ≤ 12

Igp

√1π

[β( 2M

3 −1

24M

)− 4M

3 + θ12

]if M > 1

2

(20)

ISMP,avg =

IgpM2 if M ≤ 1

2

Igp

[β

2π+ 2Mθ1

π− M

2

]if M > 1

2(21)

ISMP,rms =

Igp

√4M3π

if M ≤ 12

Igp

√1π

[β( 1

12M −4M3

)+ 4M

3 −θ1]+ 1

2 if M > 12(22)

IDMP,avg =

IgpM4 if M ≤ 1

2

Igp

[β

4π+ Mθ1

π− M

4

]if M > 1

2(23)

IDMP,rms =

Igp

√2M3π

if M ≤ 12

Igp

√1π

[β( 1

24M −2M3

)+ 2M

3 −θ12

]+ 1

4 if M > 12

.

(24)

The current efforts obtained with (8)-(24) are shown graph-ically in Fig. 10, as a function of the modulation index M andnormalized according to the input current peak and the outputcurrent. This second normalization procedure shows how thecurrent efforts vary for fixed output voltage and power. Thishappens with the variation of the ac voltage in a given powerlevel and is very meaningful for the operation of PFC rectifiers.

B. Frequency spectra

The five-level ac-side voltage vAN , also known as therectifier differential mode voltage (DM), for the proposedmodulation strategy is defined by

vAN = VoM cos(θg)+2Voπ

∞

∑m=1

[1

2m

∞

∑n=−∞

J2n+1 (2mπM) ·

·cos(nπ)cos [mθc +(2n+1)θg]],

(25)from where the amplitudes of the frequency harmonics can befound.



8

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.30

0.25

0.20

0.15

0.10

0.05

0.00

M

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0M

MPSI

ANSI

MPDI

DbIDsIDsI

0.50

0.40

0.30

0.20

0.10

0.00

rms,MPSI

1.75

1.00

0.75

0.50

0.25

0.00

3.00

2.00

1.50

0.50

0.000.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

M

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0M

1.00

1.25

1.50

2.50

rms,MPDI

rms,bDI

rms,ANSI

rms,DsI

(a)

(b)

(c)

(d)

MPSI

DbI

ANSI MPDI

rms,DsI

rms,ANSI

rms,MPDI

rms,MPSI

rms,bDI

Figure 10: Semiconductor current efforts as functions of the modulation index M and normalized: (a)–(b) with respect to theinput current peak Igp; and, (c)–(d) with respect to the output current, given by Po/Vo.

The common mode voltage of the proposed rectifier is givenby

vCM =vA,MP + vN,MP

2, (26)

which finally results in

vCM = 4Voπ2

∞

∑m=1

1

2m−1

∞

∑k=1

[J2k−1(2m−1)πm

(2k−1)

]cos[( 2m−1

2

)θc]

+

+ 4Voπ2

∞

∑m=1

12m−1

∞

∑n=−∞n6=0

∞

∑k=1

[J2k−1[(2m−1)πm](2k−1)cos(nπ)

(2k−1+2n)(2k−1−2n)

]·

·cos[( 2m−1

2

)θc +2nθg

],

(27)where θc = 2π fst and θg = 2π fgt are the instantaneous phaseangles of the modulation carrier and the grid voltage, respec-tively.

Fig. 11 shows the DM and CM voltages comparison of theproposed rectifier with the conventional two-level boost PFCrectifier (see Fig. 1(a)) and the bridgeless rectifier depicted inFig. 1(b). As shown in Fig. 11(b) and (27) the first harmonicgroup of the CM voltage appears at fs/2. The proposedthree-level PFC rectifier presents reduced spectra amplitudesand, thus, leads to smaller EMC filter components for, both,CM and DM when compared to the bridgeless rectifier. Itsconducted emissions generation performance in this regard iscomparable to that of an interleaved bridgeless PFC converterwith the advantage of using a single inductor. On the otherhand, the proposed topology might present higher CM voltagethan the conventional boost rectifier (see Fig. 1(a)) since it, asin the case of the bridgeless, does not feature the negativepoint of the line being always connected to the negative dcbus through some rectification diode. The final CM noisepaths will strongly depend on the parasitic elements of thecircuit and the analysis of CM spectra presents only part ofthe required analysis. The proposed topology will typicallypresent a larger CM filter and a smaller DM filter than theconventional PFC rectifier shown in Fig. 1(a).

0.150

0.125

0.050

0.000π

2

π0

4

π4

π3

0.100

0.025

0.075

Lb

i∆

tgθ

= 1M

= 0.89M

= 0.82M

= 0.47M

= 0.37M

Figure 12: Boost inductor current ripple as a function of theac voltage phase angle for different modulation indexes.

C. Boost Inductor Current Ripple

The normalized boost inductor current ripple, is defined by

∆iLb =

M sin(θg)−2M2sin2 (θg) if sin(θg)≤ 1

2M3M sin(θg)−2M2sin2 (θg)−1 if sin(θg)>

12M

(28)and is graphically shown in Fig. 12 for different modulationindexes M and as a function of the phase angle θg, where

∆iLb =∆iLb Lb fs

Vo. (29)

Therefore, the boost inductance can be defined as

Lb ≥Vo ∆iLb

Lb fs. (30)

D. Passive Components: Current Stresses

The maximum current ripple value of the inductor Lb,∆iLb,max, can be found with the maxima in (28). It is deter-



9

2-L bridgeless DM envelope2-L conventional DM envelope



Bri

dgel

ess

Bri

dgel

ess

3-L

bri

dgel

ess

3-L

bri

dgel

ess

2-L bridgeless CM envelope2-L conventional CM envelope

fsfs

2

fs2 fs3 fs4 fs5fs

23 fs

25 fs

27 fs

29

Frequency

fsfs

2

fs2 fs3 fs4 fs5fs

23 fs

25 fs

27 fs

29

Frequency

fsfs

2

fs2 fs3 fs4 fs5fs

23 fs

25 fs

27 fs

29

Frequency

0.1

0.01

0.02

0.2D

M v

olt

age

[p.u

.]

0.1

0.01

0.02

0.2

CM

volt

age

[p.u

.]

(a)

(b)

2-L

conve

nti

onal

2-L

conve

nti

onal



Figure 11: Voltage spectra for two- and three-level bridgeless PFC rectifiers: (a) differential mode voltage spectrum; and, (b)common mode voltage spectrum, i.e., the spectrum of vCM = (vA,MP + vN,MP)/2, spectrum. All results are normalized basedon the output voltage Vo.

mined by

∆iLb,max =

18 ·

VoLb· fs if M ≥ 1

4M·(Vo−2Vgp)

Lb· fs if M < 14

(31)

The rms value of the output capacitor current ICo,rms is givenby

ICo,rms = Igp ·√

4M3π− M2

4. (32)

In steady-state conditions, the output capacitor current iscomposed of low and high frequency components. Thesecurrent components are given by

ICo,l f =1√2

VgpIgp

2Vo, (33)

ICo,h f =√

ICo,rms2− ICo,l f

2 (34)

and are shown in Fig. 13 as a function of the modulation indexM.

E. Dc-link Voltage Ripple

The peak-to-peak value of the output voltage ripple ∆vco,maxis

∆vCo,max =Po (Cop +Con)

2π · fg ·Vo ·Cop ·Con, (35)

while each half of the dc-link presents one half of this value,i.e.,

∆vop,max = ∆von,max =∆vCo,max

2. (36)

Thus, the dc-link capacitance values can be chosen accordingto

Cop =Con ≥Po

π fg Vo ∆vCo,max. (37)

Co, rmsI

M0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.50

0.40

0.30

0.20

0.10

0.00

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

2.50

2.00

1.50

0.50

0.00

M

1.00 lf,CoIhf,CoI

rms,CoI

lf,CoIhf,CoI(a)

(b)

Figure 13: Normalized output capacitor current componentsas a function of the modulation index M: (a) normalizationaccording to the input current peak and; (b) from the outputcurrent given by Po/Vo.

F. Rectifier Current Stresses Model Accuracy

In order to verify the accuracy of the derived equations mod-eling the stresses of the studied rectifier devices, an appropriateswitching frequency and suitable components for the projectspecification given in Tab. II have been selected. A switchingfrequency of fs = 140 kHz is designated as it constitutes agood compromise between high efficiency, high power density,and high control bandwidth. Advantageously, the switchingfrequency is found near, but still below the beginning ofthe considered EMC conducted emissions measurement rangestarting at 150 kHz. With fs = 140 kHz, the values for the



10

Table II: Unidirectional single-phase PFC rectifier prototypespecification.

Specification ValueInput phase rms voltage Vg 220 V ±15%Output voltage Vo 380 VGrid fg and switching frequency fs 60 Hz / 140 kHzRated output power Po 3 kWMax. output voltage ripple ∆vCo,max 5 %Max. inductor current ripple ∆iLb,max 20 %

input inductor of Lb = 96.5 µH (∆iLb,max ≈ 18.3% · Igp) andCop = Con = 3000 µF (∆vCo,pp ≈ 3.7% ·Vo) are selected for theverification of the derived models. In Tab. III, the values ofthe average and rms component stresses calculated with therespective expressions are compared to the results obtainedwith a circuit simulator and show very good agreement.

Table III: Comparison of active and passive componentstresses determined by analytical calculations and simulations.

Analytical calc. Simulation results Deviation [%]ISAN,avg 0.41 0.41 0.0ISAN,rms 1.57 1.60 +1.9ISMP,avg 3.57 3.60 +0.84ISMP,rms 7.20 7.22 +0.27IDMP,avg 1.79 1.80 +0.56IDMP,rms 5.09 5.10 +0.19IDSAN,avg 2.19 2.24 +2.28IDSAN,rms 5.325 5.37 +0.75

ID1/2AN,avg 3.95 3.89 -1.52ID1/2AN,rms 8.04 7.94 -1.24

ICo,rms 8.18 8.10 -0.98∆iLb,max 3.52 3.42 -2.84∆vCo,max 13.96 13.62 -2.43

Table IV: Main components of the 3-kW three-level unidirec-tional single-phase PFC rectifier prototype (see Fig. 15 andFig. 16).

Component Device DescriptionDSP Texas Instruments TMS320F28027

D1,N/A, D2,N/A SiC Schottky diodes SCS112AG, RohmDMP,N , DMP,A, Si diodes RURP3060, Fairchild

SA/DS,A, SN /DS,N CoolMOSTM IPP60R099CP, InfineonSMP,1, SMP,2 STripFETTM Power Mosfet STW75NF30, ST

Lb 96.5 µH @ 140 kHz,APH40P60 core, 44 turns, 4 x AWG18 Cu wire

L f 2.4 mH JW Miller 8120-RCCop, Con 2x 1.5mF / 250 V, Panasonic EET-HC2E152EA

C f 2 x 470 nFCd 470 nFRd Damping resistor of 56 Ω

Gate Driver FOD 3180

G. Efficiency comparison

An efficiency comparison involving the topologies shown inFig. 2(g) (a three-level bridgeless) and Fig. 1(b) (a two-levelbridgeless) is presented here, while considering the followingdevices• Fast switching diodes (D1,N/A, D2,N/A): SiC diodes

SCS112AG, Rohm;• 600-V MOSFETs (SA, SN , S2,A, S2,N): Si CoolMOS

IPP60R099CP, Infineon;

0 30 60 90 120 150 180 210 240 270 30095

96

97

98

99

100

0

20

40

60

80

100

Switching frequency [kHz]

Effic

iency

[%

]

Loss

es [W

]

2L bridgeless eff.

2L bridgeless eff. (2 parallel MOSFETs)

3L bridgeless eff.

2L bridgeless losses

3L bridgeless losses

Figure 14: Efficiency and power semiconductor losses com-parison between the proposed topology (3L bridgeless) and atwo-level bridgeless (2L bridgeless) according to Fig. 1(b).A second efficiency curve for the 2L bridgeless is shownconsidering that two 600-V CoolMOS devices are used inparallel in each turn-off device and, thus, the total siliconarea becomes more similar. The MOSFET parameters in thiscase are adjusted to half the resistance values and doublethe capacitance values. All curves do not consider passivecomponents losses and signal electronics consumption.

• 300-V MOSFETs (SMP,1, SMP,2): Si Mosfet STW75NF30,ST;

• Diodes in series with MOSFETs (DMP,A, DMP,N): Sidiodes RURP3060, Fairchild.

The comparison does not include the passive componentslosses and it is assumed that no reverse recovery occurs.The rms value of the input voltage is 220 V, frequency is60 Hz, output voltage is 380 V and the output power is 3 kW.The switching losses are computed based on the switchingtimes calculations with the method presented in [47]. Theconduction losses assume that the diodes can be representedwith a constant forward voltage drop VTO in series witha resistance rT , while the MOSFETs are modeled with aconstant resistance Rc. The following devices parameters areadopted:• Fast switching diodes (D1,N/A, D2,N/A): VTO = 1.0 V; rT =

43 mΩ.• 600-V MOSFETs (SA, SN , S2,A, S2,N): Rc = 175 mΩ; anti-

parallel diode VTO = 0.75 V and rT = 30 mΩ; total gateresistance Rg = (8.2+1.3) Ω; gate-to-source capacitanceCgs = 2.74 nF; gate-to-drain capacitance Cgd = 60 pF;drain-to-source capacitance Cds = 280 pF; threshold volt-age VGS(th) = 3 V; pinch-off voltage Vp = 5 V; gate drivervoltage VG = 15 V.

• 300-V MOSFETs (SMP,1, SMP,2): Rc = 64.8 mΩ; Rg =(8.2 + 1.55) Ω; Cgs = 5.82 nF; Cgd = 110 pF; Cds =352 pF; VGS(th) = 3 V; Vp = 5 V; VG = 15 V.

• Diodes in series with MOSFETs (DMP,A, DMP,N): VTO =0.6 V and rT = 23 mΩ.

Fig. 14 shows the computed power semiconductor losses.The two-level bridgeless presents lower losses at low switchingfrequencies. This can be further improved with the use of twoparallel MOSFETs per turnoff device to achieve efficiencylevels close to 99%. This figure is not achievable with the pro-posed topology. In summary, the two-level bridgeless presents



11

Input

Filter

+

−

oR ov

opv

onv

As Ns

,1MP

s

,2MP

s

4

bL

4

bL

a

n

gv

Signal Conditioning Drivers

opv onv

ADC ePWM

Aquisition

Control

ModulatorDSC

omvgv

opv

onvLbi

sel,MPs ANd MPd

m

Hardware

DSC Peripherals

Software

dR

dCfCGrid Converter

fL

(a)

(b)

Figure 15: (a) Circuit diagram of the multilevel unidirectionalsingle-phase PFC rectifier prototype; and (b) input filter.

Boost inductor

EMC filter

Control circuits

DC-bus capacitors

Heat sinks

Semiconductors

310 mm

140

mm

44 m

m

Figure 16: Implemented 3-kW multilevel unidirectional single-phase PFC rectifier prototype.

lower conduction losses. However, as the switching frequencyrises, the efficiency of the three-level bridgeless is not asaffected and from approximately 80 kHz on the proposedtopology produces lower total losses. This would be morepronounced if the boost inductor and EMC filter elements wereconsidered.

IV. EXPERIMENTAL EVALUATION

A 3-kW hardware prototype of the proposed unidirectionalsingle-phase PFC rectifier according to the specifications givenin Tab. II and feedback control scheme depicted in Fig. 7 hasbeen built. The circuit diagram and the implemented prototypeare shown in Fig. 15 and Fig. 16, respectively. A list of theemployed semiconductor devices and passive components isgiven in Tab. IV.

81.0 °C

89.5 °C

55.2 °C 43.4 °C

47.2 °C

C25 C90

61.8 °C

bL

fL

66.0 °C

,2MPS ,1MPS

A1,D

A2,D N1,D

N2,D

A,MPD N,MPD

ASNS

61

,0 °

C

C= 29ambT= 3010WoP

Figure 18: Prototype measured temperatures while operatingat rated power and input voltage Vg = 187 V.

The main waveforms obtained with the designed prototypeoperating at rated power (Po ≈ 3 kW) are presented in Fig. 17.For comparison purposes, the results presented in Fig. 17(a)are shown with the waveforms obtained in a circuit simulator(see Fig. 17(b)), and show very good correspondence. Theobserved dc-link voltage ripple is below 4% closely matchingthe theoretical findings. The boost inductor maximum currentripple also agrees with the derived design expressions, wherethe maximum measured ripple is approximately 3.6 A. Theformation of five voltage levels in vA,N is observed. Thefiltered input current drained from the grid ig is shown inFig. 17(c). Therein, it can be observed that the input voltagedistortion near the peak of the vg waveform appears as wellas in the input current ig. This is due to the resistive behavioremulated by the designed converter. The voltages across theMOSFETs are presented in Fig. 17(d), where it is noted thatall commutations occur with a voltage level equivalent to halfthe output voltage, even at the switches that need to block thefull dc-link voltage. This produces low switching losses.

Fig. 18 shows the prototype temperature distribution mea-sured with thermal camera FLIR SC655 at an ambient tem-perature (Tamb) of 29 C. The measurements are taken forthe prototype operating at nominal power (Po ≈ 3 kW) andminimal input voltage rms value (Vg = 187 V) as it constitutesthe most critical scenario regarding the converter power lossesand, consequently it is the case where the highest thermalstress across the power elements are generated.

Fig. 19 presents the dynamic performance of the proposedfeedback control tested with the converter operating at Vg =220 V (rms) for two resistive load steps: from 40% to 100%Po (see Fig. 19(a)) and from 100% to 40% Po (see Fig. 19(b)).The output voltage could be efficiently regulated in both tests.Fig. 20 shows the harmonic analysis of the converter inputcurrent ig in comparison with the limits of the IEC 61000-3-2 standard for class A equipment. The standard limits havebeen met for the measured load conditions. The hardwarepower efficiency (η), input current THD and power factor(λ) as functions of the output power have been measuredwith a Yokogawa WT3000 power analyzer and the results areshown in Fig. 21. Considering the relatively high switchingfrequency of fs = 140 kHz for a 3-kW rectifier, a remarkable



12

)t(gv)t(ov

)t(anv

)t(Lbi

390

37040

-40

20

-20

0

400

-400

200

-200

0

0.34 0.35 0.36 0.37Time [s]

)t(Lbi

)t(ov

)t(anv

10

)t(gv

)t(gv)t(ov

)t(anv

)t(gi

(a) (b)

(c) (d)

)t(1Smpv

)t(2Smpv

)t(Sav

)t(Snv

Figure 17: Main waveforms: (a) measured output voltage vo (50 V/div), rectifier input current iLb (10 A/div), grid voltagevg (100 V/div), and multilevel voltage vA,N at the converter input terminals (200 V/div); (b) main waveforms obtained witha circuit simulator; (c) measured output voltage vo (50 V/div), grid current ig (10 A/div), grid voltage vg (100 V/div), andmultilevel voltage vA,N at the converter input terminals (200 V/div); and, (d) measured voltages across SA vSa (200 V/div), SNvSn (200 V/div), SMP,2 vSmp2 (100 V/div) and SMP,1 vSmp1 (100 V/div).

maximum efficiency of 98.6% at partial load (≈35% Po) and,advantageously, a relatively flat efficiency curve are obtained.From 10% to 100% of Po the measured efficiency is foundbetween the range of 98.0% and 98.6%. Additionally, theresults show a high power quality of the input current, i.e.,at full power a high power factor (λ≈ 0.99) and a low inputcurrent THD (THDi ≈ 2.18%) have been measured. Finally,the experimental results attest that the proposed multilevel PFCrectifier is a very attractive solution for applications in single-phase power supplies targeting for high efficiency, high linepower quality and high power density.

V. CONCLUSIONS

Multilevel high efficiency unidirectional single-phase three-level PFC rectifier topologies well-suited for applicationsaiming for high efficiency and/or high power density have beenproposed in this work. Even though most power semiconduc-

tors block the full dc-link voltage, all switching transitionsoccur with only half of the dc-link voltage. Thus, the pro-posed concepts present low switching losses when comparedto conventional two-level bridgeless rectifiers. In addition, asimple to manufacture and small volume are characteristicsof the required boost inductor. This leads to manufacturingcost advantages when comparing the proposed systems tointerleaved converters. More importantly, the new convertersfeature similar switching loss performance, but lower con-duction losses when compared to state-of-the-art three-levelrectifier topologies. In fact, as for the conventional three-levelPFCs, the main disadvantages related to two-level topologiesare the increased number of semiconductors, isolated gatedrivers and the inherit higher control complexity.

For a selected rectifier, the principle of operation, the maindesign expressions, suitable modulation scheme and PWMcontrol have been described. It has been shown that this



13

gi

gv

ov

gi

gv

ov

(a)

(b)

Figure 19: Load step: (a) from 40% to 100% Po and (b) from100% to 40% Po.

converter has reduced EMC filter requirements when com-pared to a conventional bridgeless topology. Additionally, theDM filter requirement is also reduced when compared to aconventional boost PFC rectifier, but the need of a larger CMfilter is likely. Finally, in order to verify some advantages ofthe exemplary PFC circuit, the system has been designed and a3-kW hardware prototype has been constructed and tested. Ata switching frequency of 140 kHz, rated power and nominalinput voltage a power efficiency of 98% and an input currentTHD of 2.18% have been measured, attesting the advantagesof the proposed rectifier concept.

REFERENCES

[1] D. M. Michell, “Ac-dc converter having an improved power factor,”U.S.A. Patent U.S. 4 412 277, 1983.

[2] A. de Souza and I. Barbi, “High power factor rectifier with reducedconduction and commutation losses,” in Telecommunication EnergyConference, 1999. INTELEC ’99. The 21st International, 1999, pp. 5pp.–.

[3] M. Heldwein, M. Ortmann, and S. Mussa, “Single-phase pwm boost-type unidirectional rectifier doubling the switching frequency,” in PowerElectronics and Applications, 2009. EPE ’09. 13th European Conferenceon, 2009, pp. 1–10.

Current harmonic (n)


(a)

2.5

2.0

1.0

0.0

1.5

0.5

Am

plitu

de [A

]

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39


2.5

2.0

1.0

0.0

1.5

0.5

Am

plitu

de [A

]

2.5

2.0

1.0

0.0

1.5

0.5

Am

plitu

de [A

](b)

(c)

Class A

Experimental

Class A

Experimental

Class A

Experimental

= 3012WoP

= 1221WoP

= 608WoP

)t(gi

)t(gv

)t(gi

)t(gv

)t(gi

)t(gv

100 V/div10 A/div5 ms/div



= 2.18%iTHD

= 3.12%iTHD

= 6.62%iTHD

Figure 20: Input current harmonic analysis for: (a) rated poweroutput power Po; (b) 40% Po; and (c) 20% Po. Measurementconditions with a grid voltage THD of approximately 1.9%.

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14

96

97

98

99

Rated output power [% of Po]



Po

wer

Eff

icie

ncy

[%

]

1.00

0.98

0.96

0.94

Po

wer

Fac

tor

10020 40 60 8000

10 30 50 70 90

10020 40 60 800 10 30 50 70 90

10020 40 60 800 10 30 50 70 90

20

15

10

5

25

30

iT

HD

[

%]

Vg =187 V (rms)

Vg = 220 V (rms)

(a)

(b)

(c)

Figure 21: Prototype measured: (a) power efficiency for dif-ferent input voltages (Vg = 220 V and 187 V rms); (b) powerfactor for Vg = 220V rms; and (c) input current THDi forVg = 220 V rms as functions of the rated output power.

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Andre De Bastiani Lange received the B.S. degreesin electrical engineering from the Federal Universityof Rio Grande do Sul (UFRGS), Porto Alegre,Brazil, in 2010 and M.S. degree in electrical engi-neering from the Federal University of Santa Cata-rina (UFSC), Florianpolis, Brazil, in 2012. Duringthe Master studies at the Power Electronics Institute(INEP) of the Federal University of Santa Catarina(UFSC), Florianpolis, Brazil, his research topicsincluded power factor correction, boost convertercontrol techniques and inductor design optimization.

He is currently at the Power System Operation Department of CentraisEltricas de Santa Catarina (CELESC) and his research interests include PowerElectronics and Power Distribution.

Marcio Silveira Ortmann (S’09-M’13) was born inSanto Angelo, Brazil, in 1981. He received the B.Sc.degree in electrical engineering from the NorthwestRegional University of the Rio Grande do Sul State,Ijuı, Brazil, in 2006 and the M.S. and Ph.D. degreesin electrical engineering from the Federal Universityof Santa Catarina (UFSC), Florianopolis, Brazil,in 2008 and 2012, respectively. He is currently aPostdoctoral Researcher at the Power Electronics In-stitute (INEP), Federal University of Santa Catarina. His research interests include PFC rectifiers, digital

control in power electronics, active filters and power electronics for renewableenergy sources.

Mr. Ortmann is a student member of the Brazilian Power Electronic Society(SOBRAEP).

Thiago Batista Soeiro (S10-A11) received the B.S.(Hons.) and M.S. degrees in electrical engineeringfrom the Federal University of Santa Catarina, Flori-anopolis, Brazil, in 2004 and 2007, respectively, andthe Ph.D. degree from the Swiss Federal Instituteof Technology (ETH) Zurich, Zurich,Switzerland, in2012. During the Master and Ph.D studies he was avisiting scholar at the Power Electronics and EnergyResearch Group at Concordia University, Montreal,Canada and at the Center for Power ElectronicsSystems, Blacksburg, USA, respectively. From 2012

to 2013 he was a researcher at the Power Electronics Institute (INEP) of theFederal University of Santa Catarina (UFSC), Florianpolis, Brazil.

He is currently with the Corporate Research of ABB Switzerland. Hisresearch interests include power factor correction techniques and advancedpower converters.

Marcelo Lobo Heldwein (S’99-M’08-SM’13) re-ceived the B.S. and M.S. degrees in electricalengineering from the Federal University of SantaCatarina (UFSC), Florianopolis, Brazil, in 1997 and1999, respectively, and his Ph.D. degree from theSwiss Federal Institute of Technology (ETH Zurich),Zurich, Switzerland, in 2007.

He is currently an Adjunct Professor with theElectronics and Electrical Engineering Departmentat the UFSC.

From 1999 to 2003, he worked with industry,including research at the Power Electronics Institute, Brazil and EmersonNetwork Power, Brazil and Sweden. He was a Postdoctoral Fellow at theETH Zurich and at the UFSC from 2007 to 2009. Dr. Heldwein is a memberof the Brazilian Power Electronic Society (SOBRAEP).

His research interests include Power Electronics, Advanced Power Distri-bution and Electromagnetic Compatibility.

Documents

Three-Level Single-Phase Bridgeless PFC Rectifiers