Thumb Data Processing Instructions and Breakpoint Instructions

02/18/2015

Mingliang GeYi (Leo) Wu

Xinuo (Johnny) Zhao

Overview

● Data processing instructions○ Binary encoding and Assembler format○ Equivalent ARM instructions

● Breakpoint instructions

ARM vs. Thumb data processing instructions

● bit 10 toggles register/immediate operand● bit 9: 0 - ADD, 1 - SUB● 3 bit immediate value● 3 bit to represent registers

● Rn (+ or -) Rm -> Rd

● Rn (+ or -) #imm3 -> Rd

● 2 bit opcode ○ 0 - MOV○ 1 - CMP○ 2 - ADD○ 3 - SUB

● 8 bit immediate value● Register is also the

destination register

● 5 bit immediate value for shift offset● 2 bit opcode:

○ 0 - LSL○ 1 - LSR○ 2 - ASR○ reason not having 3?

● 4 bit opcode

○ 0 - AND

○ 1 - EOR

○ 2 - LSL

○ 3 - LSR

○ 4 - ASR

○ 5 - ADC

○ 6 - SBC

○ 7 - ROR

○ 8 - TST

○ 9 - NEG

○ 10 - CMP

○ 11 - CMN

○ 12 - ORR

○ 13 - MUL

○ 14 - BIC

○ 15 - MVN

● D,M bits: operand flags indicating whether Rm or Rd is a ’Hi’ register (r8-r15)

● 2 bit opcode: ○ 0 - ADD○ 1 - CMP○ 2 - MOV○ 3 - BX (review previous lectures)

● R bit: ○ 0 - PC○ 1 - SP

● (PC or SP) + #imm8 -> Rd● 8 bit immediate value

● A bit: ○ 0 - ADD○ 1 - SUB

● SP (+ or -) #imm7 -> SP● 7 bit immediate value

ARM instructions THUMB instructions

MOVS Rd, #<#imm8> MOV Rd, #<#imm8>

MVNS Rd, #<#imm8> MVN Rd, Rm

CMP Rd, #<#imm8> CMP Rn, #<#imm8>

CMP Rn, Rm CMP Rn, Rm

TST Rn, Rm TST Rn, Rm

ADDS Rd, Rn, #<#imm3> ADD Rd, Rn, #<#imm3>

ADDS Rd, Rd, #<#imm8> ADD Rd, #<#imm8>

ADDS Rd, Rn, Rm ADD Rd, Rn, Rm

ADCS Rd, Rd, Rm ADC Rd, Rm

SUBS Rd, Rn, #<#imm3> SUB Rd, Rn, #<#imm3>

SUBS Rd, Rd, #<#imm8> SUB Rd, #<#imm8>

SUBS Rd, Rn, Rm SUB Rd, Rn, Rm

SBCS Rd, Rd, Rm SBC Rd, Rm

RSBS Rd, Rn, #0 NEG Rd, Rn

● Instructions that uses the ‘Lo’, general-purpose registers (r0 - r7)

ARM instructions THUMB instructions

MOVS Rd, Rm, LSL #<#sh> LSL Rd, Rm, #<#sh>

MOVS Rd, Rd, LSL Rs LSL Rd, Rs

MOVS Rd, Rm, LSR #<#sh> LSR Rd, Rm #<#sh>

MOVS Rd, Rd, LSR Rs LSR Rd, Rs

MOVS Rd, Rm, ASR #<#sh> ASR Rd, Rm, #<#sh>

MOVS Rd, Rd, ASR Rs ASR Rd, Rs

MOVS Rd, Rd, ROR Rs ROR Rd, Rs

ANDS Rd, Rd, Rm AND Rd, Rm

EORS Rd, Rd, Rm EOR Rd, Rm

ORRS Rd, Rd, Rm ORR Rd, Rm

BICS Rd, Rd, Rm BIC Rd, Rm

MULS Rd, Rm, Rd MUL Rd, Rm

● Instructions that uses the ‘Lo’, general-purpose registers (r0 - r7):

ARM instructions THUMB instructions

ADD Rd, Rd, Rm ADD Rd, Rm (1/2 Hi regs)

CMP Rn, Rm CMP Rn, Rm (1/2 Hi regs)

MOV Rd, Rm MOV Rd, Rm (1/2 Hi regs)

ADD Rd, PC, #<#imm8> ADD Rd, PC, #<#imm8>

ADD Rd, SP, #<#imm8> ADD Rd, SP, #<#imm8>

ADD SP, SP, #<#imm7> ADD SP, SP, #<#imm7>

SUB SP, SP, #<#imm7> SUB SP, SP, #<#imm7>

● Instructions that operate with or on the ‘Hi’ registers (r8 - r15), in some cases in combination with a ‘Lo’ register:

Breakpoint

● Binary encoding○ ARM

○ Thumb

● Assembly format○ BKPT (identical)