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7/29/2019 Timing Control
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3/12/13
Timing control in verilog
Module 3.1 Delays in Verilog
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Procedural blocks andtiming controls.
Delay controls.
Edge-Sensitive Event controls.
Level-Sensitive Event controls-Waitstatements.
Named Events.
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Timing Controls
Delay-Based
Regular delay control
AKA Inertial Delay
Intra-assignment delay control
AKA Transport delay
Zero delay control
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Regular Delay Control
parameter latency = 20;
parameter delta = 2;
regx,y,z,p,q;
InitialBegin
x=0; // no delay control
#10 y = 1; //delay control with a constant
#latency z = 0; //delay control with identifier
#(latency + delta) p = 1; //delay control withexpression
#y x = x + 1; //delay control with identifier
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Intra-assignment delaycontrolAssigning delay to the right of the
assignment operator
The intra-assignment delay computes theright-hand-side expression at the currenttime and defer the assignment of thecomputed value to the left-hand-sidevariable.
Equivalent to regular delays with atemporary variable to store the current value
of a right-hand-side expression
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Intra-assignment Delay
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Example 1
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Example 2 : change inassignment
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Example 3 : Ex1 +change in assignment
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Zero delay control
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Zero delay control
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Timing Control
Verilog is a discrete event timesimulator. If there is no timingcontrol, simulation time does notadvance.
Simulated time can onlyprogress byone of the following: gate or wire delay, if specified
a delay control, introduced by the #
symbol. an event control, introduced by the @
symbol.
the wait statement.
The order of execution of events in the
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Delay based Timing Control
Delay Control (#) Expression specifies the time duration
between initially encountering thestatement and when the statementactually executes.
Delay in Procedural Assignments
Inter-Statement Delay
Intra-Statement Delay
For example: Inter-Statement Delay
#10 A = A + 1; Intra-Statement Delay
A = #10 A + 1;
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Event-Based Timing Control(cont.)Events (@)
Change in the value of a register ornet
Used to trigger execution of astatement or block (reactivebehavior/reactivity)
Types of Event-based timingcontrol Regular event control
Named event control
Event OR control
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Event-Based Timing Control(cont.)Regular event control
Symbol: @()
Events to specify:
posedge sig:
Change ofsig from any value to 1or from 0 to any value
negedge sig: Change ofsig from any value to 0
or from 1 to any value
sig: Any chage in sig value
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Event-Based Timing Control(cont.)Regular event control Examples:
@reg_a begin
A = B&C;
end
@(posedge clock1) A = B&C;
@(negedge clock2) A = B&C;
Forever @(negedge clock3)
begin
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Event-Based Timing Control(cont.)Named event control
You can declare (name) an event, and thentriggerand recognize it.
Verilog keyword for declaration: eventeventevent1;
Verilog symbol for triggering: ->
->event1
Verilog symbol for recognizing: @()
@(event1) begin
end
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Event-Based Timing Control(cont.)Event OR control
Used when need to trigger a block upon occurrenceofany of a set of events.
The list of the events: sensitivity list
Verilog keyword: or Look at the handout
Event OR control Example:
always @ ( reset or clock )
begin
if ( reset )
q= 1b0;
else= d
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Timing Control (cont.)
wait StatementThe wait statement allows a procedural
statement or a block to be delayed until acondition becomes true.
The difference between the behavior of await statement and an event is that thewait statement is level sensitivewhereas @(posedge clock); is triggeredby a signal transition or is edgesensitive.
For Example:
wait (A == 3)
begin
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Delay Back-Annotation
Delay back- annotation is an
important and vast topic in timingsimulation.
in this section, we introduce thedesigner to the concept of back-
annotation of delays in asimulation.
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The various steps in the flow that use delayback-annotation are as follows:
1. The designer writes the RTL description andthen performs functional simulation.
2. The RTL description is converted to a gatelevel netlist by a logic synthesis tool.
3. The designer obtains prelayout estimates ofdelays in the chip by using a delay calculatorand information about the IC fabricationprocess. Then, the designer does timing
simulation or static timing verification of thegate-level netlist, using these preliminary
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4. The gate-level netlist is then converted tolayout by a place and route tool. Thepostlayout delay values are computed from
the resistance (R) and capacitance (C)information in the layout. The R and Cinformation is extracted from factors suchas geometry and IC fabrication process.
5. The post-layout delay values are back-annotated to modify the delay estimates forthe gate-level netlist. Timing simulation orstatic timing verification is run again on thegate-level netlist to check if timingconstraints are still satisfied.
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Delay Back-Annotation