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Tip Sheet for 2014 Symposia on VLSI Technology and Circuits

HONOLULU, HAWAII -- This Tip Sheet is an advance look at some of the most newsworthy papers to be presented at the 2014 Symposia on VLSI Technology & Circuits, which will be held at the Hilton Hawaiian Village here June 9-12, 2014 (Technology Symposium) and June 10-13, 2014 (Circuits Symposium). See the Editor Press Center for higher-resolution versions of these images. A glossary of technical terms is at the end of this tip sheet.

I) Technical Highlights from the Symposium on VLSI Technology

A) Platform Technology for CMOS Manufacturing 10-nm Platform Technology Featuring FinFET on Bulk and SOI: In the first-ever demonstration of FinFET technology suitable for 10-nm CMOS manufacturing – pushing device scaling two nodes beyond the current leading-edge volume production technology – Samsung and others will jointly showcase a platform technology for low-power and high-performance applications. It offers the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported on both bulk and SOI substrates. A 0.053 µm2 SRAM bit-cell is reported with a low corresponding static noise margin of 140 mV at 0.75 V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. A multi-workfunction gate stack provides Vt tunability without the variability degradation channel dopants induce. (Paper T2.2, “A 10nm Platform Technology for Low Power and High Performance Applications Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI,” K.-I. Seo et al., Samsung, IBM, STMicroelectronics, GLOBALFOUNDRIES & UMC)

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Projected scaling trend, featuring the tightest contacted poly pitch (CPP=64 nm) and metallization pitch

(Mx=48 nm) ever reported, on both bulk and SOI substrates. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications: As an alternative to FinFETs, which are inherently a complex 3D technology given their tall and thin gates, fully depleted silicon-on-insulator (FDSOI) technology is a simpler planar alternative that has shown great promise for volume production. This paper from STMicroelectronics, CEA-LETI and IBM confirms a scaling path for FDSOI technology down to 14nm, using strain-engineered FDSOI transistors. Compared to 28-nm FDSOI, it provides an 0.55x area reduction from scaling and a 30% speed boost at the same power – or a 55% power reduction at the same speed – due to a) an increase in drive current and b) low gate-to-drain capacitance. Using forward back-bias, an additional 40% dynamic power reduction for ring oscillators is experimentally demonstrated. Moreover, a full single-port SRAM is described, including a 0.081 µm2 high-density bitcell and two 0.090 µm2 bitcell designs used to address high-performance and low-leakage/low Vmin requirements. (Paper T2.3, “14nm FDSOI Technology for High Speed and Energy Efficient Applications,” O. Weber et al., STMicroelectronics, CEA-LETI & IBM)

TEM photo of an FDSOI nMOS transistor, showing gate-to-drain capacitance components and experimental values. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

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B) Emerging Device Technology Strained SiGe-on-Insulator FinFET for 10nm and Below: Forging ahead in beyond Si channel technology, IBM and others will demonstrate the most aggressively scaled strained silicon-germanium (SiGe) FinFET reported to date. It features a fin width of ~8 nm and gate length of ~15 nm, with high current drive and low leakage. The high performance s-SiGe pMOS devices show Ion ~1.05 mA/µm and ~1.3 mA/µm at Ioff=100 nA/µm and VDD=0.8 and 1 V respectively, with extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and novel interface passivation scheme enable a ~30% mobility enhancement and subthreshold swing reduction to 65mV/dec. Moreover, s-SiGe FinFETs are shown to be strong candidates for future applications at VDD=0.5 V, with very low GIDL-limited ID_min and a more manufacturing-friendly process compared to high-Ge content SiGe devices. They also exhibit an impressive Ion ~ 0.42 mA/µm at Ioff =100 nA/µm, and gm_int as high as 2.4 mS/µm. (Paper T2.4, “Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond,” P. Hashemi et al., IBM, GLOBALFOUNDRIES & MIT)

TEM images of the most aggressively scaled SiGe FinFET reported to date with a fin width of ~ 8 nm and

gate length of ~ 15 nm. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

Hetero-Integration of InGaAs Quantum Well FinFET: Addressing the challenge of integrating non-Si channel materials onto 300mm Si substrates, imec and BASF will describe indium gallium arsenide (InGaAs) FinFETs made with a unique silicon (Si) fin-replacement process, intended for integration of non-silicon channel materials onto 300mm Si substrates. The devices are integrated by process modules developed for a Si/III-V hybrid 300 mm R&D pilot line, which is compatible with future CMOS high-volume manufacturing. These are the first InGaAs FinFETs with subthreshold slope of 190 mV/dec and extrinsic transconductance (gm) of 558 µS/µm that have been achieved, with an effective oxide thickness (EOT) of 1.9 nm; Lg of 50 nm; and fin width of 55 nm. A trade-off between off-state leakage and mobility for different p-type doping levels of the InP and InGaAs layers was investigated. RMG (replacement metal gate) high-κ-last processing is demonstrated, which showed significant performance improvements versus high-κ-first processes. (Paper T4.1, “An InGaAs/InP Quantum Well FinFET Using the Replacement Fin Process Integrated in an RMG Flow on 300mm Si Substrates,” N. Waldron et al., imec & BASF)

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Process flow for InGaAs fin formation, using a fin replacement process.

▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫ High Performance Strained SiGe Nanowire TFET: Tunnel FETs (TFETs) are a promising candidate for beyond-CMOS manufacturing, but their low on-current (ION) performance is a major challenge which must be solved if they are to become viable. CEA-LETI and others will present for the first time high-performance nanowire (NW) TFETs built with a CMOS-compatible process flow. The devices feature compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge00.3 source/drain, and high-κ metal gate. The nanowire architecture strongly improves electrostatics, while the low-bandgap SiGe channel provides enhanced band-to-band tunneling (BTBT) to mitigate the low ION problem. By investigating the BTBT and NW width scaling, a record high ION up to 760 µA/µm and average subthreshold slopes of less than 80mV/dec were achieved. (Paper T8.1, “First Demonstration of Strained SiGe Nanowires TFETs with ION beyond 700µA/µm,” A. Villalon et al., CEA-LETI, SOITEC, U. of Udine & IMEP-LAHC)

TEM photos of high-performance nanowire tunnel FETs. a) shows the gated P+-I-N+ structure of a wide device; b) shows the source side of a short channel l device, and c) is a cross-section of a SiGe nanowire.

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C) Emerging Nonvolatile Technology Copper-Complementary Atom Switch, with High-Temperature Retention: For future low-power nonvolatile programmable logic, researchers from Japan’s Low Power Electronics Association & Project (LEAP) consortium will reveal a critical redox-control technology to enable conducting bridge devices. Fast (10 ns) and low voltage (2 V)

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programming of copper (Cu) atom switches are demonstrated in a 1Mb switch array for the first time. A newly developed redox-control buffer of Al0.5Ti0.5Ox leads to extremely steeply sloped, voltage-dependent, time-to-on-state (56 mV/dec) switching, by eliminating metallic Al residues at the Cu surface. Data-retention tests at 260 °C, and DC stress tests (Imax=140 µA) at 125 °C, showed that all the programmed on-states had long lifetimes. (Paper T22.5, “A Fast and Low-Voltage Cu Complementary-Atom-Switch 1Mb Array with High-Temperature Retention,” N. Banno et al., LEAP)

In the image above, a) and b) show low- and high-magnification TEM views, respectively, of a copper atom

switch for a conductive-bridge nonvolatile programmable logic device. The two lower images are energy dispersive X-ray (EDX) maps of c) copper electrode and d) ruthenium buffer layer.

▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫ Memories Printed on Paper: National Taiwan University will report the first paper-based nonvolatile memories – resistive random access devices – made with an all-printing approach using a sequence of inkjet- and screen-printing techniques. The printed paper-based memory devices (PPMDs) can be applied as labels on electronics or on living objects for multi-functional, wearable, on-skin, and biocompatible applications. The results show PPMDs would be the key to fully paper-based circuits that could be implemented directly in medical biosensors, multi-functional devices, and self-powered systems. (Paper T7.1, “Paper Memory by All Printing Technology,” D.-H. Lien et al., NTU)

In the illustration above, a) is a schematic diagram showing the fabrication process for a resistive memory device printed on paper, while b) is a photograph of the device taken by optical microscopy; the letters and line arrays (composed of Ag and TiO2) demonstrate great degree of freedom of inkjet printing. c) is a magnification of one of the letters, while d) is a cross-sectional image of the device taken by a scanning electron microscope.

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D) Design & Technology Co-Optimization Cost, Power & Performance Optimization of 20-nm SOC Technology: With an eye toward building an industry-first 20-nm cellular modem chip, Qualcomm and TSMC will describe a cost-competitive 20-nm technology node using process and design co-optimization. Compared to the 28-nm high-k metal gate (HKMG) node, it delivers twice the peak data rates and twice the carrier aggregation through layout context optimization and continuous process improvements, which led to an 18% boost in circuit performance and a simultaneous >30% reduction in power. Three-mask local interconnect and 64-nm double-patterning of lower level metals were used to achieve about twice the gate density. A single-patterning 80 nm pitch metal for routing levels was optimized for both density and performance. Consequently, the resulting technology is more cost effective compared to 28-nm HKMG processes and is cost-competitive versus 28-nm polySiON. (Paper T17.4, “Cost and Power/Performance Optimized 20nm SoC Technology for Advanced Mobile Devices,” G. Nallapati et al., Qualcomm & TSMC)

Gate-tie construct for within-gate pitch connection of gate to source to enable high speed blocks without sacrificing device width and M1 tracks. Shaded areas are cells with layout context optimization, while

green areas are standard cells. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

E) Functional Diversification

Curved CMOS Image System: When light transmitted by a lens strikes a perpendicular target such as a CMOS image sensor, it forms a circle of light called an image circle. It’s difficult for a flat (planar) CMOS image sensor to deliver high image sensitivity at high resolution (highly scaled pixel pitch) because of the fundamental physical limit known as quantum efficiency. To break through that physical limit and to achieve higher sensitivity anywhere within the image circle at higher resolution, Sony built and will describe an imaging system that comprises a hemispherically curved, back-illuminated CMOS image sensor (BIS) and integrated lens. It doubles the sensitivity at the edge of the image circle while increasing sensitivity at its center by a factor of 1.4, with a 5x reduction of dark current (Jd) compared to a planar BIS. Moreover, a common problem known as lens field curvature aberration (Afc) is mitigated by the curved sensor itself, and so the curved BIS enables higher system sensitivity with a brighter lens with a smaller F number (Fn) than is

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possible with a planar BIS. In addition, by controlling the tensile stress of the BIS chip to produce a curved shape in the first place, the energy band-gap (Eg) is widened and a lower Jd is achieved. (Paper T2.1, “A Novel Curved CMOS Image Sensor Integrated with Imaging System,” K. Itonaga et al., Sony)

Concept of an imaging system which integrates a curved sensor with a brighter (lower F number) lens for

better image sensitivity. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

More-than-Moore Silicon Photonics: Silicon photonics is the term for photonic devices that are mass-produced using economical CMOS technologies. At this year’s VLSI Technology Symposium, Micron Technology will describe the first monolithic silicon-photonics–on-bulk-CMOS process flow for devices that would interconnect distant, distributed memories. Features include deep-trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables transmit/receive operation while minimizing interconnect parasitics. With the addition of an external 1280-nm light source, a fully functional optical link (5 Gb/s with 2.8 pJ/b), capable of WDM (wavelength division multiplexing), has been demonstrated. In addition to the polysilicon resonant detector used in the link, a monolithically integrated SiGe-based photodetector using selective epitaxial growth was also developed. (Paper T21.1, “Integration of Silicon Photonics in Bulk CMOS,” R. Meade et al., Micron, MIT, U. of Colorado & UC Berkeley)

Design layout of an integrated electro-optic test cell with transmission eye diagram (inset)

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II) Technical Highlights from the Symposium on VLSI Circuits

A) SOC Circuits and Processors Among the various innovations in SOC (system-on-a-chip) circuits being presented at this year’s VLSI Symposia, two presentations will address the increasing demand for efficient data encryption solutions. A paper by S. Mathew et al. from Intel Corp., will describe an AES (Advanced Encryption Standard) hardware accelerator module suitable for battery-constrained mobile and wearable systems. The accelerator is implemented in Intel’s 22nm tri-gate (FinFET) CMOS technology with only 2090 gates. It features an operating voltage range of 0.34V to 1.10V, a peak energy-efficiency of 289 Gbps/W, and an AES-128 encrypt/decrypt throughput of 432 Mbps/671 Mbps (respectively) at 0.9V room temperature. (Paper C16.1, “340mV-1.1V, 289Gbps/W, 2090-gate NanoAES Hardware Accelerator with Area-optimized Encrypt/Decrypt GF(2^4)^2 Polynomials in 22nm tri-gate CMOS,” S. Mathew, et al., Intel Corporation) Meanwhile, N. Miura et al. from Kobe and Tohoku University will describe a cryptographic engine which is resistant against local analysis attacks that occur via a micro-electromagnetic probe. An LC-oscillator detects the approach of a probe and subsequently protects the secret data by switching into a dummy or a lock mode. A hardware prototype successfully demonstrated its functionality, and confirmed a relatively low power and performance adder of 7.6% and 0.2%, respectively. (Paper C16.4, “A Local EM-Analysis Attack Resistant Cryptographic Engine with Fully-Digital Oscillator-Based Tamper-Access Sensor,” N. Miura et al., Kobe University)

Intel will describe a 22-nm FinFET-based AES-128 data-encryption hardware accelerator module for battery-powered systems. As shown in the figures above, it has an operating voltage range of 0.34V to

1.10V, peak energy-efficiency of 289 Gbps/W, and an AES-128 encrypt/decrypt throughput of 432 Mbps/671 Mbps (respectively) at 0.9V.

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Researchers from Kobe and Tohoku University will describe a cryptographic engine that is resistant to

local analysis attacks that occur via a micro-electromagnetic probe. An LC-oscillator detects the approach of a probe and subsequently protects the secret data by switching into a dummy or a lock mode.

▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫ Another notable SOC paper, by Y. Sinangil et al. from MIT, NVIDIA, and the University of Chicago, will describe a self-aware processor with energy-monitoring circuits that can measure the actual energy consumption of its major circuit blocks. The monitors are directly embedded into the on-chip DC/DC converters with a small power/area overhead of less than 0.1% and 1.0%, respectively. That enables the process to operate over a wide range of applications and under dynamic operating conditions, in particular a scalable voltage range between 0.6V and 1.8V.Low voltage operation is supported by SRAM circuits with 8T bit-cells and write-assist functionality. Hardware measurements confirm energy savings of up to 8.4x. (Paper C16.5, “A Self-Aware Microprocessor SoC using Energy Monitors Integrated into DC/DC Converters for System Adaptation,” Y. Sinangil et al., MIT)

A paper from MIT, NVIDIA, and the University of Chicago will describe a self-aware processor with

energy-monitoring circuits that can measure the actual energy consumption of its major circuit blocks. The monitors are directly embedded into on-chip DC/DC converters with a small power/area overhead of less

than 0.1% and 1.0%, respectively. Energy savings of up to 8.4x were reported. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

B) Joint Focus Session on Memory Innovations

Embedded memory macros often are of mutual interest for technology experts and circuit designers alike. Accordingly, two Joint Focus Sessions have been established to present a variety of innovations in the field of DRAM, SRAM and non-volatile memory circuits. Among the DRAM and SRAM presentations, S. Tanaka et al. of Renesas Electronics will describe a dual-port SRAM featuring a self-adjustable negative bias bit line write-assist technique characterized by a highly granular voltage-dependent tuning of the write-assist

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level. They built a 512 Kbit test chip in 28-nm HKMG technology (1 GHz operation at 1.0V) that demonstrated a Vmin reduction of 190mV and a 21% power reduction compared to previous assist circuits. (Paper C14.1, “A 512-kb 1-GHz 28-nm Partially Write-Assisted Dual-Port SRAM with Self-Adjustable Negative Bias Bitline,” S. Tanaka et al., Renesas Electronics) In addition, industry papers by ARM, MoSys, and Intel will provide details of the latest innovations in embedded SRAM and DRAM macros.

Renesas will describe a dual-port 512 Kbit SRAM in 28-nm HKMG technology that operates at 1 GHz at

1.0V. It demonstrates a Vmin reduction of 190mV and a power reduction of 21% compared to previous assist circuits.

▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫ With regard to non-volatile memory, H. Noguchi et al. of Toshiba Corp. will describe a highly reliable, low-power non-volatile cache memory based on an advanced perpendicular STT-MRAM. A novel read-out circuit with dual sensing capabilities provides high reliability together with typical error-correction coding. The proposed solution offers performance-to-power numbers that exceed existing SRAM, embedded DRAM and STT-MRAM solutions. (Paper C12.1, “Highly Reliable and Low-Power Nonvolatile Cache Memory with Advanced Perpendicular STT-MRAM for High-Performance CPU,” H. Noguchi et al., Toshiba Corporation)

A reliable, low-power STT-MRAM-based non-volatile cache memory from Toshiba offers better

performance-to-power-level capabilities than existing SRAM, embedded DRAM and STT-MRAM solutions. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

A paper by S. Tanakamaru et al. of Chuo University and the University of Tokyo will describe new schemes targeting an improved market adoption for SSD (solid-state drives)

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based on MLC (multi-level cell) NAND memories. An application-aware coding scheme will be presented which can support applications requiring high endurance and low data-retention (e.g. cloud servers), as well as applications needing low endurance but high data-retention (e.g. photos in social networks). The schemes improve bit-error-rates by 79% and 52% for the n-out-of-8 level cell and the universal asymmetric coding scheme, respectively. (Paper C12.4, “Application-Aware Solid-State Drives (SSDs) with Adaptive Coding,” S. Tanakamaru, Chuo University)

Chuo University and the University of Tokyo will describe an application-aware coding scheme for solid-state drives based on multi-level-cell NAND memories. The application-aware functionality enables it to support applications ranging from those needing high endurance/low data-retention capabilities, to those

needing low endurance/high data-retention capabilities. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

C) Wireless Sensor Nodes and Medical Electronics

New integration concepts and ultra-low-power VLSI circuits have been the basis for major advancements in the field of wireless sensor nodes, particularly in medical electronics. To address the growing interest in those disciplines, the 2014 Symposium on VLSI Circuits will feature four dedicated paper sessions on the following topics:

� Power Management for Wireless Sensor Nodes � Sensor Node Radios � Medical Imaging � Biomedical Circuits & Systems

A notable paper by M. Tabesh et al. from the University of Berkeley and Stanford University will describe a 24/60 GHz passive radio system implemented on a wireless-powered pad-less single chip. It provides high miniaturization and low costs for applications like sensor monitoring, RFID tagging or inventory tracking. The chip is built in 65-nm CMOS and measures only 3.7mm x 1.2mm including antennas, but with no need for any additional components. The entire system operates with standby harvested power below 1.5uW and an aggregated data rate above 12 Mbps. (Paper C7.1, “A Power-Harvesting Pad-Less mm-Sized 24/60GHz Passive Radio with On-Chip Antennas,” M. Tabesh et al., University of Berkeley)

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A paper from University of California, Berkeley and Stanford will describe a single-chip 24/60 GHz

passive radio system for applications like sensor monitoring, RFID tagging, or inventory tracking. The entire system operates with standby harvested power below 1.5uW and has an aggregated data rate above

12 Mbps. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

A paper from I. Lee et al. from the University of Michigan describes a battery supervisory circuit for low-power wireless sensor nodes which are powered by an energy-harvester/battery combination. Battery health is monitored and battery charging is controlled such that a constant effective threshold voltage is achieved. As a result, the usable range of battery voltages is increased while voltage oscillations are avoided at the same time. Compared to conventional battery supervisory circuits, it demonstrated much lower hysteresis (77mV vs. 656mV) and much higher battery voltage ranges (up to 2.7 times). (Paper C3.1, “Low Power Battery Supervisory Circuit with Adaptive Battery Health Monitor,” I. Lee et al., University of Michigan)

A University of Michigan paper will describe a battery supervisory circuit for low-power wireless sensor nodes that are powered by an energy-harvester/battery combination. It

allows a constant effective threshold voltage to be maintained and voltage fluctuations to be reduced, thus rendering a wide range of battery voltages usable while minimizing

losses. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

A paper by T. Morrison et al. from the University of Washington describes a single-chip solution for a wearable electrocardiography (ECG) system that enables secure, continuous cardiac monitoring on mobile devices like smartphones. The chip is integrated into a “smart shirt” – a form-fitting textile together with flexible electrodes, battery, and antenna. Clinically standard 12-lead ECG data is recorded from this smart shirt, encrypted and wirelessly transmitted via an on-chip ISM-band radio and flexible antenna.

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It dissipates less than 1 mW. (Paper C18.4, “A Single-chip Encrypted Wireless 12-Lead ECG Smart Shirt for Continuous Health Monitoring,” T. Morrison et al., University of Washington)

A University of Washington paper will describe a single-chip solution for a low-power, wearable electro-

cardiography (ECG) system that enables secure, continuous cardiac monitoring on mobile devices like smartphones. The chip is integrated into a “smart shirt” – a form-fitting textile that includes with flexible

electrodes, battery, and antenna. ▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫

D) Data Converter Circuits

These four technical sessions of the 2014 Symposium on VLSI Circuits will address the increased number of innovations in data converter circuits:

� Advanced ADC Techniques � Oversampled ADCs � DACs and Mixed-Signal Techniques � High-Speed SAR ADCs

A paper by B. Verbruggen et al. from imec, Renesas Electronics, and the Vrije University of Brussels will describe a 200 MS/s 2x interleaved 14-bit pipelined SAR ADC (successive approximation register analog-to-digital converter). The ADC uses a new residue amplifier to achieve low noise at low power, and incorporates interleaved channel time-constant calibration. Built in 28-nm CMOS technology, it features a peak SNDR (signal-to-noise + distortion ratio) of 70.7 dB at 200 MS/s while consuming 2.3mW at 0.9V. (Paper C23.1, “A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS,” B. Verbruggen et al., Renesas Electronics)

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Imec, Renesas Electronics, and the Vrije University of Brussels will describe a 200 MS/s 2x interleaved 14-bit pipelined SAR (successive approximation register) A/D converter that achieves low noise at low power -- a peak SNDR (signal-to-noise + distortion ratio) of 70.7 dB at 200 MS/s. It consumes just 2.3mW at 0.9V.

▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫ An innovative nine-bit interleaved DAC (digital-to-analog converter) will be presented by E. Olieman et al. from the University of Twente. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC is implemented in a 28nm FD-SOI technology and features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage. (Paper C19.4, “A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist,” E. Olieman et al., University of Twente)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time

interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2

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E) Frequency Generation and Clock Circuits S.-J. Kim et al. from Samsung Electronics will describe the first synchronous cyclic TDC (time-to-digital-converter). The TDC is implemented in a 28nm CMOS technology and features a novel 2x time amplifier whose gain is insensitive to variations and noise. The 12-bit TDC occupies only 0.01mm2, consumes 0.820mW at 0.9V, and achieves 0.63ps of time resolution over a 2.6ns input range. (Paper C22.2, “A 0.63ps, 12b, Synchronous Cyclic TDC using a Time Adder for On-chip Jitter Measurement of a SoC in 28nm CMOS Technology,” S.-J. Kim et al., Samsung Electronics)

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Samsung will describe the first synchronous cyclic time-to-digital converter, whose gain is insensitive to

variations and noise. A paper by F.-W. Kuo et. al. from TSMC and the Delft University of Technology discloses a new architecture for an all-digital PLL (phase-locked-loop) for advanced cellular radios, like 4G mobile phones. It is based on a wide tuning range, a fine-resolution class-F DCO with only switchable metal capacitors, and a phase-predictive TDC. The all-digital PLL is realized on a 28nm CMOS technology platform, supports a two-point modulation, and consumes 12mW at a 1.05V supply voltage while occupying 0.22mm2 of area. Compared to previous solutions, a 72% reduction in power and a 38% area reduction are achieved. (Paper C9.4, “A 12mW All-Digital PLL Based on Class-F DCO for 4G Phones in 28nm CMOS,” F.-W. Kuo et al., TSMC)

TSMC and Delft University of Technology will discuss a new architecture for an all-digital phased-locked

loop for advanced cellular radios, like 4G mobile phones. Compared to previous solutions, a 72% reduction in power and a 38% area reduction are achieved

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F) Wireline Receivers and Transmitters As in previous years, the 2014 Symposium on VLSI Circuits will include a wide variety of papers on wireline and optical communication and their corresponding circuit

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implementations, including sessions on “Ultra-High-Speed Wireline Transceivers” and “Advanced Wireline Techniques.” E.-H. Chen et. al. of Rambus will discuss a 40 Gb/s Serial Link SerDes (serializer/deserializer) for chip-to-chip communication. It targets applications in communication systems with high I/O bandwidth, such as the routers and servers which address the steadily increasing demands of networking and cloud-based applications. The SerDes features two-tap feed-forward equalizers (FFE) in both transmitter and receiver, a three-stage continuous-time linear equalizer and discrete-time equalizers. It is realized in 28nm CMOS technology and exhibits a 23.2 mW/Gb/s power efficiency at 40 Gb/s. (Paper C2.3, “A 40-Gb/s Serial Link Transceiver in 28-nm CMOS Technology,” E-H. Chen et al., Rambus)

40-Gb/s Tx eye (a) without and (b) with the Tx-FFE for 1st post-cursor cancellation after an 8-dB loss

channel, as proposed by Rambus.

A paper by A. Garg et al. from Broadcom describes a quad-channel 112-128 Gb/s coherent DP-QPSK transmitter. The single 27.9-32.1 Gb/s transmitter lane features a half-rate architecture with a two-tap FIR. The DP-QPSK transmitter’s pre-decoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a global reset. The power consumption of the transmitter and PLL is reported at 712 mW. (Paper C2.2, “A Quad-Channel 112-128 Gb/s Coherent Transmitter in 40 nm CMOS,” A. Garg et al., Broadcom)

Broadcom will describe a quad-channel 112-128 Gb/s coherent DP-QPSK transmitter. Its pre-decoded

data alignment is maintained by the use of an automatic synchronous feedback loop, removing the need for a global reset.

▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫▫ Here are definitions of some important technical terms:

� ADC, or Analog-to-Digital Converter – A device that converts a continuous physical quantity (usually voltage) to a digital number.

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� Back-End/BEOL and Front-End/FEOL -- In integrated circuit manufacturing, transistors and other active devices are built first (at the front end of the manufacturing line or FEOL), while the interconnect, or the wiring, is built afterward, at the “back end” of the manufacturing line (BEOL).

� CMOS/MOS/MOSFET/FET-- Most transistors today are FETs, or field-effect transistors. Most FETs are built with CMOS manufacturing technology (complementary metal oxide semiconductor). Generically they are called MOSFETs, or sometimes MOS transistors.

� Compound/III-V Semiconductors -- Most semiconductors are silicon-based, but researchers continue to investigate other semiconducting materials with higher electron mobilities because they can be used to make faster devices. The tradeoff is that the materials are harder to work with than silicon. Compound semiconductors are made of two or more elements (e.g. GaAs, InP, GaN, etc.) which are generally found in groups III and V of the periodic table of the elements.

� DAC or Digital-to Analog Converter – A device that converts digital data into an analog signal (current, voltage, or electric charge).

� DP-QPSK – An acronym for “dual polarization quadrature phase shift keying.” Phase-shift keying is a digital method of conveying data by changing, or modulating, the phase of a reference signal known as a carrier wave. DP-QPSK is a sophisticated version of phase-shift keying intended to reduce conversion error rates.

� FD-SOI -- Fully depleted silicon on insulator, a class of transistor architectures that can offer speed and power advantages over standard silicon transistors.

� FinFET -- A transistor whose shape resembles a fin, usually with multiple gates surrounding it for better on/off switching control.

� Front-End/FEOL and Back-End/BEOL -- In integrated circuit manufacturing, transistors and other active devices are built first (at the front end of the manufacturing line or FEOL), while the interconnect, or the wiring, is built afterward, at the “back end” of the manufacturing line (BEOL).

� HKMG, or High-k Dielectrics/Metal Gates -- A dielectric is an electrical insulator. “k” is the relative permittivity and is a measure of how well a material will prevent current flow between the gate electrode and the channel region of a field-effect transistor, while capacitively coupling the two to control on/off switching. In future CMOS integrated circuits (chips) the gate dielectric will need to provide capacitive coupling equivalent to that of a silicon-dioxide layer that is just a few atoms thick, to allow the length of the channel region to be scaled down to 10 nm and below. Metal gate materials are more compatible with high-k gate dielectrics than are traditional doped polycrystalline silicon material. Much progress has been made in recent years to integrate metal gates into the CMOS process flow for the manufacture of high-performance chips.

� III-V -- see Compound/III-V Semiconductors � Integrated Circuit -- An electrical circuit comprising many interconnected elements (e.g.

transistors, diodes, capacitors, resistors, inductors) built on a semiconducting substrate. � Interconnect -- The metal lines, or wiring, connecting transistors and other circuit elements. See

Back-End/BEOL. � Low-k Dielectrics/Interconnect -- Interconnect refers to the metal wires that connect elements

together in an integrated circuit (chip). The close proximity of adjacent wires can result in capacitance that can limit chip performance. A low-k dielectric is needed, to electrically insulate the copper lines while minimizing their mutual capacitance, but these materials are generally more fragile and thus pose challenges for manufacturing.

� MEMS -- A micro-electro-mechanical system, containing micrometer-scale moving parts. � N-FET/P-FET or NMOS/PMOS -- MOSFETs come in two varieties (n-channel or p-channel)

which operate in a complementary fashion. � Non-volatile memory (NVM) – A type of computer memory that retains its stored information

even when the power is off. � Phase-Change Memory/PCM -- Phase-change materials have crystalline and non-crystalline

states which are used to represent the digits “0” or “1” in computer non-volatile memory. Electrical current is used to toggle between the two states – heat from the current causes the material to change its state.

� Scaling/Density/Integration -- Scaling is making transistors and other circuit elements smaller so that more of them will fit on a chip. A denser chip has more transistors on it than one which is less

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dense. Integration is combining circuit elements on a chip to add more functions to achieve lower cost per function.

� Semiconductor -- A material that can be made to conduct or to block the passage of electrical current, giving the ability to store and process information.

� SOI -- A silicon-on-insulator substrate, used to reduce parasitic capacitance and thereby improve integrated circuit performance

� Strained silicon & SiGe stressors -- Silicon is said to be “strained” when its atoms are pulled farther apart or closer together than normal. Doing so alters the ease with which electrons flow through the silicon, enabling transistors built with it to operate faster and /or at lower voltage. The external stressors which impart strain are materials with slightly different atomic spacing than silicon. For example, a common way to compressively strain the channel region of a p-channel silicon field-effect transistor is to embed silicon-germanium (SiGe) – which has larger atomic spacing than does Si -- in the source and drain regions which it spans

� SRAM -- A type of computer memory (static random access memory) that uses six or more transistors to store each bit of information. It can be written to and read from very quickly.

� STT-MRAM – An acronym for spin torque transfer magnetic random access memory, an emerging type of non-volatile memory that operates according to the “spin” state of electrons, not their electric charge. STT-MRAMs can be made extremely small.

� TDC, or Time-to-Digital Converter – A device for recognizing events and providing a digital representation of the time they occurred.

� Transistor -- A tiny electrical switch that serves as the building block for integrated circuits. It has no moving parts and is made with a semiconductor material, usually silicon. Transistors can be ganged together by the billions on chips and programmed to receive, process and store information, and to output information and/or control signals.

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