TIQ COMPARATOR
TIQ COMPARATORFlash type ADCPresented by:SatishSandeepMalvika
SinghMadhur GoelKuldeep Kumar
Coordinator:Neerja Singh(Asst. Prof.)
Contents: IntroductionConventional flash type ADCTIQ based flash
type ADCTIQ comparator Features of TIQ based ADCAdvantages of TIQ
based flash type ADCTechnique usedDC AnalysisTransient
AnalysisObservationFuture prospects .
Introduction The flash ADC architecture has high speed
conversion due to its parallel structure. Needs a large number of
comparators as the resolution increases.
A 3-bit flash ADC needs 7 comparators, but 63 comparators are
needed for a 6-bit flash ADC.
This exponentially increasing number of comparator requires a
large die size and a large amount of power consumption.
Conventional flash type ADC
TIQ based flash type ADCThe flash ADC features (TIQ) technique
for high speed and low power using standard CMOS technology.
The TIQ based flash ADC operates on power supply voltage of
0.7V.
The use of four cascading inverters as a voltage comparator is
the reason for the techniques name.
The voltage comparators compare the input voltage with internal
reference voltages. Which are determined by the transistor sizes of
the inverters.
Hence, resistor ladder circuit is not used.
TIQ Based Flash type ADC
TIQ
ComparatorVr_+VinVinVinVrVthVoutVoutVoutVinVoutVthDIFFERENTIAL
INPUTVOLTAGE COMPARATORINVERTERVr is provided by a voltage
references source,External to the voltage comparatorVth is an
internal parameter of an inverter,fixed by the transistor
sizesFeatures of TIQ based ADCIncreased resolution
High Speed
Relatively small area
Relatively Low Power Consumption
Advantages of TIQ based flash type ADCIt eliminates the need of
reference voltages which require a resistor ladder circuit.
Here, threshold voltage of an inverter acts as reference
voltage.
Eliminates the need of high gain differential input voltage
comparators that are more complex and slower
Comparison operation speed is faster.
Techniques UsedIn order to achieve minimum propagation
delay:Increase the sinking and sourcing current.This can be
achieved by : Making the width of PMOS and NMOS large.So in this
work transistor sizing is used to achieve minimum delay.We used W/L
>1
DC Analysis
Transient Analysis
ObservationNMOSPMOSTHRESHOLD VOLTAGE
W (nm)L (nm)W (nm)L (nm)(Vth)1009095900.99 V10090120901.01
V10090170901.012 VNMOSPMOSRise Time Fall Time Delay Time
W(nm)L(nm)W(nm)L(nm)(Tr)(psec)(Tf)(psec)(Td)(nsec)100909590409.632160.00129
0.19 10090120906.40265 160.00311 0.18 10090170906.40248
320.002440.15 DC ANALYSISTRANSIENT ANALYSISFormulae Used:
where, Wp = PMOS width, Wn = NMOS width, VDD =supply voltage,
Vtn = NMOS threshold voltage, Vtp = PMOS threshold voltage, n =
electron mobility, p = hole mobility.PMOS length = NMOS
length(assumed).where ==charge-carrier effective mobility,W=gate
width, L=gate length andCox=gate oxide capacitance per unit
area
td=C Vdd/IdFuture ProspectsWe will be using Logical Efforts a
method to determine minimum prop. delay prior to simulation for
cascaded inverters .We will design the TIQ individual comparators
in particular (W/L>1) ratios.
