Tiva C Series TM4C1294NCPDT Microcontroller Data Sheet ...profesores.fi-b.unam.mx/vicflo/Microprocesadores/Manuales/tm4c1294ncpdt.pdf5.2.4 PowerControl.....229 5.2.5 ClockControl.....230

Tiva™ TM4C1294NCPDT Microcontroller

DATA SHEET

Copyr ight © 2007-2014Texas Instruments Incorporated

DS-TM4C1294NCPDT-15863.2743SPMS433B

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

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June 18, 20142Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 45About This Document .................................................................................................................... 48Audience .............................................................................................................................................. 48About This Manual ................................................................................................................................ 48Related Documents ............................................................................................................................... 48Documentation Conventions .................................................................................................................. 49

1 Architectural Overview .......................................................................................... 511.1 Tiva™ C Series Overview .............................................................................................. 511.2 TM4C1294NCPDT Microcontroller Overview .................................................................. 521.3 TM4C1294NCPDT Microcontroller Features ................................................................... 551.3.1 ARM Cortex-M4F Processor Core .................................................................................. 551.3.2 On-Chip Memory ........................................................................................................... 571.3.3 External Peripheral Interface ......................................................................................... 591.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 611.3.5 Serial Communications Peripherals ................................................................................ 611.3.6 System Integration ........................................................................................................ 671.3.7 Advanced Motion Control ............................................................................................... 741.3.8 Analog .......................................................................................................................... 761.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 781.3.10 Packaging and Temperature .......................................................................................... 781.4 TM4C1294NCPDT Microcontroller Hardware Details ....................................................... 781.5 Kits .............................................................................................................................. 791.6 Support Information ....................................................................................................... 79

2 The Cortex-M4F Processor ................................................................................... 802.1 Block Diagram .............................................................................................................. 812.2 Overview ...................................................................................................................... 822.2.1 System-Level Interface .................................................................................................. 822.2.2 Integrated Configurable Debug ...................................................................................... 822.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 832.2.4 Cortex-M4F System Component Details ......................................................................... 832.3 Programming Model ...................................................................................................... 842.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 842.3.2 Stacks .......................................................................................................................... 852.3.3 Register Map ................................................................................................................ 852.3.4 Register Descriptions .................................................................................................... 872.3.5 Exceptions and Interrupts ............................................................................................ 1032.3.6 Data Types ................................................................................................................. 1032.4 Memory Model ............................................................................................................ 1032.4.1 Memory Regions, Types and Attributes ......................................................................... 1062.4.2 Memory System Ordering of Memory Accesses ............................................................ 1072.4.3 Behavior of Memory Accesses ..................................................................................... 1072.4.4 Software Ordering of Memory Accesses ....................................................................... 1082.4.5 Bit-Banding ................................................................................................................. 1092.4.6 Data Storage .............................................................................................................. 1112.4.7 Synchronization Primitives ........................................................................................... 112

3June 18, 2014Texas Instruments-Production Data


2.5 Exception Model ......................................................................................................... 1132.5.1 Exception States ......................................................................................................... 1142.5.2 Exception Types .......................................................................................................... 1142.5.3 Exception Handlers ..................................................................................................... 1192.5.4 Vector Table ................................................................................................................ 1192.5.5 Exception Priorities ...................................................................................................... 1202.5.6 Interrupt Priority Grouping ............................................................................................ 1202.5.7 Exception Entry and Return ......................................................................................... 1202.6 Fault Handling ............................................................................................................. 1232.6.1 Fault Types ................................................................................................................. 1242.6.2 Fault Escalation and Hard Faults .................................................................................. 1242.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1252.6.4 Lockup ....................................................................................................................... 1252.7 Power Management .................................................................................................... 1262.7.1 Entering Sleep Modes ................................................................................................. 1262.7.2 Wake Up from Sleep Mode .......................................................................................... 1262.8 Instruction Set Summary .............................................................................................. 127

3 Cortex-M4 Peripherals ......................................................................................... 1343.1 Functional Description ................................................................................................. 1343.1.1 System Timer (SysTick) ............................................................................................... 1353.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1363.1.3 System Control Block (SCB) ........................................................................................ 1373.1.4 Memory Protection Unit (MPU) ..................................................................................... 1373.1.5 Floating-Point Unit (FPU) ............................................................................................. 1423.2 Register Map .............................................................................................................. 1463.3 System Timer (SysTick) Register Descriptions .............................................................. 1493.4 NVIC Register Descriptions .......................................................................................... 1533.5 System Control Block (SCB) Register Descriptions ........................................................ 1633.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1923.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 201

4 JTAG Interface ...................................................................................................... 2074.1 Block Diagram ............................................................................................................ 2084.2 Signal Description ....................................................................................................... 2084.3 Functional Description ................................................................................................. 2094.3.1 JTAG Interface Pins ..................................................................................................... 2094.3.2 JTAG TAP Controller ................................................................................................... 2114.3.3 Shift Registers ............................................................................................................ 2124.3.4 Operational Considerations .......................................................................................... 2124.4 Initialization and Configuration ..................................................................................... 2154.5 Register Descriptions .................................................................................................. 2154.5.1 Instruction Register (IR) ............................................................................................... 2164.5.2 Data Registers ............................................................................................................ 217

5 System Control ..................................................................................................... 2205.1 Signal Description ....................................................................................................... 2205.2 Functional Description ................................................................................................. 2205.2.1 Device Identification .................................................................................................... 2205.2.2 Reset Control .............................................................................................................. 2215.2.3 Non-Maskable Interrupt ............................................................................................... 228


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5.2.4 Power Control ............................................................................................................. 2295.2.5 Clock Control .............................................................................................................. 2305.2.6 System Control ........................................................................................................... 2395.3 Initialization and Configuration ..................................................................................... 2465.4 Register Map .............................................................................................................. 2475.5 System Control Register Descriptions (System Control Offset) ....................................... 254

6 Processor Support and Exception Module ........................................................ 5236.1 Functional Description ................................................................................................. 5236.2 Register Map .............................................................................................................. 5236.3 Register Descriptions .................................................................................................. 523

7 Hibernation Module .............................................................................................. 5317.1 Block Diagram ............................................................................................................ 5337.2 Signal Description ....................................................................................................... 5337.3 Functional Description ................................................................................................. 5347.3.1 Register Access Timing ............................................................................................... 5357.3.2 Hibernation Clock Source ............................................................................................ 5357.3.3 System Implementation ............................................................................................... 5387.3.4 Battery Management ................................................................................................... 5397.3.5 Real-Time Clock .......................................................................................................... 5397.3.6 Tamper ....................................................................................................................... 5427.3.7 Battery-Backed Memory .............................................................................................. 5457.3.8 Power Control Using HIB ............................................................................................. 5457.3.9 Power Control Using VDD3ON Mode ........................................................................... 5467.3.10 Initiating Hibernate ...................................................................................................... 5467.3.11 Waking from Hibernate ................................................................................................ 5467.3.12 Arbitrary Power Removal ............................................................................................. 5477.3.13 Interrupts and Status ................................................................................................... 5487.4 Initialization and Configuration ..................................................................................... 5487.4.1 Initialization ................................................................................................................. 5487.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5497.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5497.4.4 External Wake-Up from Hibernation .............................................................................. 5507.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5517.4.6 Tamper Initialization ..................................................................................................... 5517.5 Register Map .............................................................................................................. 5517.6 Register Descriptions .................................................................................................. 553

8 Internal Memory ................................................................................................... 6008.1 Block Diagram ............................................................................................................ 6008.2 Functional Description ................................................................................................. 6028.2.1 SRAM ........................................................................................................................ 6028.2.2 ROM .......................................................................................................................... 6028.2.3 Flash Memory ............................................................................................................. 6048.2.4 EEPROM .................................................................................................................... 6158.2.5 Bus Matrix Memory Accesses ...................................................................................... 6218.3 Register Map .............................................................................................................. 6218.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6248.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6508.6 Memory Register Descriptions (System Control Offset) .................................................. 667



9 Micro Direct Memory Access (μDMA) ................................................................ 6789.1 Block Diagram ............................................................................................................ 6799.2 Functional Description ................................................................................................. 6799.2.1 Channel Assignments .................................................................................................. 6809.2.2 Priority ........................................................................................................................ 6819.2.3 Arbitration Size ............................................................................................................ 6829.2.4 Request Types ............................................................................................................ 6829.2.5 Channel Configuration ................................................................................................. 6839.2.6 Transfer Modes ........................................................................................................... 6859.2.7 Transfer Size and Increment ........................................................................................ 6939.2.8 Peripheral Interface ..................................................................................................... 6939.2.9 Software Request ........................................................................................................ 6949.2.10 Interrupts and Errors .................................................................................................... 6949.3 Initialization and Configuration ..................................................................................... 6949.3.1 Module Initialization ..................................................................................................... 6949.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6959.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6969.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6989.3.5 Configuring Channel Assignments ................................................................................ 7019.4 Register Map .............................................................................................................. 7019.5 μDMA Channel Control Structure ................................................................................. 7029.6 μDMA Register Descriptions ........................................................................................ 709

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 74210.1 Signal Description ....................................................................................................... 74310.2 Pad Capabilities .......................................................................................................... 74610.3 Functional Description ................................................................................................. 74710.3.1 Data Control ............................................................................................................... 74810.3.2 Interrupt Control .......................................................................................................... 75010.3.3 Mode Control .............................................................................................................. 75110.3.4 Commit Control ........................................................................................................... 75210.3.5 Pad Control ................................................................................................................. 75210.3.6 Identification ............................................................................................................... 75310.4 Initialization and Configuration ..................................................................................... 75310.5 Register Map .............................................................................................................. 75510.6 Register Descriptions .................................................................................................. 758

11 External Peripheral Interface (EPI) ..................................................................... 81511.1 EPI Block Diagram ...................................................................................................... 81611.2 Signal Description ....................................................................................................... 81711.3 Functional Description ................................................................................................. 81811.3.1 Master Access to EPI .................................................................................................. 81911.3.2 Non-Blocking Reads .................................................................................................... 81911.3.3 DMA Operation ........................................................................................................... 82011.4 Initialization and Configuration ..................................................................................... 82111.4.1 EPI Interface Options .................................................................................................. 82211.4.2 SDRAM Mode ............................................................................................................. 82211.4.3 Host Bus Mode ........................................................................................................... 82611.4.4 General-Purpose Mode ............................................................................................... 84711.5 Register Map .............................................................................................................. 854


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11.6 Register Descriptions .................................................................................................. 856

12 Cyclical Redundancy Check (CRC) .................................................................... 94612.1 Functional Description ................................................................................................. 94612.1.1 CRC Support .............................................................................................................. 94612.2 Initialization and Configuration ..................................................................................... 94812.2.1 CRC Initialization and Configuration ............................................................................. 94812.3 Register Map .............................................................................................................. 94912.4 CRC Module Register Descriptions .............................................................................. 949

13 General-Purpose Timers ...................................................................................... 95513.1 Block Diagram ............................................................................................................ 95613.2 Signal Description ....................................................................................................... 95713.3 Functional Description ................................................................................................. 95813.3.1 GPTM Reset Conditions .............................................................................................. 95913.3.2 Timer Clock Source ..................................................................................................... 95913.3.3 Timer Modes ............................................................................................................... 95913.3.4 Wait-for-Trigger Mode .................................................................................................. 96813.3.5 Synchronizing GP Timer Blocks ................................................................................... 96913.3.6 DMA Operation ........................................................................................................... 97013.3.7 ADC Operation ............................................................................................................ 97013.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 97013.4 Initialization and Configuration ..................................................................................... 97113.4.1 One-Shot/Periodic Timer Mode .................................................................................... 97113.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 97213.4.3 Input Edge-Count Mode ............................................................................................... 97213.4.4 Input Edge Time Mode ................................................................................................. 97313.4.5 PWM Mode ................................................................................................................. 97313.5 Register Map .............................................................................................................. 97413.6 Register Descriptions .................................................................................................. 975

14 Watchdog Timers ............................................................................................... 102814.1 Block Diagram ........................................................................................................... 102914.2 Functional Description ............................................................................................... 102914.2.1 Register Access Timing ............................................................................................. 103014.3 Initialization and Configuration .................................................................................... 103014.4 Register Map ............................................................................................................ 103014.5 Register Descriptions ................................................................................................. 1031

15 Analog-to-Digital Converter (ADC) ................................................................... 105315.1 Block Diagram ........................................................................................................... 105415.2 Signal Description ..................................................................................................... 105515.3 Functional Description ............................................................................................... 105615.3.1 Sample Sequencers .................................................................................................. 105615.3.2 Module Control .......................................................................................................... 105715.3.3 Hardware Sample Averaging Circuit ........................................................................... 106215.3.4 Analog-to-Digital Converter ........................................................................................ 106315.3.5 Differential Sampling .................................................................................................. 106515.3.6 Internal Temperature Sensor ...................................................................................... 106715.3.7 Digital Comparator Unit .............................................................................................. 106815.4 Initialization and Configuration .................................................................................... 1072



15.4.1 Module Initialization ................................................................................................... 107215.4.2 Sample Sequencer Configuration ............................................................................... 107315.5 Register Map ............................................................................................................ 107315.6 Register Descriptions ................................................................................................. 1076

16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 116116.1 Block Diagram ........................................................................................................... 116216.2 Signal Description ..................................................................................................... 116216.3 Functional Description ............................................................................................... 116416.3.1 Transmit/Receive Logic .............................................................................................. 116416.3.2 Baud-Rate Generation ............................................................................................... 116516.3.3 Data Transmission ..................................................................................................... 116616.3.4 Serial IR (SIR) ........................................................................................................... 116616.3.5 ISO 7816 Support ...................................................................................................... 116716.3.6 Modem Handshake Support ....................................................................................... 116816.3.7 9-Bit UART Mode ...................................................................................................... 116916.3.8 FIFO Operation ......................................................................................................... 116916.3.9 Interrupts .................................................................................................................. 117016.3.10 Loopback Operation .................................................................................................. 117116.3.11 DMA Operation ......................................................................................................... 117116.4 Initialization and Configuration .................................................................................... 117216.5 Register Map ............................................................................................................ 117316.6 Register Descriptions ................................................................................................. 1174

17 Quad Synchronous Serial Interface (QSSI) ..................................................... 122617.1 Block Diagram ........................................................................................................... 122617.2 Signal Description ..................................................................................................... 122717.3 Functional Description ............................................................................................... 122817.3.1 Bit Rate Generation ................................................................................................... 122917.3.2 FIFO Operation ......................................................................................................... 122917.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 123017.3.4 SSInFSS Function ..................................................................................................... 123117.3.5 High Speed Clock Operation ...................................................................................... 123217.3.6 Interrupts .................................................................................................................. 123217.3.7 Frame Formats ......................................................................................................... 123317.3.8 DMA Operation ......................................................................................................... 124017.4 Initialization and Configuration .................................................................................... 124017.4.1 Enhanced Mode Configuration ................................................................................... 124217.5 Register Map ............................................................................................................ 124317.6 Register Descriptions ................................................................................................. 1244

18 Inter-Integrated Circuit (I2C) Interface .............................................................. 127518.1 Block Diagram ........................................................................................................... 127618.2 Signal Description ..................................................................................................... 127718.3 Functional Description ............................................................................................... 127818.3.1 I2C Bus Functional Overview ...................................................................................... 127818.3.2 Available Speed Modes ............................................................................................. 128418.3.3 Interrupts .................................................................................................................. 128618.3.4 Loopback Operation .................................................................................................. 128718.3.5 FIFO and µDMA Operation ........................................................................................ 128718.3.6 Command Sequence Flow Charts .............................................................................. 1289


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18.4 Initialization and Configuration .................................................................................... 129718.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 129718.4.2 Configure the I2C Master to High Speed Mode ............................................................ 129818.5 Register Map ............................................................................................................ 129918.6 Register Descriptions (I2C Master) .............................................................................. 130118.7 Register Descriptions (I2C Slave) ............................................................................... 133018.8 Register Descriptions (I2C Status and Control) ............................................................ 1347

19 Controller Area Network (CAN) Module ........................................................... 135619.1 Block Diagram ........................................................................................................... 135719.2 Signal Description ..................................................................................................... 135719.3 Functional Description ............................................................................................... 135819.3.1 Initialization ............................................................................................................... 135919.3.2 Operation .................................................................................................................. 135919.3.3 Transmitting Message Objects ................................................................................... 136019.3.4 Configuring a Transmit Message Object ...................................................................... 136119.3.5 Updating a Transmit Message Object ......................................................................... 136219.3.6 Accepting Received Message Objects ........................................................................ 136219.3.7 Receiving a Data Frame ............................................................................................ 136319.3.8 Receiving a Remote Frame ........................................................................................ 136319.3.9 Receive/Transmit Priority ........................................................................................... 136319.3.10 Configuring a Receive Message Object ...................................................................... 136419.3.11 Handling of Received Message Objects ...................................................................... 136519.3.12 Handling of Interrupts ................................................................................................ 136719.3.13 Test Mode ................................................................................................................. 136819.3.14 Bit Timing Configuration Error Considerations ............................................................. 137019.3.15 Bit Time and Bit Rate ................................................................................................. 137019.3.16 Calculating the Bit Timing Parameters ........................................................................ 137219.4 Register Map ............................................................................................................ 137519.5 CAN Register Descriptions ......................................................................................... 1376

20 Ethernet Controller ............................................................................................ 140720.1 Block Diagram ........................................................................................................... 140820.2 Signal Description ..................................................................................................... 140820.3 Functional Description ............................................................................................... 140920.3.1 Ethernet Clock Control ............................................................................................... 140920.3.2 DMA Controller ......................................................................................................... 141020.3.3 TX/RX Controller ....................................................................................................... 143420.3.4 MAC Operation ......................................................................................................... 143820.3.5 IEEE 1588 and Advanced Timestamp Function ........................................................... 144020.3.6 Frame Filtering .......................................................................................................... 144920.3.7 Source Address, VLAN, and CRC Insertion, Replacement or Deletion .......................... 145020.3.8 Checksum Offload Engine .......................................................................................... 145220.3.9 MAC Management Counters ...................................................................................... 145320.3.10 Power Management Module ....................................................................................... 145420.3.11 Serial Management Interface ..................................................................................... 145720.3.12 Interrupt Configuration ............................................................................................... 145720.4 Ethernet PHY ............................................................................................................ 145720.4.1 Integrated PHY Block Diagram ................................................................................... 145720.4.2 Functional Description ............................................................................................... 1458



20.4.3 Interface Configuration ............................................................................................... 146320.5 Initialization and Configuration .................................................................................... 146420.5.1 Ethernet PHY Initialization .......................................................................................... 146520.6 Register Map ............................................................................................................ 146720.7 Ethernet MAC Register Descriptions ........................................................................... 147020.8 Ethernet PHY Register Descriptions ........................................................................... 1589

21 Universal Serial Bus (USB) Controller ............................................................. 164421.1 Block Diagram ........................................................................................................... 164521.2 Signal Description ..................................................................................................... 164521.3 Register Map ............................................................................................................ 1646

22 Analog Comparators .......................................................................................... 165322.1 Block Diagram ........................................................................................................... 165422.2 Signal Description ..................................................................................................... 165422.3 Functional Description ............................................................................................... 165522.3.1 Internal Reference Programming ................................................................................ 165622.4 Initialization and Configuration .................................................................................... 165822.5 Register Map ............................................................................................................ 165922.6 Register Descriptions ................................................................................................. 1659

23 Pulse Width Modulator (PWM) .......................................................................... 166923.1 Block Diagram ........................................................................................................... 167023.2 Signal Description ..................................................................................................... 167223.3 Functional Description ............................................................................................... 167223.3.1 Clock Configuration ................................................................................................... 167223.3.2 PWM Timer ............................................................................................................... 167223.3.3 PWM Comparators .................................................................................................... 167323.3.4 PWM Signal Generator .............................................................................................. 167423.3.5 Dead-Band Generator ............................................................................................... 167523.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 167523.3.7 Synchronization Methods .......................................................................................... 167623.3.8 Fault Conditions ........................................................................................................ 167723.3.9 Output Control Block .................................................................................................. 167823.4 Initialization and Configuration .................................................................................... 167823.5 Register Map ............................................................................................................ 167923.6 Register Descriptions ................................................................................................. 1682

24 Quadrature Encoder Interface (QEI) ................................................................. 174824.1 Block Diagram ........................................................................................................... 174824.2 Signal Description ..................................................................................................... 175024.3 Functional Description ............................................................................................... 175024.4 Initialization and Configuration .................................................................................... 175324.5 Register Map ............................................................................................................ 175324.6 Register Descriptions ................................................................................................. 1754

25 Pin Diagram ........................................................................................................ 177126 Signal Tables ...................................................................................................... 177226.1 Signals by Pin Number .............................................................................................. 177326.2 Signals by Signal Name ............................................................................................. 178526.3 Signals by Function, Except for GPIO ......................................................................... 179726.4 GPIO Pins and Alternate Functions ............................................................................ 1808


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26.5 Possible Pin Assignments for Alternate Functions ....................................................... 181126.6 Connections for Unused Signals ................................................................................. 1816

27 Electrical Characteristics .................................................................................. 181827.1 Maximum Ratings ...................................................................................................... 181827.2 Operating Characteristics ........................................................................................... 181927.3 Recommended Operating Conditions ......................................................................... 182027.3.1 DC Operating Conditions ........................................................................................... 182027.3.2 Recommended GPIO Operating Characteristics .......................................................... 182027.4 Load Conditions ........................................................................................................ 182327.5 JTAG and Boundary Scan .......................................................................................... 182427.6 Power and Brown-Out ............................................................................................... 182627.6.1 VDDA Levels .............................................................................................................. 182627.6.2 VDD Levels ................................................................................................................ 182727.6.3 VDDC Levels .............................................................................................................. 182827.6.4 Response ................................................................................................................. 182927.7 Reset ........................................................................................................................ 183127.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 183427.9 Clocks ...................................................................................................................... 183527.9.1 PLL Specifications ..................................................................................................... 183527.9.2 PIOSC Specifications ................................................................................................ 183727.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 183727.9.4 Hibernation Clock Source Specifications ..................................................................... 183727.9.5 Main Oscillator Specifications ..................................................................................... 183827.9.6 System Clock Specification with ADC Operation .......................................................... 184227.9.7 System Clock Specification with USB Operation .......................................................... 184227.10 Sleep Modes ............................................................................................................. 184327.11 Hibernation Module ................................................................................................... 184527.12 Flash Memory ........................................................................................................... 184727.13 EEPROM .................................................................................................................. 184827.14 Input/Output Pin Characteristics ................................................................................. 184927.14.1 Types of I/O Pins and ESD Protection ......................................................................... 185127.15 External Peripheral Interface (EPI) .............................................................................. 185327.16 Analog-to-Digital Converter (ADC) .............................................................................. 186127.17 Synchronous Serial Interface (SSI) ............................................................................. 186727.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 187027.19 Ethernet Controller .................................................................................................... 187127.19.1 DC Characteristics .................................................................................................... 187127.19.2 Clock Characteristics ................................................................................................. 187127.19.3 AC Characteristics ..................................................................................................... 187227.20 Universal Serial Bus (USB) Controller ......................................................................... 187527.21 Analog Comparator ................................................................................................... 187727.22 Pulse-Width Modulator (PWM) ................................................................................... 187927.23 Current Consumption ................................................................................................ 1880

A Package Information .......................................................................................... 1885A.1 Orderable Devices ..................................................................................................... 1885A.2 Device Nomenclature ................................................................................................ 1885A.3 Device Markings ........................................................................................................ 1885A.4 Packaging Diagram ................................................................................................... 1887



List of FiguresFigure 1-1. Tiva™ TM4C1294NCPDT Microcontroller High-Level Block Diagram ....................... 54Figure 2-1. CPU Block Diagram ............................................................................................. 82Figure 2-2. TPIU Block Diagram ............................................................................................ 83Figure 2-3. Cortex-M4F Register Set ...................................................................................... 86Figure 2-4. Bit-Band Mapping .............................................................................................. 111Figure 2-5. Data Storage ..................................................................................................... 112Figure 2-6. Vector Table ...................................................................................................... 119Figure 2-7. Exception Stack Frame ...................................................................................... 122Figure 3-1. SRD Use Example ............................................................................................. 140Figure 3-2. FPU Register Bank ............................................................................................ 143Figure 4-1. JTAG Module Block Diagram .............................................................................. 208Figure 4-2. Test Access Port State Machine ......................................................................... 212Figure 4-3. IDCODE Register Format ................................................................................... 218Figure 4-4. BYPASS Register Format ................................................................................... 218Figure 4-5. Boundary Scan Register Format ......................................................................... 218Figure 5-1. Basic RST Configuration .................................................................................... 224Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 224Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 224Figure 5-4. Power Architecture ............................................................................................ 229Figure 5-5. Main Clock Tree ................................................................................................ 233Figure 5-6. Module Clock Selection ...................................................................................... 242Figure 7-1. Hibernation Module Block Diagram ..................................................................... 533Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 537Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 537Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 538Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 542Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 542Figure 7-7. Tamper Block Diagram ....................................................................................... 542Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 543Figure 8-1. Internal Memory Block Diagram .......................................................................... 601Figure 8-2. Flash Memory Configuration ............................................................................... 605Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 606Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 606Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 607Figure 8-6. Prefetch Fills from Flash ..................................................................................... 608Figure 8-7. Mirror Mode Function ......................................................................................... 609Figure 9-1. μDMA Block Diagram ......................................................................................... 679Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 686Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 688Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 689Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 691Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 692Figure 10-1. Digital I/O Pads ................................................................................................. 747Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 748Figure 10-3. GPIODATA Write Example ................................................................................. 749


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Figure 10-4. GPIODATA Read Example ................................................................................. 749Figure 11-1. EPI Block Diagram ............................................................................................. 817Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 824Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 825Figure 11-4. SDRAM Write Cycle ........................................................................................... 826Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 836Figure 11-6. iRDY Signal Connection ..................................................................................... 836Figure 11-7. PSRAM Burst Read ........................................................................................... 839Figure 11-8. PSRAM Burst Write ........................................................................................... 839Figure 11-9. Read Delay During Refresh Event ...................................................................... 840Figure 11-10. Write Delay During Refresh Event ....................................................................... 841Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 842Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 845Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 845Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 846Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 846Figure 11-16. Continuous Read Mode Accesses ...................................................................... 846Figure 11-17. Write Followed by Read to External FIFO ............................................................ 847Figure 11-18. Two-Entry FIFO ................................................................................................. 847Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 850Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 851Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 851Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 852Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 852Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 852Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 852Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 853Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 853Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 853Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 854Figure 13-1. GPTM Module Block Diagram ............................................................................ 956Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 964Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 965Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 967Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 967Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 968Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 968Figure 13-8. Timer Daisy Chain ............................................................................................. 969Figure 14-1. WDT Module Block Diagram ............................................................................. 1029Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1054Figure 15-2. ADC Module Block Diagram ............................................................................. 1055Figure 15-3. ADC Sample Phases ....................................................................................... 1060Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1060Figure 15-5. Skewed Sampling ............................................................................................ 1061Figure 15-6. Sample Averaging Example .............................................................................. 1063Figure 15-7. ADC Input Equivalency .................................................................................... 1064



Figure 15-8. ADC Voltage Reference ................................................................................... 1064Figure 15-9. ADC Conversion Result ................................................................................... 1065Figure 15-10. Differential Voltage Representation ................................................................... 1067Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1068Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1070Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1071Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1072Figure 16-1. UART Module Block Diagram ........................................................................... 1162Figure 16-2. UART Character Frame .................................................................................... 1165Figure 16-3. IrDA Data Modulation ....................................................................................... 1167Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1227Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1234Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1235Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1236Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1236Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1237Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1238Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1238Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1239Figure 18-1. I2C Block Diagram ........................................................................................... 1276Figure 18-2. I2C Bus Configuration ....................................................................................... 1278Figure 18-3. START and STOP Conditions ........................................................................... 1279Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1279Figure 18-5. R/S Bit in First Byte .......................................................................................... 1280Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1280Figure 18-7. High-Speed Data Format .................................................................................. 1286Figure 18-8. Master Single TRANSMIT ................................................................................ 1290Figure 18-9. Master Single RECEIVE ................................................................................... 1291Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1292Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1293Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1294Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1295Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1296Figure 18-15. Slave Command Sequence .............................................................................. 1297Figure 19-1. CAN Controller Block Diagram .......................................................................... 1357Figure 19-2. CAN Data/Remote Frame ................................................................................. 1358Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1367Figure 19-4. CAN Bit Time ................................................................................................... 1371Figure 20-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1408Figure 20-2. Ethernet MAC and PHY Clock Structure ............................................................ 1410Figure 20-3. Enhanced Transmit Descriptor Structure ........................................................... 1414Figure 20-4. Enhanced Receive Descriptor Structure ............................................................ 1419Figure 20-5. TX DMA Default Operation Using Descriptors .................................................... 1426Figure 20-6. TX DMA OSF Mode Operation Using Descriptors .............................................. 1428Figure 20-7. RX DMA Operation Flow .................................................................................. 1431Figure 20-8. Networked Time Synchronization ...................................................................... 1441Figure 20-9. System Time Update Using Fine Correction Method .......................................... 1443


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Figure 20-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer PathCorrection ....................................................................................................... 1446

Figure 20-11. Wake-Up Frame Filter Register Bank ................................................................ 1454Figure 20-12. Integrated PHY Diagram .................................................................................. 1458Figure 20-13. Interface to Ethernet Jack ................................................................................. 1464Figure 21-1. USB Module Block Diagram ............................................................................. 1645Figure 22-1. Analog Comparator Module Block Diagram ....................................................... 1654Figure 22-2. Structure of Comparator Unit ............................................................................ 1655Figure 22-3. Comparator Internal Reference Structure .......................................................... 1656Figure 23-1. PWM Module Diagram ..................................................................................... 1671Figure 23-2. PWM Generator Block Diagram ........................................................................ 1671Figure 23-3. PWM Count-Down Mode .................................................................................. 1674Figure 23-4. PWM Count-Up/Down Mode ............................................................................. 1674Figure 23-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1675Figure 23-6. PWM Dead-Band Generator ............................................................................. 1675Figure 24-1. QEI Block Diagram .......................................................................................... 1749Figure 24-2. QEI Input Signal Logic ...................................................................................... 1750Figure 24-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1752Figure 25-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1771Figure 27-1. Load Conditions ............................................................................................... 1823Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1825Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1825Figure 27-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1827Figure 27-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1828Figure 27-6. POK Assertion vs VDDC ................................................................................... 1829Figure 27-7. POR-BOR VDD Glitch Response ....................................................................... 1829Figure 27-8. POR-BOR VDD Droop Response ...................................................................... 1830Figure 27-9. Digital Power-On Reset Timing ......................................................................... 1831Figure 27-10. Brown-Out Reset Timing .................................................................................. 1832Figure 27-11. External Reset Timing (RST) ............................................................................ 1832Figure 27-12. Software Reset Timing ..................................................................................... 1832Figure 27-13. Watchdog Reset Timing ................................................................................... 1832Figure 27-14. MOSC Failure Reset Timing ............................................................................. 1833Figure 27-15. Hibernation Module Timing ............................................................................... 1846Figure 27-16. ESD Protection ................................................................................................ 1851Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1852Figure 27-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1854Figure 27-19. SDRAM Read Timing ....................................................................................... 1854Figure 27-20. SDRAM Write Timing ....................................................................................... 1855Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1856Figure 27-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1856Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1857Figure 27-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1857Figure 27-25. General-Purpose Mode Read and Write Timing ................................................. 1858Figure 27-26. PSRAM Single Burst Read ............................................................................... 1859Figure 27-27. PSRAM Single Burst Write ............................................................................... 1860Figure 27-28. ADC External Reference Filtering ..................................................................... 1866Figure 27-29. ADC Input Equivalency .................................................................................... 1866



Figure 27-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer TimingMeasurement .................................................................................................. 1868

Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1868Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1869Figure 27-33. I2C Timing ....................................................................................................... 1870Figure 27-34. MOSC Crystal Characteristics for Ethernet ........................................................ 1871Figure 27-35. Single-Ended MOSC Characteristics for Ethernet .............................................. 1872Figure 27-36. Reset Timing ................................................................................................... 1872Figure 27-37. 100 Base-TX Transmit Timing ........................................................................... 1873Figure 27-38. 10Base-TX Normal Link Pulse Timing ............................................................... 1873Figure 27-39. Auto-Negotiation Fast Link Pulse Timing ........................................................... 1874Figure 27-40. 100Base-TX Signal Detect Timing ..................................................................... 1874Figure 27-41. ULPI Interface Timing Diagram ......................................................................... 1876Figure A-1. Key to Part Numbers ........................................................................................ 1885Figure A-2. TM4C1294NCPDT 128-Pin TQFP Package Diagram ......................................... 1887


Table of Contents

List of TablesTable 1. Revision History .................................................................................................. 45Table 2. Documentation Conventions ................................................................................ 49Table 1-1. TM4C1294NCPDT Microcontroller Features .......................................................... 52Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 85Table 2-2. Processor Register Map ....................................................................................... 86Table 2-3. PSR Register Combinations ................................................................................. 92Table 2-4. Memory Map ..................................................................................................... 103Table 2-5. Memory Access Behavior ................................................................................... 107Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 109Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 109Table 2-8. Exception Types ................................................................................................ 115Table 2-9. Interrupts .......................................................................................................... 116Table 2-10. Exception Return Behavior ................................................................................. 123Table 2-11. Faults ............................................................................................................... 124Table 2-12. Fault Status and Fault Address Registers ............................................................ 125Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 127Table 3-1. Core Peripheral Register Regions ....................................................................... 134Table 3-2. Memory Attributes Summary .............................................................................. 138Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 140Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 141Table 3-5. AP Bit Field Encoding ........................................................................................ 141Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 142Table 3-7. QNaN and SNaN Handling ................................................................................. 145Table 3-8. Peripherals Register Map ................................................................................... 146Table 3-9. Interrupt Priority Levels ...................................................................................... 171Table 3-10. Example SIZE Field Values ................................................................................ 199Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 208Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 210Table 4-3. JTAG Instruction Register Commands ................................................................. 216Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 220Table 5-2. Reset Sources ................................................................................................... 221Table 5-3. Clock Source Options ........................................................................................ 231Table 5-4. Clock Source State Following POR ..................................................................... 231Table 5-5. System Clock Frequency ................................................................................... 235Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 237Table 5-7. Actual PLL Frequency ........................................................................................ 238Table 5-8. Peripheral Memory Power Control ...................................................................... 243Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 244Table 5-10. MOSC Configurations ........................................................................................ 247Table 5-11. System Control Register Map ............................................................................. 247Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 277Table 5-13. MOSC Configurations ........................................................................................ 281Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 300Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 303Table 5-16. Module Power Control ........................................................................................ 451Table 5-17. Module Power Control ........................................................................................ 453



Table 5-18. Module Power Control ........................................................................................ 456Table 5-19. Module Power Control ........................................................................................ 461Table 5-20. Module Power Control ........................................................................................ 463Table 5-21. Module Power Control ........................................................................................ 465Table 5-22. Module Power Control ........................................................................................ 467Table 5-23. Module Power Control ........................................................................................ 470Table 5-24. Module Power Control ........................................................................................ 472Table 5-25. Module Power Control ........................................................................................ 476Table 5-26. Module Power Control ........................................................................................ 478Table 5-27. Module Power Control ........................................................................................ 480Table 5-28. Module Power Control ........................................................................................ 482Table 5-29. Module Power Control ........................................................................................ 484Table 5-30. Module Power Control ........................................................................................ 486Table 5-31. Module Power Control ........................................................................................ 488Table 5-32. Module Power Control ........................................................................................ 490Table 5-33. Module Power Control ........................................................................................ 492Table 5-34. Module Power Control ........................................................................................ 494Table 6-1. System Exception Register Map ......................................................................... 523Table 7-1. Hibernate Signals (128TQFP) ..........................................