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Application ReportSLVA531A–February 2013–Revised September 2013
TLK1XX Design and Layout Guide
Aviad Yarmakov....................................................................................................... Industrial Interface
ABSTRACTMany times when approaching a new design, significant time and effort can be saved by applying correctand recommended design guidelines already in the planning phase. The purpose of this document is tosupply these guidelines to the engineer working with the TLK family of products; saving time, effort, andcost, and decreasing time to market for their solution.
Contents1 Introduction .................................................................................................................. 32 MDI (TP/CAT-V) Connections ............................................................................................. 4
2.1 RJ-45 Connections ................................................................................................ 42.2 ESD EMI EMC Recommendations .............................................................................. 42.3 Fiber Optic Implementations ...................................................................................... 5
3 Power Supply ................................................................................................................ 63.1 Filtering .............................................................................................................. 63.2 Single-Supply Operation .......................................................................................... 73.3 Dual-Supply Operation ............................................................................................ 83.4 I/O Voltage Supply ................................................................................................. 83.5 CT Supply ........................................................................................................... 8
4 MAC Interfaces .............................................................................................................. 94.1 Media Independent Interface (MII) ............................................................................... 94.2 Reduced Media Independent Interface (RMII) ................................................................ 104.3 Termination Requirement ....................................................................................... 104.4 Recommended Maximum Trace Length ...................................................................... 11
5 Clock Requirements ....................................................................................................... 115.1 External Oscillator Clock Source ............................................................................... 115.2 Crystal Clock Source ............................................................................................. 125.3 Oscillator or Crystal .............................................................................................. 12
6 LED and Non-LED Strap Pins ........................................................................................... 137 PCB Layout Considerations .............................................................................................. 14
7.1 Calculating Impedance .......................................................................................... 157.2 PCB Layer Stacking .............................................................................................. 16
8 Magnetics ................................................................................................................... 189 ESD Design Guidelines ................................................................................................... 19
9.1 Board Design Guidelines ........................................................................................ 199.2 Board Layout Guidelines ........................................................................................ 20
10 Reset Operation ........................................................................................................... 2210.1 Hardware Reset .................................................................................................. 2210.2 POR_BYPASS mode (TLK110 only) .......................................................................... 2210.3 Software Reset ................................................................................................... 22
11 Schematics Example ...................................................................................................... 2312 Other Applicable Documents ............................................................................................. 29
List of Figures
1 Typical Application .......................................................................................................... 3
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www.ti.com
2 MDI Connection ............................................................................................................ 43 Recommended Magnetics ................................................................................................. 54 Chassis GND and Board GND Separation .............................................................................. 55 VDD Layout ................................................................................................................... 66 Power Connections for Single-Supply Operation ....................................................................... 77 Power Connections for Dual-Supply Operation ........................................................................ 88 MII Signaling ................................................................................................................. 99 RMII/MAC Connection .................................................................................................... 1010 Oscillator Circuit ........................................................................................................... 1111 Crystal Oscillator Circuit .................................................................................................. 1212 Strapping and LED Loading Example .................................................................................. 1313 Differential Signal Pair – Stubs .......................................................................................... 1414 Differential Signal Pair – Plane Crossing............................................................................... 1415 Microstrip Impedance – Single-Ended.................................................................................. 1516 Microstrip Impedance – Differential ..................................................................................... 1517 Stripline Impedance – Single-Ended.................................................................................... 1618 Stripline Impedance – Differential ....................................................................................... 1619 PCB Stripline Layer Stacking ............................................................................................ 1720 Alternative PCB Stripline Layer Stacking............................................................................... 1721 Grounds Separation....................................................................................................... 1922 Decoupling Capacitors.................................................................................................... 2023 Layer Separation .......................................................................................................... 2124 Grounds Layout Separation .............................................................................................. 2125 Schematic 1 of 6........................................................................................................... 2326 Schematic 2 of 6........................................................................................................... 2427 Schematic 3 of 6........................................................................................................... 2528 Schematic 4 of 6........................................................................................................... 2629 Schematic 5 of 6........................................................................................................... 2730 Schematic 6 of 6........................................................................................................... 28
List of Tables
1 25-MHz Oscillator Requirements ........................................................................................ 122 50-MHz Oscillator Requirements ........................................................................................ 123 25-MHz Crystal Requirements........................................................................................... 134 Magnetics Requirements ................................................................................................. 185 Recommended Magnetics................................................................................................ 18
2 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
MPU/CPU
Mode
Access C
ontr
olle
r
MII/RMIITLK110
10/100 Mbps
25/50 MHzClock
Source
StatusLEDs
Magnetics
RJ-4
5 10BASE-Tor
100BASE-TX
www.ti.com Introduction
1 IntroductionThe TLK1XX family of products are robust, full-featured, low-power, 10/100 physical layer devices. Withcable length performance far exceeding IEEE specifications and features that provide lower cost solutions,for both 10BASE-T and 100BASE-TX Ethernet protocols, the devices ensure compatibility andinteroperability with other standards-based Ethernet products in these applications:• High-end peripheral devices• Industrial controls• Factory automation• General embedded applications
Use of this document, in conjunction with product data sheets, application notes, and reference designs,help ensure issue-free system products. In this application note we review: MAC Interface, Physicalmedium interface, Board design, Power supply, Configuration, and Components selection, among othertopics. Product Applicability: TLK110, TLK105, TLK106.
Figure 1. Typical Application
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PHY Device
RD–
RD+
TD–
TD+
49.9 Ω
49.9 Ω
49.9 Ω
49.9 Ω
1 Fµ
1 Fµ
1 Fµ
1 Fµ
Place These Resistors andCapacitors Close to the Device
Note: Center TAP is Pulled to VDD
Transformer Center Taps*Place Capacitors Close to the
100- DifferentialΩ
T11:1 with Common-Mode Choke
01206
Ω
01206
Ω
1500 pF2 kV
Bob-Smith Termination75 EachΩ
RD–
RJ45
RD+
TD–
NC
NC
TD+
NC
NC
3.3 VSupply
3.3 VSupply
3.3 VSupply
0.1 Fµ
0.1 Fµ
0.1 F*µ
0.1 F*µ
100- DifferentialΩ
MDI (TP/CAT-V) Connections www.ti.com
2 MDI (TP/CAT-V) ConnectionsThe network or medium dependent interface (MDI) connection is via the transmit (TD+ & TD–) and receive(RD+ & RD–) differential pair pins. These connect to a termination network, then to 1:1 magnetics(transformer) and an RJ-45. For space savings, the magnetics and RJ-45 may be a single-integratedcomponent. A standard CAT-V Ethernet cable is then used to connect to the rest of the network. Figure 2shows the recommended 10/100 Mb/s twisted pair interface circuit.
Figure 2. MDI Connection
2.1 RJ-45 ConnectionsThe transformer used in the MDI connection provides DC isolation between local circuitry and the networkcable. The center tap of the isolated winding has Bob Smith termination through a 75-Ω resistor and a1000-pF capacitor to chassis ground. The termination capacitor should be rated to a voltage of at least 2kV.
NOTE: Bob-Smith termination does not apply for Power Over Ethernet (PoE) applications.
Bob-Smith termination is used to reduce noise resulting from common mode current flows,as well as reduce susceptibility to any noise from unused wire pairs on the RJ-45. It isdescribed in patent publication US5321372 A.
2.2 ESD EMI EMC RecommendationsThe following recommendations are provided to improve EMI performance:• Use a metal shielded RJ-45 connector, and connect the shield to chassis ground.• Use magnetics with integrated common-mode choking devices with the choke on the side of the PHY
(for example PULSE HX1198).• Do not overlap the circuit and chassis ground planes, keep them isolated. Connect chassis ground and
system ground together using one 4700 pF NPO 2000 V 10% across the void between the groundplanes on the 1, 2 pair side of the RJ-45.
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MAGNETICS
CHA
RJ45_RA
CHB
100NF1UF
I88
CT_INPUT
HX1188NLI41
75 75
I87 I89
I51
10N
F
75
10N
F
I47
THHMTSW-101-07-TM-S-240MECHANICALMC0002R
6116526-1
75
PN0021R
I861UF100NF
I924700PF
1
TP30MIL1
T1
1
2
3
4
5
6
7
8
9
10
U2
21
R8
12
C8
21
R7
21
R6
12
C7
21
R5 2
1 C14
21 C9
21 C15
21 C10
12
C16
GND_PIN10
GND_PIN9
I/0_PIN8
I/0_PIN7
I/0_PIN6
I/0_PIN5
I/0_PIN4
I/0_PIN3
I/0_PIN2
I/0_PIN1
H1102
TX_P16
TX_P15
TX_P14
NC_P13
RX_P8
TX_P3
RX_P10
RX_P11
NC_P12 NC_P5
NC_P4
RX_P7
RX_P6
TX_P2
TX_P1
RX_P9
IN
1:1
1:1
11
16
10
15
7
2
6
1
8
3
9
14
RECEIVE
www.ti.com MDI (TP/CAT-V) Connections
Figure 3. Recommended Magnetics
Figure 4. Chassis GND and Board GND Separation
2.3 Fiber Optic ImplementationsSome TLK1XX family products utilize the MDI interface to connect to fiber optic transceivers. Individualdevice datasheets describe how to terminate the MDI signals when enabling fiber mode in these devices.
Although the termination requirements for fiber mode operation differ from the termination requirements oftwisted pair operation, the characteristic impedance of the terminations and the associated signal tracesare the same. Therefore, the same MDI signal routing recommendations described in Section 7 apply toFiber-enabled systems as well.
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PCBVia
PHYComponent
Optional 0 Ω
PCB Via
Ground Pin
V PinDD1 nF10 nF10 Fµ 100 pF
3.3 VSupply
Power Supply www.ti.com
3 Power Supply
3.1 FilteringBypass the power rails with the following low-impedance surface mount capacitors: 10 µF, 10 nF, 1 nF, an100 pF. To reduce EMI, place the capacitors as close as possible to the component VDD supply pins,preferably between the supply pins and the vias connecting to the power plane. In some systems it maybe desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if addingEMI beads becomes necessary to meet system level certification testing requirements, see Figure 5.
It is recommended the PCB have at least one solid ground plane and one solid VDD plane to provide a lowimpedance power source to the component. This also provides a low impedance return path for non-differential digital MII and clock signals. (See Figure 5.)
Place a 10.0-μF capacitor near the PHY component for local bulk bypassing between the VDD and groundplanes. The rise time of the VDD should be typically 500 µs.
Figure 5. VDD Layout
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3.3-VSupply
3.3-VSupply
AVDD33
PFBOUT
PFBIN1
PFBIN2
0.1 µF
10 µF0.1 µF
VDD33_IO
TD+
TD
RD
RD+
49.9 Ω
49.9 Ω
0.1 µF
1:1 T1
1:1
RD
RD+
TD+
TD
RJ45
1 Fµ
1 Fµ
3.3-VSupply
0.1 Fµ
0.1 Fµ
1 nF
10 nF
10 nF
1 nF
10 Fµ
100 pF 10 Fµ
100 pF
VDD33_IO
49.9 Ω
49.9 Ω
1 Fµ
3.3-VSupply
0.1 Fµ
1 Fµ 0.1 Fµ
3.3-VSupply
10 nF1 nF100 pF 10 Fµ
www.ti.com Power Supply
3.2 Single-Supply OperationIf a single 3.3-V power supply is desired, the TLK10x internal regulator provides the necessary coresupply voltages. Place 10-μF and 0.1-μF ceramic capacitors close to the PFBOUT pin, the output of theinternal regulator. Connect the PFBOUT pin to the PFBIN1 and PFBIN2 pins. Put a 0.1-μF capacitor closeto the PFBIN1 and PFBIN2 pins. To operate in this mode, connect the TLK10x supply pins as shown inFigure 6.
Figure 6. Power Connections for Single-Supply Operation
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3.3-VSupply
1.55-VSupply
3.3-VSupply
AVDD33
PFBOUT
PFBIN1
PFBIN2
VDD33_IO
TD+
TD
RD
RD+
Floating
49.9 Ω
49.9 Ω
1:1 T1
1:1
RD
RD+
TD+
TD
RJ45
1 Fµ
1 Fµ
3.3-VSupply
0.1 Fµ
0.1 Fµ
49.9 Ω
49.9 Ω
1 Fµ
3.3-VSupply
0.1 Fµ
1 Fµ 0.1 Fµ
3.3-VSupply
10 nF1 nF100 pF 10 Fµ
Power Supply www.ti.com
3.3 Dual-Supply OperationWhen a 1.55-V external power rail is available on board, the TLK1XX may be configured to work with dualpower supply and thus reduce power consumption in the overall system. The TLK1XX dual supplyconfiguration is shown in Figure 7. PFBOUT is left floating. The 1.55-V external supply is connected toPFBIN1 and PFBIN2. Furthermore, to lower the power consumption, power down the internal regulator bywriting 1 to bit 15 of the VRCR register (0x00d0h).
Figure 7. Power Connections for Dual-Supply Operation
3.4 I/O Voltage SupplyThe TLK1XX I/O's have the flexibility to work with the VDDIO voltage level which is lower than 3.3 V, referto the VDDIO application note for more thorough information.
3.5 CT SupplyIt is recommended to provide a constant power supply to the center tap when connected to a link partner.
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PHY MAC
TX_CLK
TX_EN
TXD [3:0]
RX_CLK
RX_DV
RX_ER
RXD [3:0]
CRS
COL
COL
CRS
RXD [3:0]
RX_ERR
RX_DV
RX_CLK
TXD [3:0]
TX_EN
TX_CLK
www.ti.com MAC Interfaces
4 MAC InterfacesThe TLK1XX family supports both MII and RMII connectivity to the Media Access Controller (MAC). Whenusing MII, the advantages are in the round trip delay of the data transmission of the PHY. The TLK1XXallows MII mode to maintain state-of-the-art, low deterministic round-trip delay, which is a crucial factor formany automated industrial protocols like EtherCAT, PROFINET, and more. For space-critical designs,RMII mode is usually used, due to the reduced number of pins required (save both traces on board andnumber of pins required by host)
4.1 Media Independent Interface (MII)The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects thePHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.The MII signals are summarized below:
Data signals: MII_TXD [3:0]RXD [3:0]
Transmit and receive-valid signals: MII_TX_ENMII_RX_DV
Line-status signals: CRS (carrier sense)COL (collision)
Figure 8. MII Signaling
The isolate register 0.10 defined in IEEE802.3-2002 used to electrically isolate the PHY from the MII (ifSet, all transactions on the MII interface are ignored by the PHY).
Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signalCOL. The CRS signal asserts to indicate the reception of data from the network or as a function ofTransmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occurDuring half-duplex operations when both transmit and receive operation occur simultaneously.
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PHY MAC
TX_CLK
RX_ER
RXD [1:0]
CRS/RX_DV
XI
RX_DV
TX_EN
TXD [1:0]TXD [1:0]
RX_CLK (optional)
RX_CLK
RX_DV (optional)
RX_ER
RXD [1:0]
CRS/RX_DV
50-MHZClock Source
MAC Interfaces www.ti.com
4.2 Reduced Media Independent Interface (RMII)TLK110 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMIIspecification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low costalternative to the IEEE 802.3u [2] MII as specified in Clause 22. Architecturally, the RMII specificationprovides an additional reconciliation layer on either side of the MII, but can be implemented in the absenceof an MII.
The RMII specification has the following characteristics:• It is capable of supporting 10 Mbps and 100 Mbps data rates• A single clock reference is sourced from the MAC to PHY (or from an external source)• It provides independent 2 bit wide (di-bit) transmit and receive data paths
Figure 9. RMII/MAC Connection
4.2.1 MII to RMII Schematic Changes1. Change the OSC to 50 MHz, connect it to PHY (Xi pin) and MAC2. External Pull up MII_MODE (RX_DV) (Pin 39)3. No need to connect PHY and MAC with: TXD[3:2],RXD[3:2], TX_CLK, RX_CLK
If a given design requires both MII and RMII modes of operation, it is recommended to use a single 50-MHz oscillator on board. While in RMII mode, this is the required configuration, for MII mode, by usingregister access, the TLK1XX can be configured to work in MII mode also when the source clock is 50MHz.
4.3 Termination RequirementTo reduce digital signal energy, 33-Ω series termination resistors are recommended for all MII outputsignals (including RXCLK, TXCLK, and RX data signals.
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VDD
RS
RP
X2X1
25/50 MHz
www.ti.com Clock Requirements
4.4 Recommended Maximum Trace LengthAlthough RMII and MII are synchronous bus architectures, there are a number of factors limiting signaltrace lengths. With a longer trace, the signal becomes more attenuated at the destination and thus moresusceptible to noise interference.
Longer traces also act as antennas, and if run on the surface layer, can increase EMI radiation. If a longtrace is running near and adjacent to a noisy signal, the unwanted signals could be coupled in as crosstalk.
It is recommended to keep the signal trace lengths as short as possible. Ideally, keep the traces under 6inches.
Trace length matching, to within 2.0 inches on the MII or RMII bus is also recommended. Significantdifferences in the trace lengths can cause data timing issues.
As with any high-speed data signal, good design practices dictate that impedance should be maintainedand stubs should be avoided throughout the entire data path.
5 Clock RequirementsTLK1XX family products support either an external CMOS level oscillator source or a crystal resonatordevice. The X1 pin is the clock input, requiring either 25 or 50 MHz, depending on the MII/RMII mode.
In MII mode, use either a 25-MHz crystal or 50-MHz oscillator. For RMII mode, only a 50-MHz oscillatorcan be used.
The input clock signal is also buffered and provided as an output signal on some TLK1XX family products.
5.1 External Oscillator Clock SourceIf an oscillator is used, XI should be tied to the clock source and XO should be left floating. No series orload termination is required from the clock source, but may prove beneficial in some circumstances.
For EMI purposes, it may be beneficial to include series termination to limit the energy sourced from theoscillator. If series termination is used, the termination resistor should be placed as close to the oscillatoroutput as possible on the PCB.
For longer traces, series termination coupled with matched parallel termination to ground and matchedtrace impedance may prove beneficial as well. If a parallel termination resistor is used, it should be placedas closely as possible to the XI pin.
Connections for using an oscillator are shown in Figure 10. Specifications for CMOS oscillators are listedin Table 1.
Figure 10. Oscillator Circuit
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CL1
XOXI
R1
CL2
Clock Requirements www.ti.com
5.2 Crystal Clock SourceFor MII mode, the recommended crystal is a 25-MHz, parallel, 20-pF load crystal resonator. Figure 11shows a typical circuit for a crystal resonator. The load capacitor values will vary with the crystal vendors;check with the vendor for load recommendations.
Approximate load capacitor values can be calculated by
2 × Crystal load spec – 7 pF = CL.
The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of100 µW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limitingresistor should be placed in series between XO and the crystal.
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1and CL2 should be set at 33 pF, and R1 should be set at 0 Ω.
Figure 11. Crystal Oscillator Circuit
5.3 Oscillator or CrystalThe parametric specifications for utilizing an external oscillator are shown in Table 1 and Table 2.
The commonly used crystal is AT cut and fundamental frequency. This is the recommended type forTLK1XX components since AT cut exhibits the most frequency stability over a wide temperature range.The requirements for 25-MHz crystals are listed in Table 3.
In the case where multiple clock sources are needed, a high speed PLL clock distribution driver isrecommended. The drivers may be obtained from vendors such as Texas Instruments, Pericom, andIntegrated Device Technology. Consult vendor for specifics.
Table 1. 25-MHz Oscillator RequirementsParameter Test Conditions MIN TYP MAX UnitFrequency 25 MHzFrequency tolerance Operational temperature ±50 ppmFrequency stability 1 year aging ±50 ppmRise/Fall Time 10%–90% 8 nsJitter (short term) Cycle-to-cycle 50 psJitter (long term) Accumulative over 10 ms 1 nsSymmetry Duty cycle 40% 60%Load capacitance 15 30 pF
Table 2. 50-MHz Oscillator RequirementsParameter Test Conditions MIN TYP MAX UnitFrequency 50 MHzFrequency tolerance Operational temperature ±50 ppmFrequency stability 1 year aging ±50 ppmRise/Fall Time 10%–90% 6 ns
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VDD
LED I/O PinStrapped High,Active Low
ConventionInput/OutputStrapped High
ConventionInput/OutputStrapped Low
LED I/O PinStrapped High,Active Low
2.2 kΩ
470 kΩ
2.2 kΩ 2.2 kΩ 2.2 kΩ
470 kΩ
www.ti.com LED and Non-LED Strap Pins
Table 2. 50-MHz Oscillator Requirements (continued)Parameter Test Conditions MIN TYP MAX UnitJitter (short term) Cycle-to-cycle 50 psJitter (long term) Accumulative over 10 ms 1 nsSymmetry Duty cycle 40% 60%Load capacitance xx xx pF
Table 3. 25-MHz Crystal RequirementsParameter Test Conditions MIN TYP MAX UnitFrequency 25 MHzFrequency tolerance Operational temperature ±50 ppm
At 25°C ±50 ppmFrequency stability 1 year aging ±5 ppmLoad capacitance 10 40 pF
6 LED and Non-LED Strap PinsTLK1XX products support both conventional configuration strap input/output pins and multi-purpose LightEmitting Diode (LED) I/O pins. The LED pins can display the status of Link, Speed, Activity, or thepresence of Collisions.
Many conventional strap I/O pins have high impedance (10 k to 20 k) default strap resistors presentinternal to the device. In order to overdrive these internal strap resistors, it is recommended that 2.2 kΩresistors be used for selecting non-default strap options.
Additionally, even though the internal strap resistors are adequate for configuring the device in mostapplications, in some applications with noisy environments it is recommended that additional external 2.2 kstraps be used to select default options as well.
With regard to multi-purpose LED I/O pins, in order to achieve dual input/output functionality, the activestate of each LED output driver is dependent on the input logic level sampled during power-up/reset. Forexample, if a multifunction LED pin is resistively pulled low, then the corresponding output is configured asactive high. Conversely, if an input is resistively pulled high, then the corresponding output is configuredas active low.
Figure 12 illustrates example of both conventional and multipurpose LED pin strap configurations.
Figure 12. Strapping and LED Loading Example
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Do Not Cross Power
or Ground Planes
Ground or Power Plane
Does Not Maintain Parallelism
Avoid
Stubs
Ground or Power Plane
PCB Layout Considerations www.ti.com
7 PCB Layout Considerations• Place the 49.9-Ω,1% resistors, and the decoupling capacitors, near the TLK1XX TD± and RD± pins
and via directly to the VDD plane.• Avoid stubs on all signal traces, especially the differential signal pairs. See Figure 13.• Within the pairs (for example, TD+ & TD–) the trace lengths should be run parallel to each other and
matched in length. Matched lengths minimize delay differences, avoiding an increase in common modenoise and increased EMI. See Figure 13.
• Ideally, there should be no crossover or via on the signal paths. Vias present impedancediscontinuities and should be minimized. Route an entire trace pair on a single layer, if possible.
• Keep PCB trace lengths as short as possible.• Signal traces should not be run such that they cross a plane split. See Figure 14. A signal crossing a
plane split may cause unpredictable return path currents and would likely impact signal quality as well,potentially creating EMI problems.
• MDI signal traces should have 50 Ω to ground or 100-Ω differential controlled impedance. Many toolsare available online to calculate this, two are located here:http://www.emclab.umr.edu/pcbtlc/index.htmlhttp://www.ultracad/articles/diff_z.pdf
Figure 13. Differential Signal Pair – Stubs
Figure 14. Differential Signal Pair – Plane Crossing
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Copyright © 2013, Texas Instruments Incorporated
W
T
H
W S
S
H
0.96
Zdiff 2Zo 1 0.48 e
æ ö-ç ÷
è øæ öæ öç ÷= - ç ÷
ç ÷ç ÷è øè ø
W
T
H
87 HZo 1N 5.98
0.8W TEr (1.41)
æ ö æ ö= ç ÷ ç ÷ç ÷ ++ è øè ø
www.ti.com PCB Layout Considerations
Optimally, we would want to keep all the traces as short as possible. In those cases where it is notpossible, spacings should have the following priority:1. Distance between the PHY and the 50-Ω termination resistors.2. Distance between the magnetic and the RJ-45.3. Distance between the 50-Ω termination resistors and the magnetic.4. Distance between the MAC and the PHY.
This gives the flexibility to make some adjustments, but hopefully minimizes the impact on performance.
7.1 Calculating ImpedanceUse the following equations to calculate the differential impedance of the board.
7.1.1 Microstrip Impedance – Single-ended
(1)
W = Width of the traceH = Height of dielectric above the return planeT = Trace thicknessEr = Relative permittivity of the dielectric
Figure 15. Microstrip Impedance – Single-Ended
7.1.2 Microstrip Impedance – Differential
(2)
W = Width of the traceH = Height of dielectric above the return planeT = Trace thicknessS = Space between tracesEr = Relative permittivity of the dielectric
Figure 16. Microstrip Impedance – Differential
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W S W
H
T
H
S
H
2.9
Zo 2Zo 1 0.347 e
æ ö-ç ÷
è øæ öæ öç ÷= - ç ÷
ç ÷ç ÷è øè ø
W
H
T
H
60 2H TZo Ln 1.9
0.8W TEr
+æ ö= ç ÷+è ø
PCB Layout Considerations www.ti.com
For microstrip traces, a solid ground plane is needed under the signal traces. The ground plane helpskeep the EMI localized and the trace impedance continuous. Since stripline traces are typicallysandwiched between the ground and supply planes, they have the advantage of lower EMI radiation andless noise coupling. The tradeoff of using strip line is a lower propagation speed.
7.1.3 Stripline Impedance – Single-ended
(3)
W = Width of the traceH = Height of the dielectric above the return planeT = Trace thicknessEr = Relative permittivity of the dielectric
Figure 17. Stripline Impedance – Single-Ended
7.1.4 Stripline Impedance – Differential
(4)
W = Width of the traceH = Height of the dielectric above the return planeT = Trace thicknessS = Space between tracesEr = Relative permittivity of the dielectric
Figure 18. Stripline Impedance – Differential
7.2 PCB Layer StackingTo meet signal integrity and performance requirements, at minimum a four layer PCB is recommended forimplementing TLK1XX components in end-user systems. The following layer stack-ups are recommendedfor 4-, 6-, and 8-layer boards, although other options are possible.
16 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Chassis Ground
V SupplyDD
High Speed Signal
Chassis Ground
Chassis Ground
High Speed Signal
V SupplyDD
Chassis Ground
4 Layer
High Speed Signal
Ground
V SupplyDD
High Speed Signal
High Speed Signal
Ground
High Speed Signal
High Speed Signal
V SupplyDD
High Speed Signal
High Speed Signal
Ground
High Speed Signal
V SupplyDD
Ground
High Speed Signal
V Supply/GroundDD
High Speed Signal
6 Layer
8 Layer
www.ti.com PCB Layout Considerations
Figure 19. PCB Stripline Layer Stacking
Within a PCB it may be desirable to run traces using different methods, microstrip vs. stripline, dependingon the location of the signal on the PCB. For example, it may be desirable to change layer stacking wherean isolated chassis ground plane is used. Figure 20 illustrates alternative PCB stacking options.
Figure 20. Alternative PCB Stripline Layer Stacking
17SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Magnetics www.ti.com
8 MagneticsWithin a design, the selection of certain components is very important in respect to the systemperformance. One of the main components among these is the magnetic. The magnetics have a largeimpact on the PHY performance. While several components are listed below, the TLK1XX maintains highperformance with most existing on the shelf magnetics (RJ45 integrated or not), as long as theycompatible with the requirements listed in Table 4. It is recommended that the magnetics include both anisolation transformer and an integrated common mode choke to reduce EMI. When doing the layout, donot run signals under the magnetics. This could cause unwanted noise crosstalk. Likewise, void theplanes under discrete magnetics, helping to prevent common-mode noise coupling. To save board spaceand reduce component count, use an RJ-45 with integrated magnetics.
Table 4. Magnetics RequirementsParameter TYP Units Condition
Turn Ratio 1:1 – ±2%Insertion Loss –1 dB 1–100 MHzReturn Loss –16 dB 1–30 MHz
–12 dB 30–60 MHz–10 dB 60–80 MHz
Differential to common rejection ration –30 dB 1–50 MHz–20 dB 50–150 MHz
Crosstalk –35 dB 30 MHz–30 dB 60 MHz
Isolation 1,500 Vrms HPOT
Recommended magnetics include:
Table 5. Recommended Magnetics (1)
Manufacturer Part NumberPulse Engineering, Inc. HX1188
HX1189(1) Contact magnetics manufacturers for latest part numbers and product specifications. Thoroughly test and validate all magnetics
before using them in production.
18 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
MAGNETICS
CHA
RJ45_RA
CHB
100NF1UF
I88
CT_INPUT
HX1188NLI41
75 75
I87 I89
I51
10N
F
75
10N
F
I47
THHMTSW-101-07-TM-S-240MECHANICALMC0002R
6116526-1
75
PN0021R
I861UF100NF
I924700PF
1
TP30MIL1
T1
1
2
3
4
5
6
7
8
9
10
U2
21
R8
12
C8
21
R7
21
R6
12
C7
21
R5 2
1 C14
21 C9
21 C15
21 C10
12
C16
GND_PIN10
GND_PIN9
I/0_PIN8
I/0_PIN7
I/0_PIN6
I/0_PIN5
I/0_PIN4
I/0_PIN3
I/0_PIN2
I/0_PIN1
H1102
TX_P16
TX_P15
TX_P14
NC_P13
RX_P8
TX_P3
RX_P10
RX_P11
NC_P12 NC_P5
NC_P4
RX_P7
RX_P6
TX_P2
TX_P1
RX_P9
IN
www.ti.com ESD Design Guidelines
9 ESD Design Guidelines
9.1 Board Design GuidelinesThe following list refers to guidelines of the external BOM system:• Capacitors:
– Solder a HV capacitor between RJ45 and the board GND (refer to Figure 21)– Place the capacitor close to lines 1-2 (Channel A).– Capacitor value and DC rating has little effect (1.5–3.9 nF, 2 kV and above were used with no
noticeable difference).– Capacitors on power supplies: 4 caps in parallel, values of 10 µF, 1 µF, 100 nF and 100 pF (refer to
figure Figure 22).• Connect the shielding to earth ground as close to the RJ45 connector.• While TLK supports a large variety of magnetics, it is recommended in some systems to use Pulse's
H1198 magnetic (Opposite iso-magnetic architecture in comparison to H1188) with RJ45 withoutmagnetic.
Figure 21. Grounds Separation
19SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
3.3-VSupply
3.3-VSupply
AVDD33
PFBOUT
PFBIN1
PFBIN2
0.1 µF
10 µF0.1 µF
VDD33_IO
TD+
TD
RD
RD+
49.9 Ω
49.9 Ω
0.1 µF
1:1 T1
1:1
RD
RD+
TD+
TD
RJ45
1 Fµ
1 Fµ
3.3-VSupply
0.1 Fµ
0.1 Fµ
1 nF
10 nF
10 nF
1 nF
10 Fµ
100 pF 10 Fµ
100 pF
VDD33_IO
49.9 Ω
49.9 Ω
1 Fµ
3.3-VSupply
0.1 Fµ
1 Fµ 0.1 Fµ
3.3-VSupply
10 nF1 nF100 pF 10 Fµ
ESD Design Guidelines www.ti.com
Figure 22. Decoupling Capacitors
9.2 Board Layout GuidelinesBoard layout can make extensive enhancements to ESD immunity. To meet signal integrity andperformance requirements, at minimum, a four-layer PCB is recommended for implementing TLK1XXcomponents in end-user systems. Refer to Figure 19 for layer stack-ups.
It is strongly recommended to separate the chassis and main ground by layer, as seen in Figure 23.
20 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Board GND Ground Gap
Width for HV Cap
RJ45
ChassisGND
Gap Should Include Magnetic
Design Consideration
Component Side
Main Ground Layer
Chassis Ground Layer
No Other Ground on this Layer
Chassis Ground
Ground Clearing
Ground Clearing
RJ45 Top Layer
Bottom Layer
Intermediate Layer(Main Ground Layer)
Max Possible Layer Separation
Minimum 1 Layer
www.ti.com ESD Design Guidelines
Figure 23. Layer Separation
Grounds and supplies should each have their own dedicated layer.
Please note, if one-layer separation was not possible after all (less recommended), and the RJ45 andmain ground are on the same layer, they should be spaced as much as possible – at least 256 mil. Pleasesee Figure 24.
Figure 24. Grounds Layout Separation
The RJ45 ground must be hooked to enable direct connection from the board to the earth ground (thisshould be the ground connected to the earth ground during ESD test).
21SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Reset Operation www.ti.com
10 Reset OperationTLK1XX products include an internal POR function and do not need to be explicitly reset after power up(except for the TLK100), for normal operation. If required during normal operation, the device can be resetby a hardware or a software reset.
10.1 Hardware ResetA hardware reset (HW reset) is accomplished by applying a low pulse (CMOS level), with a duration of atleast 1 µS, to the RESET_N. This resets the device such that all registers are re-initialized to defaultvalues and the hardware configuration values are re-latched into the device (similar to the power-up andreset operation).
10.2 POR_BYPASS mode (TLK110 only)This mode is mainly used if faster RESET and wake up (less than the 270 ms) time is required. ThisRESET is applied after power is ramped up (90% build up at least!). This mode is applicable if POR is atbypass. Connect PIN 20 to pull down (via 2.2-kΩ resistor). Release the RESET_N pin 1 ms (minimumrequirement) after power activation. The time from RESET_N release to wake up is 1 ms.
10.3 Software ResetA software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register(BMCR). The period of time from setting the reset bit, to the time when software reset has concluded isapproximately 1 ms.
In a software reset all the registers in the device are reset to default values and the hardwareconfiguration values are maintained. Software driver code must wait 3 ms following a software resetbefore allowing further serial MII (MDIO/MDC) communications with the device.
22 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
RESET
POWER SUPPLY
POR
MAGNETICS
GND
MII
RMII
IN RMII MODE CONNECT JUMPER BETWEEN 2-3
TLK110 DUT
RESISTOR CLOSE TO DUT
TLK110 CONFIGURATION
MII_CONECTOR
1_5V_PS
COL
LED_LINK
CRS
TXD0
RXD3
RXD2
MDC
CRS
COL
TX_CLK
25_50M_REF RXD1
MTLW-103-23-S-S-260PN0035R
TPS3825-33DBVTMX0052
I371NF
I35
RESET_N
IGNOREIGNOREIGNORE
1NF
5V_PS
3_3V_PS
1_5V_PS
IGNORE
RESET_N
ROOM=MAG_DUTTDP_A
TDM_A
RDP_B
RDM_B
TXD1
TXD3
ROOM=POWER SUPPLY
TX_EN
RXD0
ROOM=MII_CONNECTOR
RX_ER
RX_DV
TXD2
MDIO
RX_CLK
ROOM=TLK110_DUT
25_50M_REF
MDC
MDIO
RDM_B
RDP_B
RXD0
RXD1
RXD2
RXD3
RX_CLK
RX_DV
RX_ER
TDM_A
TDP_A
TXD0
TXD1
TXD2
TXD3
TX_CLK
TX_EN
0
3_3V_PS
3_3V_PS
ROOM=CONFIGURATIONS
3_3V_PS
COL
CRS
LED_LINK
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_ER
M201
J2
M202 M203 M200
1
TP30MIL19
1
TP30MIL20
1
TP30MIL21
1
TP30MIL22
1 1 1 12
1
C29
21
C30
2
15
4
3
U3
21R32
12
3
J1
MII_REV2
TXD3
TXD2
TXD1
TXD0
RXD3
RXD2
RXD1
RXD0
TX_EN
TX_CLK
RX_ER
RX_DV
RX_CLK
MDIO
MDC
CRS
COL5V_PS
3xjumper
IN3
IN2
IN1
TLK110_CONFIGURATION_DUT_REV2
RX_ER
RX_DV
RXD3
RXD2
RXD1
RXD0
LED_LINK
CRS
COL
3_3V_PS
TLK110_DUT_32P_REV1
TX_EN
TX_CLK
TXD3
TXD2
TXD1
TXD0
TDP_A
TDM_A
RX_ER
RX_DV
RX_CLK
RXD3
RXD2
RXD1
RXD0
RDP_B
RDM_B
MDIO
MDC
LED_LINK
CRS
COL
25M_50M_REF
RESET_N
3_3V_PS
1_5V_PS
TLK110_CUSTOMER_PS3_3V_PS
1_5V_PS5V_PS
tps3825-33dbvt
RESET_OUT_PIN3
MR_N_IN_PIN4
VDD_PWR_PIN5 RESET_N_OUT_PIN1
GND_PWR_PIN2
VIA
VIA
VIA
JUMPER
MAGNETICS_REV2
CT_INPUT
RDM_B
RDP_B
TDM_A
TDP_A
VIA
TP30MIL1
TP30MIL1
TP30MIL1
TP30MIL1
www.ti.com Schematics Example
11 Schematics ExampleThis section contains the TLK105 and TLK106 schematics.
Figure 25. Schematic 1 of 6
23SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
MAGNETICS
MAGNETICS
CHA
RJ45_RA
CHB
100NF1UF
I88
49.9
49.9
CT_INPUT
CT_INPUT
HX1188NLI41
75 75
I87 I89
I51
10N
F
75
100NFI83
10N
F
I47
THHMTSW-101-07-TM-S-240MECHANICALMC0002R
49.9
6116526-1
0
75
PN0021R
0
I84100NF
I851UF
I821UF
49.9
TDM_A
RDP_B
RDM_B
I86
TDP_A
1UF100NF
I924700PF
I804700PF
21R10
2 1R14
21R11
21R12
1
TP30MIL1
T1
1
2
3
4
5
6
7
8
9
10
U2
21
R8
12
C8
21
R7
21
R6
12
C7
21
R5
2 1R13
21R9
12
C19
1 2
C24
1 2
C23
1 2
C25
1 2
C26
21 C14
21 C9
21 C15
21 C10
12
C16
IN
GND_PIN10
GND_PIN9
I/0_PIN8
I/0_PIN7
I/0_PIN6
I/0_PIN5
I/0_PIN4
I/0_PIN3
I/0_PIN2
I/0_PIN1
H1102
TX_P16
TX_P15
TX_P14
NC_P13
RX_P8
TX_P3
RX_P10
RX_P11
NC_P12 NC_P5
NC_P4
RX_P7
RX_P6
TX_P2
TX_P1
RX_P9
IN
TP30MIL1
IN
IN
IN
IN
Schematics Example www.ti.com
Figure 26. Schematic 2 of 6
24 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
MII_CONNECTORMALE
IGNORE IGNORE IGNORE IGNORE IGNORE IGNORE IGNORE
MC0002RIGNOREIGNORE
MC0002RIGNORE
MC0002RIGNORE
MC0002RIGNORE
MC0002RIGNORE
MC0002RIGNORE
MC0002RIGNORE
MC0002R
33
TXD2
TXD0
RX_CLKRX_DV
47UF
3333
33
33
33
3333
33
33
3333
33TXD3
RX_ER
RXD1RXD0
RXD2
MDC
TXD1
COLCRS
RXD3
33
TX_ENTX_CLK
47UF
33
MDIO5V_PS
5V_PS5V_PS
5V_PS
PN0212AMP174218-2
IGNOREMC0002R
33
33
IGNORE
21 R29
1
TP30MIL17
1
TP30MIL15
1
TP30MIL13
1
TP30MIL11
1
TP30MIL9
1
TP30MIL7
1
TP30MIL5
21 R2421 R22
21 R30
21 R26
21R3121R27
21 R2821R25
21 R23
41
42
P1
21 R20
21R1921R17
21R1621R15
21
C27
21
C281
TP30MIL18
21 R21
21R18
1
TP30MIL2
1
TP30MIL3
1
TP30MIL4
1
TP30MIL6
1
TP30MIL8
1
TP30MIL10
1
TP30MIL12
1
TP30MIL14
1
TP30MIL16TP30MIL
1TP30MIL
1TP30MIL
1TP30MIL
1TP30MIL
1TP30MIL
1TP30MIL
1TP30MIL
1
ININININ
ININININ
TP30MIL1
TP30MIL1
OU
T
+
+
IN
ININ
IN
INININ
ININ
GN
D_P
IN4
2G
ND
_P
IN4
1
PIN40
PIN39
PIN38
PIN37
PIN36
PIN35
PIN34
PIN33
PIN32
PIN31
PIN30
PIN29
PIN28
PIN27
PIN26
PIN25
PIN24
PIN23
PIN22
PIN21
PIN20
PIN19
PIN18
PIN17
PIN16
PIN15
PIN14
PIN13
PIN12
PIN11
PIN10
PIN9
PIN8
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
TP30MIL1
TP30MIL1
TP30MIL1
TP30MIL1
TP30MIL1
TP30MIL1
TP30MIL1
www.ti.com Schematics Example
Figure 27. Schematic 3 of 6
25SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
3.3V_PS
OFF = MII 5VMII 3V3ON =
PULLUP RESISTOR
1.5V_PS
4.9
9K
3_3V_PS
1_5V_PS1_5V_PS
3_3V_PS
3_3V_PS
I40
1UF
100U
F
0
IGN
OR
E
0 0
VR0096R TPS74801DRC
I33
27P
F
5.6
2K
10K
I26
1NF I2
510
0PF
I2410
0NF
I20
SOT23NPN_SM-MMBT2222A
TR0001R
1K
I19 1
7_
21
SY
GC
_S
53
020
0
IGN
OR
E
220N
F
100U
F
00
VR0095RTPS75433Q
3.3K
100U
F
10N
F
1NF
100P
F
RC
08
05
D1
7_
21
SY
GC
_S
53
0G
RE
EN
402
I2
I5I6I7
I17
3_3V_PS
0
IGNORE
0
5V_PS
I2810
UF
21
R4
21
R3
21
U1
21
R1
21
R2
21
C2
12
C1
21
R63
21
LD
8
21
LD
1
2
3
1Q1
21R62
12
C38
12
C37
12
C36
12
C34
21
R60
2 1R58
21
R61
12
C33
7
3
9
8
1
2
5
4
10
116
U4
21
R57
21
R33
21
C32
21
R55
12
C31
21R56
21 R59
12
C6
12
C5
12
C4
21
C3 +
OU
T
+
tps74801drc
GN
D_
PW
R_P
IN6
TH
ER
MA
L_
PA
D_P
WR
_P
IN11
OUT_OUT_PIN10
BIAS_IN_PIN4
EN_IN_PIN5
IN_IN_PIN2
IN_IN_PIN1
FB_OUT_PIN8
OUT_OUT_PIN9
PG_OUT_PIN3
SS_OUT_PIN7
OUT
KA
KA
+
tps75433q
PW
R_
PA
D_G
ND
GN
D/H
EA
TS
INK
_P
WR
_P
IN1
GN
D/H
EA
TS
INK
_P
WR
_P
IN11
GN
D_
PW
R_P
IN17
GN
D/H
EA
TS
INK
_P
WR
_P
IN10
GN
D/H
EA
TS
INK
_P
WR
_P
IN20
RESET/PG_OUT_PIN6
EN_IN_PIN5
IN_IN_PIN4
NC
_P
IN2
NC
_P
IN12
NC
_P
IN14
NC
_P
IN13
NC
_P
IN18
NC
_P
IN16
NC
_P
IN15
NC
_P
IN19
OUTPUT_OUT_PIN9
OUTPUT_OUT_PIN8
IN_IN_PIN3
FB/SENSE_IN_PIN7
IN
Schematics Example www.ti.com
Figure 28. Schematic 4 of 6
26 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
0805 FOOTPRINT
0805 FOOTPRINT
0805 FOOTPRINT
0805 FOOTPRINT
0805 FOOTPRINT
0805 FOOTPRINT MUST BE CONNECTED WHEN WORKING IN RMII MODE
CLOSE TO PIN 15
CLOSE TO PIN 16
CLOSE TO PIN 24
25/50MHZ OSCILATOR
CLOSE TO PIN 13
TLK110 DUT
TLK110
3_3V_PS
MDIO
IGNORE
RBIAS
PFBIN2
I47
IGNORE
1_5V_PS
1_5V_PS
1_5V_PS
PFBOUT
PFBOUT
0
0
I171100NF 0
I182
10N
F I181
1NF I1
8010
0PF
0
IGNORE
2.2K
RE
SE
T_N
3_3V_PS
3_3V_PS IOVDD33
AVDD33
10U
F
10N
F
1NF
0
100P
F
0
10U
F
10N
F
1NF
100P
F I14
I16
I17
I18
I126
I149
I150
I151
100NF
100NFI185
2.2K
10U
FI1
83
2.2K
2.2KIGNORE
3_3V_PS
IGNORE
2.2
K
RXD3
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
100NFI51
I52
10UF
4.87K
PFBIN1
VF3AH1-25MHZOS0040R
IGNORE
4.7K
0IGNORE
0
100P
F I138
1NF I1
39
10N
F I140
0
I11033PF
1M
I12833PF
25M_50M_REF
3_3V_PS
0
HH
25
00
-18
-E-2
5P
PM
OX
00
40
R
I109
IGNORE0
C49
C46
C44
C42
R64
C54
C53C52
R82J14
R96
R71
R73
R72
XT
AL1
C51
R78
C50
R70
C48
R68
U5
R66
C41
C40
C39
R65
C47
C45
C43
R106
C55
R67
R80
R77
R79
C60
C59
C58
C57
C56
R74
R75
R76
PFBIN2
PFBOUT
RDM_B
RDP_B
TDM_A
TDP_A
PFBIN1
AVDD33
RBIASRX_CLK
RXD1
RX_DV
CRS
RX_ER
COL
RXD0
RXD2
MD
C
MD
IO
LE
D_LIN
K
RE
SE
T_N
IOVDD33
TLK11032PQFN
21
21
21
21
21
U6
12
212
12
112
34
21
12
12
12
12
21
12
121
2
12
21
12
21
21
21
21
21
12
12
12
121
2
21
21
21
21
21
21
21
21
2121
21
21
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OU
T
OU
T
IN
OU
T
JUMPER
OUT
IN
IN
VDD_4 OUTPUT_3
GND_2 E_D_1
OUT
OUT
OUT
OUT
OUT
OUT
tlk110_32p_qfn_rev1
VD
D_
PF
BIN
2_
PO
WE
R_
P2
4
TX
CL
K_
OU
TP
UT
_P
2
RX
D_
3/P
HY
AD
4_
OU
TP
UT
_P
1
TX
EN
_IN
PU
T_
P3
TX
D_
0_
INP
UT
_P
4
TX
D_
1_
INP
UT
_P
5
TX
D_
2_
INP
UT
_P
6
TX
D_
3_
INP
UT
_P
7
INT
N_
INP
UT
_P
8
POWER_PAD_POWER_P33
LE
D_
LIN
K/A
N0
_O
UT
PU
T_
P1
7
RE
SE
TN
_IN
PU
T_
P1
8
MD
IO_
BID
IR_
P1
9
MD
C_
INP
UT
_P
20
VD
DS
_3
P3
V_
PO
WE
R_
P2
1
XO
_O
UT
PU
T_
P2
2
XI_
INP
UT
_P
23
RXD_2/PHYAD3_OUTPUT_P32
RXD_0/PHYAD1_OUTPUT_P30
COL/PHYAD0_OUTPUT_P29
RX_ER/MDIX_EN_OUTPUT_P28
CRS/CRS_DV/LED_CFC_OUTPUT_P27
MIRX_DV/MII_MODE_OUTPUT_P26
RXD_1/PHYAD2_OUTPUT_P31
RX_CLK_OUTPUT_P25 RBIAS_POWER_P16
AVDD33/AFE_TEST_POWER_P14
VDD_PFBIN1_POWER_P13
TD_P_BIDIR_P12
TD_N_BIDIR_P11
RD_P_BIDIR_P10
RD_N_BIDIR_P9
VDD_PFBOUT_POWER_P15
OUT
XT
AL
P1
P2
OUT
OUT
OUT
OUT
www.ti.com Schematics Example
Figure 29. Schematic 5 of 6
27SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
CFG_ANEG_SPD_0
CFG_PHY_ID [2]
CFG_PHY_ID [3]
CONFIGURATION PINS
CFG_PHY_ID [0]
CFG_CROSSOVR
MII/RMII
CFG_PHY_ID [1]
CFG_PHY_ID [4]
LED_MODE_CONFIGURATION
2.2K
3_3V_PS
2.2KIGNORE
2.2K
RXD3
2.2K
RXD2
2.2K
COL
RX_DV
RX_ER
RXD0
RXD1
2.2K
2.2K
2.2K
IGNORE
CRS
IGNORE
LED_LINK
470
2.2K
PN0035RMTLW-103-23-S-S-260
I22
2.2K
17_21SYGC_S530
I48
470
3_3V_PS
17_21SYGC_S530
R36
R35
R39
R38
R37
R41
LD4
R49
R48
R46
R47LD5
J4
J6
J5
R40
J7
J8
J10
R51
21
21
21
21
21
21
21 21
21
21
21
2 1
12
3
21
21
21
21
21
21
21
IN
IN
IN
JU
MP
ER
JU
MP
ER
JU
MP
ER
JU
MP
ER
JU
MP
ER
3xjumper
IN3
IN2
IN1
KA
IN
K A
IN
IN
IN
IN
IN
IN
Schematics Example www.ti.com
Figure 30. Schematic 6 of 6
28 TLK1XX Design and Layout Guide SLVA531A–February 2013–Revised September 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
www.ti.com Other Applicable Documents
12 Other Applicable DocumentsUse the following documents in conjunction with this document, to assist in designing with the TLK1XXproducts:• TLK110 datasheet• TLK105 and TLK106 Data Sheet (SLLSEB8)• Transformerless application note (SLLA327)• PBO application note (SLLA328)
29SLVA531A–February 2013–Revised September 2013 TLK1XX Design and Layout GuideSubmit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
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