TLV840-Q1 Nano-Power Voltage Supervisor with Adjustable

TLV840-Q1 Nano-Power Voltage Supervisor with Adjustable Reset Time Delay

1 FeaturesQualified for automotive applications:

• AEC-Q100 qualified with the following results:– Device temperature grade 1: –40°C to +125°C

ambient operating temperature– Device HBM ESD classification level 2– Device CDM ESD classification level C7B

Designed for high performance:

• Nano supply current : 120 nA (Typ)• High accuracy: ±0.5% (Typ)• Built-in hysteresis (VHYS): 5% (Typ)• Fixed threshold voltage (VIT-): 0.8 V to 5.4 V

Designed for a wide range of applications:

• Operating voltage range : 0.7 V to 6 V• Fixed (VIT-) voltage: 0.8 V to 5.4 V in 0.1 V steps• Programmable reset time delay (tD)

– Min time delay: 40 µs (typ) without capacitor• Active-low manual reset (MR)

Multiple output topologies / Package type:

• Four output topologies (RESET / RESET):– TLV840MADL-Q1: open-drain, active-low– TLV840MAPL-Q1: push-pull, active-low– TLV840MADH-Q1: open-drain, active-high– TLV840MAPH-Q1: push-pull, active-high

• Package: SOT23-5 (DBV)

2 Applications• Surround view system, front camera• Automotive gateway• Radar ECU• Automotive head unit• ADAS controller• Emergency call• Telematics control unit

3 DescriptionThe TLV840-Q1 device is a voltage supervisor orreset IC that can operate at wide input voltage levelsfrom 0.7 V to 6 V while maintaining very low quiescentcurrent across the whole VDD and temperature range.TLV840-Q1 offers the best combination of low powerconsumption, high accuracy and low propagationdelay (tp_HL= 30 µs typical).

Reset output signal is asserted when the voltage atVDD drops below the negative voltage threshold(VIT-). Reset signal is cleared when VDD rise aboveVIT- plus hysteresis (VHYS) and the reset time delay(tD) expires. Reset time delay can be programmedby connecting a capacitor between the CT pin andground. For a minimum reset delay time the CT pincan be left floating. The TLV840-Q1, with its manualreset pin (MR), offers program flexibility by forcing thesystem into a hard reset when the pin is asserted.

Additional features: Low power-on reset voltage(VPOR), built-in glitch immunity protection for VDD,built-in hysteresis, low open-drain output leakagecurrent (Ilkg(OD)). TLV840-Q1 is a perfect voltagemonitoring solution for automotive applications andbattery-powered / low-power applications.

Device InformationPART NUMBER PACKAGE (1) BODY SIZE (NOM)

TLV840-Q1 SOT-23 (5) (DBV) 2.90 mm × 1.60 mm

(1) For package details, see the mechanical drawing addendumat the end of the data sheet.

TLV840MADL29Q1

VDD

GND

RESET

Microcontroller

VDD

5 V

RESET

LDO3.3 V

CT

IN OUT

*Rpu

*Rpu only for open-drain output

MR

Typical Application CircuitVDD (V)

I DD (

µA

)

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 60.08

0.12

0.16

0.2

0.24

0.28

0.32

0.36

0.4

IDDv

25°C-40°C125°C

Typical Supply Current

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents1 Features............................................................................12 Applications..................................................................... 13 Description.......................................................................14 Revision History.............................................................. 25 Device Comparison......................................................... 36 Pin Configuration and Functions...................................47 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 57.2 ESD Ratings .............................................................. 57.3 Recommended Operating Conditions ........................57.4 Thermal Information ...................................................57.5 Electrical Characteristics ............................................67.6 Timing Requirements .................................................77.7 Timing Diagrams ........................................................87.8 Typical Characteristics ............................................. 10

8 Detailed Description......................................................128.1 Overview................................................................... 12

8.2 Functional Block Diagram......................................... 128.3 Feature Description...................................................128.4 Device Functional Modes..........................................17

9 Application and Implementation.................................. 189.1 Application Information............................................. 189.2 Typical Application.................................................... 18

10 Power Supply Recommendations..............................2111 Layout...........................................................................22

11.1 Layout Guidelines................................................... 2211.2 Layout Example...................................................... 22

12 Device and Documentation Support..........................2312.1 Device Nomenclature..............................................2312.2 Receiving Notification of Documentation Updates..2412.3 Support Resources................................................. 2412.4 Trademarks.............................................................24

13 Mechanical, Packaging, and OrderableInformation.................................................................... 24

4 Revision History

Changes from Revision * (November 2020) to Revision A (April 2021) Page• RTM release....................................................................................................................................................... 1

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5 Device ComparisonFigure 5-1 shows the device naming nomenclature to compare the different device variants. See Section 12.1 fora more detailed explanation.

TLV 840 X X XX XX XXX

Feature Opon

M: Capacitor delay (CT)

and manual reset (MR)

Output Type

DL: Open-drain,

acve-low

PL: Push-pull,

acve-low

DH: Open-drain,

acve-high

PH: Push-pull,

acve-high

Detect Voltage Threshold

08: 0.8V

...

54: 5.4V

Delay Opon

A:

- 40 µs default

(CT pin oang)

- Programmable

(CT pin with capacitor

to GND)

Package

DBV: SOT23

Q1

Figure 5-1. Device Naming Nomenclature

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6 Pin Configuration and Functions

1

2VDD

3GND 4

5 CT

Not to scale

MR

RESET / RESET

Figure 6-1. Pin Configuration TLV840M-Q1DBV Package 5-Pin SOT-23

TLV840M-Q1 Top View

Table 6-1. Pin FunctionsPIN

I/O DESCRIPTIONPIN NO. TLV840MAxL-Q1 TLV840MAxH-Q1

1 RESET N/A O

Active-Low Output Reset Signal: This pin is driven logic lowwhen VDD voltage falls below the negative voltage threshold (VIT-).RESET remains low (asserted) for the delay time period (tD) afterVDD voltage rises above VIT+ = VIT-+VHYS.

1 N/A RESET O

Active-High Output Reset Signal: This pin is driven logic highwhen VDD voltage falls below the negative voltage threshold (VIT-).RESET remains high (asserted) for the delay time period (tD) afterVDD voltage rises above VIT+ = VIT-+VHYS.

2 VDD VDD I Input Supply Voltage: TLV840-Q1 monitors VDD voltage

3 GND GND _ Ground

4 MR MR I

Manual Reset: Pull this pin to a logic low to assert a reset signal inthe RESET output pin. After MR pin is left floating or pulls to logichigh, the RESET output deasserts to the nominal state after thereset delay time (tD) expires.

5 CT CT -

Capacitor Time Delay Pin: The CT pin offers a user-programmable delay time. Connect an external capacitor on thispin to adjust time delay. When not in use leave pin floating for thesmallest fixed time delay.





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7 Specifications7.1 Absolute Maximum Ratingsover operating free-air temperature range, unless otherwise noted(1)

MIN MAX UNITVoltage VDD –0.3 6.5 V

VoltageCT, MR (2), RESET (TLV840MAPL), RESET(TLV840MAPH) –0.3 VDD+0.3 (3)

VRESET (TLV840MADL) –0.3 6.5

Current RESET, RESET pin –20 20 mA

Temperature (4) Operating ambient temperature, TA –40 125

Temperature (4) Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stressratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicatedunder Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.

(2) If the logic signal driving MR is less than VDD, then IDD current increases based on voltage differential.(3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller(4) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

7.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman body model (HBM), per AEC Q100-002(1) ±2000

VCharged device model (CDM), per AEC Q100-011 ±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VoltageVDD (TLV840MAxL) 0.7 6

VCT, RESET (TLV840MAxL), RESET (TLV840MAPH) ,MR 0 6

Current RESET and RESET pin current –5 5 mA

TA Operating ambient temperature –40 125

7.4 Thermal Information

THERMAL METRIC(1)

TLV840-Q1UNITDBV (SOT23-5)

5 PINSRθJA Junction-to-ambient thermal resistance 193.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 117.9 °C/W

RθJB Junction-to-board thermal resistance 98.5 °C/W

ψJT Junction-to-top characterization parameter 43.4 °C/W

ψJB Junction-to-board characterization parameter 97.8 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

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7.5 Electrical CharacteristicsAt 0.7 V ≤ VDD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pFand over operating free-air temperature range –40 to 125, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typicalvalues are at TA = 25

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCOMMON PARAMETERSVDD Input supply voltage TLV840MAxL 0.7 6 V

VIT–Negative-going input threshold accuracy(1)

VIT- = 0.8 V to 1.7 V –2.5 ±0.5 2.5%

VIT- = 1.8 V to 5.4 V –2 ±0.5 2

VHYS Hysteresis on VIT– pin 2.5 5 7 %

IDD Supply current into VDD pin (2)VDD = 2 V; VIT– = 0.8 V to 1.8 V 0.12 1.0

µAVDD = 6 V; VIT– = 0.8 V to 5.4 V 0.15 1.2

VMR_L Manual reset logic low input (2) 0.3VDD V

VMR_H Manual reset logic high input (2) 0.7VDD V

RMR Manual reset internal pull-up resistance 100 kΩ

RCT CT pin internal resistance 500 kΩ

TLV840MADL (Open-drain active-low)

VPOR Power on Reset Voltage (3) VOL(max) = 300 mVIOUT(Sink) = 15 µA 700 mV

VOLLow level output voltage

VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300

mVVDD =1.5 V, 1.6 V ≤ VIT– ≤ 3.3 VIOUT(Sink) = 500 µA 300

VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 VIOUT(Sink) = 2 mA 300

Ilkg(OD) Open-Drain output leakage currentVDD = VPULLUP = 6VTA = –40 to 85 10 100 nA

VDD = VPULLUP = 6V 10 350 nA

TLV840MAPL (Push-pull active-low)

VPOR Power on Reset Voltage (3) VOL(max) = 300 mVIOUT(Sink) = 15 µA 700 mV


VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300

mVVDD = 1.5 V, 1.6 V ≤ VIT– ≤ 3.3 VIOUT(Sink) = 500 µA 300

VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 VIOUT(Sink) = 2 mA 300

VOHHigh level output voltage

VDD = 1.8 V, 0.8 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD

VVDD = 3.3 V, 1.5 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD

VDD = 6 V, 3.1 V ≤ VIT– ≤ 5.5 VIOUT(Source) = 2 mA 0.8VDD





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7.5 Electrical Characteristics (continued)At 0.7 V ≤ VDD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pFand over operating free-air temperature range –40 to 125, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typicalvalues are at TA = 25

PARAMETER TEST CONDITIONS MIN TYP MAX UNITTLV840MAPH (Push-pull active-high)

VPOR Power on Reset Voltage (3) VOH(min) = 0.8VDD VIOUT (Source) = 15 uA 900 mV


VDD=3.3 V0.8 V ≤ VIT- ≤ 3.0 VIOUT(Sink) = 500 µA

300 mV

VDD=6 V3.1 V ≤ VIT- ≤ 5.5 VIOUT(Sink) = 2 mA

300 mV

VOHHigh level output voltage

VDD = 0.9 V 1 V ≤ VIT- ≤ 1.5 VIOUT(Sink) = 15 µA

0.8VDD V

VDD=1.5 V1.6 V ≤ VIT- ≤ 3.3 VIOUT(Sink) = 500 µA

0.8VDD V

VDD=3.3 V3.4 V ≤ VIT- ≤ 5.5 VIOUT(Sink) = 2 mA

0.8VDD V

(1) VIT– threshold voltage range from 0.8 V to 5.4 V (for DL, PL versions) in 100 mV steps(2) If the logic signal driving MR is less than VDD, then IDD current increases based on voltage differential(3) VPOR is the minimum VDD voltage level for a controlled output state

7.6 Timing RequirementsAt 0.7 V ≤ VDD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pFand over operating free-air temperature range –40 to 125, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typicalvalues are at TA = 25

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tP_HLPropagation detect delay for VDD fallingbelow VIT–

VDD : (VIT+ + 10%) to (VIT– – 10%)(1) 30 50 µs

tD Reset time delay

CT pin = Open or NC(VIT- - 10%) to (VIT+ + 10%) 40 80 µs

CT pin = 10 nF 6.2 ms

CT pin = 1 µF 619 ms

tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive(2) 10 µs

tSTRT Startup Delay (3) CT pin = Open or NC 300 µs

tMR_PW MR pin pulse duration to assert reset (4) 500 ns

tMR_RESPropagation delay from MR low to resetassertion

VDD = 3.3 V,MR = VMR_H to VMR_L

1 µs

tMR_tD Delay from MR release to reset deassert VDD = 3.3 V,MR = VMR_L to VMR_H

tD ms

(1) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS

(2) Overdrive % = [(VDD/ VIT–) – 1] × 100%(3) When VDD starts from less than the specified minimum VDD and then exceeds VIT-, reset is release after the startup delay (tSTRT), a

capacitor at CT pin will add tD delay to tSTRT time(4) Refer section on Manual Reset Input for min pulse width needed on MR pin

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7.7 Timing Diagrams

tDtP_HL

VDD

VPOR

VOH

VOL

VIT+

VDD(MIN)

VIT-

RESET

tSTRT + tD tP_HL tSTRT + tD

(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will beadded to the startup time, VDD slew rate = 100 mV / μs.

(2) Open-Drain timing diagram where RESET is pulled up to VDD via an external pull-up resistor

(3) RESET output is undefined when VDD is < VPOR

Figure 7-1. Timing Diagram TLV840MADL-Q1 (Open-Drain Active-Low)

tDtP_HL

VDD

VPOR

VOH

VOL

VIT+

VDD(MIN)

VIT-

RESET

tP_HLtSTRT + tD tSTRT + tD


(5) RESET output is undefined when VDD is < VPOR and limited to VOL for VDD slew rate = 100 mV / μS

Figure 7-2. Timing Diagram TLV840MAPL-Q1 (Push-Pull Active-Low)





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tDtP_HL

VDD

VPOR

VOH

VOL

VIT+

VDD(MIN)

VIT-

RESET

tSTRT + tD tP_HL tSTRT + tD


Figure 7-3. Timing Diagram TLV840MAPH-Q1 (Push-Pull Active-High)

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7.8 Typical CharacteristicsTypical characteristics show the typical performance of the TLV840-Q1 device. Test conditions are TA = 25°C, VDD = 3.3 V,RPull-Up = 100 kΩ, CLOAD = 50 pF, unless otherwise noted.

VDD (V)

I DD (

µA

)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.00.06

0.12

0.18

0.24

0.30

0.36

0.42-40°C25°C125°C

Figure 7-4. Supply Current vs Supply VoltageTemperature (oC)

VIT

- A

ccu

racy (

%)

-40 -20 0 20 40 60 80 100 120 140-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5VIT- = 2 VVIT- = 3.3 V

Figure 7-5. VIT- Accuracy vs Temperature

Temperature (oC)

VH

YS (

%)

-40 -20 0 20 40 60 80 100 120 1403.2

3.6

4.0

4.4

4.8

5.2

5.6VIT- = 2 VVIT- = 3.3 V

Figure 7-6. VHYS vs TemperatureTemperature (oC)

TP

_H

L (

s)

-40 -20 0 20 40 60 80 100 120 14014.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

μTLV840MADL13

Figure 7-7. Propagation Delay vs Temperature

Temperature (oC)

t D d

ela

y (

ms)

-40 -20 0 20 40 60 80 100 120 14010

20

30

40

50

60

70TLV840MADL13

Figure 7-8. Reset Time Delay vs Temperature

CT Capacitance ( F)

t D d

ela

y (

ms)

0 2 4 6 8 100

1200

2400

3600

4800

6000

μ

Figure 7-9. Reset Time Delay vs CT Capacitance





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7.8 Typical Characteristics (continued)Typical characteristics show the typical performance of the TLV840-Q1 device. Test conditions are TA = 25°C, VDD = 3.3 V,RPull-Up = 100 kΩ, CLOAD = 50 pF, unless otherwise noted.

IOL (mA)

VO

L (

V)

0 1 2 3 4 50

0.04

0.08

0.12

0.16

0.2-40oC25oC125oC

Figure 7-10. VOL vs IOL

Temperature (oC)

VO

L (

V)

-40 -20 0 20 40 60 80 100 120 1400.04

0.05

0.06

0.07

0.08

0.09

0.10VIT- = 2 V

Figure 7-11. VOL vs Temperature

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8 Detailed Description8.1 OverviewThe TLV840-Q1 is a family of nano-quiescent current voltage detectors with fixed threshold voltage. TLV840-Q1features include programable reset time delay using external capacitor, active-low manual reset, 0.5% typicalmonitor threshold accuracy with hysteresis and glitch immunity.

Fixed negative threshold voltages (VIT-) can be factory set from 0.8 V to 5.4 V. TLV840-Q1 is available inSOT-23 5-pin industry standard package.

8.2 Functional Block Diagram

+

–Reference

GND

VDD

RESET

GND

VDD

RESET

LOGIC

TIMER

CT

Push-pull (TLV840MAPx)

version only

RCT

RMR

VDD

RESET

MR

8.3 Feature Description8.3.1 Input Voltage (VDD)

VDD pin is monitored by the internal comparator to indicate when VDD falls below the fixed threshold voltage.VDD also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and othercontrol logic blocks. Good design practice involve placing a 0.1 μF to 1 μF bypass capacitor at VDD input fornoisy applications to ensure enough charge is available for the device to power up correctly.





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8.3.1.1 VDD Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDDpin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis(VHYS) the output reset is deasserted after tD delay.

VDD

Hystersis Width

VIT+VIT-

RESET RESET

VDD

Hystersis Width

VIT+VIT-

Figure 8-1. Hysteresis Diagram

8.3.1.2 VDD Transient Immunity

The TLV840-Q1 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients dependson both pulse duration (tGI_VIT-) found in Section 7.6 and overdrive. Overdrive is defined by how much VDDdeviates from the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question,as shown in Equation 1.

Overdrive = | [(VDD / VIT-) – 1] × 100% | (1)

Overdrive

Pulse

Duration

VDD

VIT-

VIT+

Figure 8-2. Overdrive vs Pulse Duration

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8.3.2 User-Programmable Reset Time Delay

The reset time delay can be set to a minimum value of 80 µs by leaving the CT pin floating, or a maximum valueof approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmedby connecting a capacitor no larger than 10 µF between CT pin and GND.

The relationship between external capacitor (CCT) in µF at CT pin and the time delay (tD) in seconds is given byEquation 2.

tD (typ) = -ln (0.29) x RCT x CCT + tD (no cap) (2)

Equation 3 solves for external capacitor (μF) by plugging RCT and tD (CT pin = Open) given in Section 7.5section:

CCT = (tD - 80 µs) ÷ 618937 (3)

The reset delay varies according to three variables: the external capacitor (CCT), CT pin internal resistance (RCT)provided in Section 7.5, and a constant. The minimum and maximum variance due to the constant is show inEquation 4 and Equation 5:

tD (min) = -ln (0.37) x RCT (min) x CCT_EXT (min) + tD (no cap) (4)

tD (max) = -ln (0.25) x RCT (max) x CCT_EXT (max) + tD (no cap) (5)

The recommended maximum delay capacitor for the TLV840-Q1 is limited to 10 µF as this ensures there isenough time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs,the previously charged up capacitor discharges, and if the monitored voltage returns from the fault conditionbefore the delay capacitor discharges completely, the reset delay will be shorter than expected because thedelay capacitor will begin charging from a voltage above zero. Larger delay capacitors can be used so long asthe capacitor has enough time to fully discharge during the duration of the voltage fault. The amount of timerequired to discharge the delay capacitor relative to the reset delay increases as VDD overdrive increases asshown in Figure 8-3. From the graph below, to ensure the CT capacitor is fully discharged, the time period orduration of the voltage fault needs to be greater than 10% of the programmed reset time delay.

VDD Fault Underoltage (V)

Fault T

ime to R

eset

Dela

y T

ime R

atio (

%)

0.6 0.8 1 1.2 1.4 1.6 1.8 25

10

15

20

25

30

35

40

45

50

55

CTR_

25°C

Figure 8-3. CCT Discharge Time During Fault Condition (VIT- = 2 V, CCT = 1 µF)





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8.3.3 Manual Reset (MR) Input

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MRwith pulse duration longer than tMR_PW will cause the reset output to assert. After MR returns to a logic high(VMR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.

The minimum duration for which MR is held under VMR_L must be at least 1% of tMR_tD. Otherwise, the effectivereset delay will be shorter roughly by the difference between 1% of tMR_tD and the actual MR pulse width. Forlarge capacitor based delays this difference could be noticeable unless care is taken to lengthen the MR pulsewidth.

MR is internally connected to VDD through a pull-up resistor RMR shown in Section 8.2. If the logic signalcontrolling MR is less than VDD, then additional current flows from VDD into MR internally. For minimum currentconsumption, drive MR to either VDD or GND. VMR should not be higher than VDD voltage.

VIT+

tP_HL

VHYS

VIT-

tD

VIT+

VHYS

VIT-

tMR_tD

VMR_L

Time

tMR_RES

tMR_PW(1)

MR

VDD

RESET

VMR_H

(2)

(1) MR pulse width too small to assert RESET(2) MR voltage not low enough to assert RESET

Figure 8-4. Timing Diagram MR and RESET

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8.3.4 Output Logic8.3.4.1 RESET Output, Active-Low

RESET (Active-Low) applies to TLV840DL-Q1 (Open-Drain) and TLV840PL-Q1 (Push-Pull) hence the "L" in thedevice name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and theMR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, thenRESET is asserted.

When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for thespecified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic highvoltage (VOH).

The TLV840DL-Q1 (Open-Drain) version, denoted with "D" in the device name, requires an external pull-upresistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source andRESET can be pulled up to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltagelevels, give some consideration when choosing the pull-up resistor values. The external pull-up resistor valuedetermines the actual VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).

The Push-Pull variants (TLV840PL-Q1 and TLV840PH-Q1), denoted with "P" in the device name, does notrequire an external pull-up resistor.

8.3.4.2 RESET Output, Active-High

RESET (Active-High), denoted with no bar above the pin label, applies to TLV840DH-Q1 (Open-Drain)and TLV840PH-Q1 push-pull active-high version, hence the "H" in the device name. RESET remains low(deasserted) as long as VDD is above the negative threshold (VIT-) and the MR pin is floating or above VMR_H. IfVDD falls below the negative threshold (VIT-) or if MR is driven low, then RESET is asserted driving the RESETpin to high voltage (VOH).

When MR is again logic high or floating and VDD rise above VIT+ the delay circuit will hold RESET high for thespecified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic lowvoltage (VOL).

The TLV840DH-Q1 (Open-Drain) version, denoted with "D" in the device name, requires an external pull-upresistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source andRESET can be pulled up to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltagelevels, give some consideration when choosing the pull-up resistor values. The external pull-up resistor valuedetermines the actual VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).

The Push-Pull variants (TLV840PL-Q1 and TLV840PH-Q1), denoted with "P" in the device name, does notrequire an external pull-up resistor.





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8.4 Device Functional ModesTable 8-1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic lowis represented by "L".

Table 8-1. Truth TableVDD MR RESET RESET

VDD < VPOR Ignored Undefined Undefined

VPOR < VDD < VIT- Ignored H L

VDD ≥ VIT- L H L

VDD ≥ VIT- H L H

VDD ≥ VIT- Floating L H

8.4.1 Normal Operation (VDD > VPOR)

When VDD is greater than VPOR, the reset signal is determined by the voltage on the VDD pin with respect to thetrip point (VIT-)

• MR high: the reset signal corresponds to VDD with respect to the threshold voltage.• MR low: in this mode, the reset is asserted regardless of the threshold voltage.

8.4.2 Below Power-On-Reset (VDD < VPOR)

When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull theasserted output low or high and reset voltage level is undefined.

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9 Application and ImplementationNote

Information in the following applications sections is not part of the TI component specification, andTI does not warrant its accuracy or completeness. TI’s customers are responsible for determiningsuitability of components for their purposes. Customers should validate and test their designimplementation to confirm system functionality.

9.1 Application InformationThe following sections describe in detail how to properly use this device, depending on the requirements of thefinal application.

9.2 Typical Application9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing

A typical application for the TLV840-Q1 is voltage rail monitoring and power-up sequencing as shown inFigure 9-1. The TLV840-Q1 can be used to monitor any rail above 0.9 V. In this design application, twoTLV840-Q1 devices monitor two separate voltage rails and sequences the rails upon power-up. TheTLV840MAPL29-Q1 is used to monitor the 3.3-V main power rail and the TLV840MADL10-Q1 is used to monitorthe 1.2-V rail provided by the LDO for other system peripherals. The RESET output of the TLV840MAPL29-Q1 isconnected to the enable (EN) input of the LDO. A reset event is initiated on either voltage supervisor when theVDD voltage is less than VIT-. For a system-wide reset event, both MR pins are tied to the SYS_RST. For thepurpose of this application, the design detail on MR are not covered. For more information on the function of MR,please see Section 8.3.3

TLV840MADL10-Q1

VDD

GND

RESET

Microcontroller

3.3 V

RESET

1.2 V

CT

IN OUT

49.9 k

MR

VCOREVI/O

1 F

NCTLV840MAPL29-Q1

VDD

GND

RESETCT

MR

LDO

EN

1 F

0.047 F

SYS_RST

Figure 9-1. TLV840-Q1 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram





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9.2.1.1 Design Requirements

This design requires voltage supervision on two separate rails: 3.3-V and 1.2-V rails. The voltage rail needs tosequence upon power up with the 3.3-V rail coming up first followed by the 1.2-V rail at least 25 ms after.

PARAMETER DESIGN REQUIREMENT DESIGN RESULT

Two Rail Voltage Supervision Monitor 3.3-V and 1.2-V railsTwo TLV840-Q1 devices provide voltagemonitoring with 1% accuracy with device optionsavailable in 0.1 V variations

Voltage Rail Sequencing Power up the 3.3-V rail first followed by 1.2-V rail25 ms after

The CT capacitor on TLV840MAPL29-Q1 is set to0.047 µF for a reset time delay of 29 ms typical

Maximum device currentconsumption 1 µA Each TLV840-Q1 requires 120 nA typical

9.2.1.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the supply voltage of themicroprocessor. The TLV840-Q1 can monitor any voltage between 0.8 V and 5.4 V. Depending on how faraway from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correctvoltage supervisor variant to choose. In this example, the first TLV840-Q1 triggers when the 3.3-V rail falls to2.9 V. The second TLV840-Q1 triggers a reset when the 1.2-V rail falls to 0.9 V. The secondary constraintfor this application is the reset time delay that must be at least 25 ms to allow the microprocessor, and allother devices using the 3.3-V rail, enough time to startup correctly before the 1.2-V rail is enabled via theLDO. Because a minimum time is required, the user must account for capacitor tolerance. For applications withambient temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and solving for CCT inEquation 2. Solving Equation 2 for 25 ms gives a minimum capacitor value of 0.0403 µF which is rounded up toa standard value 0.047 µF to account for capacitor tolerance.

A 1 µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistoris only required for the Open-Drain device variants and is calculated to ensure that VOL does not exceed maxlimit given the Isink possible at the expected supply voltage. In this design example nominal VDD is 1.2 V butdropping to 0.9 V. In Section 7.5, max VOL provides 15 µA I sink for 0.7 V VDD, which is the closest voltage tothis design example. Using 15 µA of Isink and 300 mV max VOL, gives us 40 kΩ for the pull-up resistor. Anyvalue higher than 40 kΩ would ensure that VOL will not exceed 300 mV max specification.

9.2.1.3 Application Curves

VDD

RESET

(LDO Enable)

V (LDO)OUT

30ms delay from VDD (3.3 V) to LDO Enable set by 0.047 µF on CT of TLV840MAPL29-Q1

Negligible delay from LDO Enable to 1.2 V VOUT

Figure 9-2. Startup Sequence Highlighting the Delay Between 3.3 V and 1.2 V Rails

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9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM

These application curves are taken with the TLV840EVM and they display a change in reset delay time withdifferent capacitor values. The output reset delay time was designed with the ease of programability for thecustomer. Figure 9-3 displays an output reset delay time of 57.6 μs with no capacitor on the CT pin. Figure 9-4and Figure 9-5 have output reset delay times of 5.42 ms and 56.8 ms, respectively. Both the output delay timesand capacitors used resulted in an order of magnitude difference. Please see the TLV840EVM User Guide formore information.

VDD

RESET

Reset Delay (tD)= 57.6 µs

Figure 9-3. TLV840EVM RESET Time Delay (tD) withNo Capacitor

VDD

RESET

Reset Delay (tD)= 5.42 ms

Figure 9-4. TLV840EVM RESET Time Delay (tD) with0.01-µF Capacitor

VDD

RESET

Reset Delay (tD)= 56.8 ms

Figure 9-5. TLV840EVM RESET Time Delay (tD) with 0.1-µF Capacitor




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10 Power Supply RecommendationsThe TLV840 is designed to operate from an input supply with a voltage range between 0.7 V and 6 V. TIrecommends an input supply capacitor between the VDD pin and GND pin. This device has a 6.5 V absolutemaximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltagetransient that can exceed 6.5 V, additional precautions must be taken.

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11 Layout11.1 Layout GuidelinesMake sure that the connection to the VDD pin is low impedance. Good analog design practice recommendsplacing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connectedto the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a >0.1 µF ceramic capacitor as near as possible to the VDD pin.

• If a CCT capacitor is used, place these components as close as possible to the CT pin. If the CT pin is leftunconnected, make sure to minimize the amount of parasitic capacitance on the pin to < 5 pF.

• Place the pull-up resistors on RESET pin as close to the pin as possible.

11.2 Layout ExampleThe layout example in shows how the TLV840DL-Q1 is laid out on a printed circuit board (PCB) with a user-defined delay.

GND

CIN

GND

VDD

CCTRpull-up

RESET CT

MR

VDD

Pull-up resistor required for Open-Drain

(TLV840MADx-Q1) only

Vias used to connect pins for application - specific connections

Figure 11-1. TLV840M-Q1 Recommended Layout





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12 Device and Documentation Support12.1 Device NomenclatureTable 12-1 shows how to decode the function of the device based on its part number

Table 12-1. Device Naming ConventionDESCRIPTION NOMENCLATURE VALUE

Generic Part number TLV840 TLV840

Feature Option M 1 Manual Reset option in addition to CT pin

Delay Option A 40 µs (Default internal reset time delay)

Variant code (Output Topology) DL Open-Drain, Active-Low

PL Push-Pull, Active-Low

DH Open-Drain, Active-High

PH Push-Pull, Active-High

Detect Voltage Option ## (two characters) Example: 12 stands for 1.2 V threshold

Package DBV SOT23-5

Reel R Large Reel

Automotive Version Q1 AEC-Q100

1. Orderable part numbers with TLV840M-Q1 are only available with the delay option A. However, longerdelays can be achieved through an external capacitor on the CT pin. Leaving the CT pin floating will result intypical 40 μs delay feature option.

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12.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.3 Support Resources12.4 TrademarksAll trademarks are the property of their respective owners.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.





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PACKAGE OPTION ADDENDUM

www.ti.com 26-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TLV840MADL12DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HNF

TLV840MADL22DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HOF

TLV840MADL30DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HPF

TLV840MADL31DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HMF

TLV840MADL32DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HQF

TLV840MADL40DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HDF

TLV840MAPH29DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2INF

TLV840MAPL36DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2HVF

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

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PACKAGE OPTION ADDENDUM


Addendum-Page 2

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV840-Q1 :

• Catalog : TLV840

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TLV840MADL12DBVRQ1 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3






TLV840MAPH29DBVRQ1 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TLV840MAPL36DBVRQ1 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV840MADL12DBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0






TLV840MAPH29DBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0

TLV840MAPL36DBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

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PACKAGE OUTLINE

C

0.220.08 TYP

0.25

3.02.6

2X 0.95

1.9

1.450.90

0.150.00 TYP

5X 0.50.3

0.60.3 TYP

80 TYP

1.9

A

3.052.75

B1.751.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Refernce JEDEC MO-178.4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side.

0.2 C A B

1

34

5

2

INDEX AREAPIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

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EXAMPLE BOARD LAYOUT

0.07 MAXARROUND

0.07 MINARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/F 06/2021


NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:15X

PKG

1

3 4

5

2

SOLDER MASKOPENINGMETAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSED METAL

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP


4214839/F 06/2021

NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

1

3 4

5

2

IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’sapplicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2021, Texas Instruments Incorporated

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Documents

TLV840-Q1 Nano-Power Voltage Supervisor with Adjustable