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TMS320C5515 EvaluationModule (EVM)

2010 DSP Development Systems

ReferenceTechnical

TMS320C5515 EvaluationModule (EVM)

Technical Reference

512705-0001 Rev. A February 2010

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2010 Spectrum Digital, Inc.

WARNINGTo minimize risk of electric shock hazard, use only the following power supply for the EVM module with Medical DevelopmentApplications: SL Power AULT Model MW173KB0503F01.

Contents

1 Introduction to the TMS320C5515 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C5515 EVM, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 C5515 GPIO Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.5 C5515 EVM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.6 C5515 I2C Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82 Operation and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation and physical layout of the TMS320C5515 EVM and its connectors. 2.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 J1, RS-232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.2 J2, Embedded USB Emulation Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.3 J3, I2C Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.4 J4, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5 J5, HDR4 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.6 J6, I2C Probe Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.7 J7, Stereo Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.8 J8, External JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.9 J9, Stereo In 1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.10 J10, Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.11 J11, USB Type B Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.12 J12, Stereo In 2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.13 J13, Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.14 J14, Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.2.15 J15, MMC/SD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.16 J16, +5 Volt In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.2.17 J17, Embedded Emulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.2.18 J18, Battery Holder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.2.19 J19, Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.20 M1, Left Microphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.21 M2, Right Microphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.22 Blue Tooth Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.2.22.1 P1, Blue Tooth Board Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.2.22.2 P2, Blue Tooth Board Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4 C5515 EVM Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.1 SW1, RESET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.2 SW2, WAKEUP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.3 SW4, LDO Option DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.4 SW5, On/Off Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.5 SW6-SW15, Function Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.5 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.5.1 C5515 EVM Option Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.5.1.1 JP2, nRESET Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.5.1.2 JP3, UART_EN Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.5.1.3 JP5, WAKEUP Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.5.1.4 JP6, LDO_EN Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.5.1.5 JP9, CLK_SEL Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.5.1.6 JP12, MIC_BIAS Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.5.1.7 JP39, VIN Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.5.2 C5515 EVM Power Domain Probe Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the TMS320C5515 EVMB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the TMS320C5515 EVM

About This Manual

This document describes the board level operations of the TMS320C5515Evaluation Module (EVM). The EVM is based on the Texas InstrumentsTMS320C5515 Digital Signal Processor.

The TMS320C5515 EVM is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320C5515 DSP todetermine if the processor meets the designers application requirements. Evaluatorscan create software to execute on board or expand the system in a variety of ways.

The TMS320C5515 EVM can be used to develop TMS320C5504 applications sincethe TMS320C5504 processor is a subset of the TMS320C5515.

Notational Conventions

This document uses the following conventions.

The TMS320C5515 will sometimes be referred to as the C55XX.

The TMS320C5515 EVM will sometimes be referred to as the EVM.

Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320C55XX DSP CPU Reference GuideTexas Instruments TMS320C55XX DSP Peripherals Reference Guide

Table 1: Hardware History

Revision History

A Prototype Release

B Production Release

Table 2: Manual History

Revision History

A Production Release

1-1

Chapter 1

Introduction to the TMS320C5515 EVM

Chapter One provides a description of the TMS320C5515 EVMalong with the key features and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Development Tools 1-31.3 Power Supply 1-31.4 C5515 GPIO Terminal Functions 1-41.5 C5515 EVM Memory Map 1-71.6 C5515 I2C Addressing 1-8

Spectrum Digital, Inc

1-2 TMS320C5515 EVM Technical Reference

1.1 Key Features

The C5515 EVM is a standalone development platform that enables users toevaluate and develop applications for the TI TMS320C5515 Digital Signal Processor(DSP). The EVM also serves as a hardware reference design for the TMS320C5515DSP. Schematics, logic equations and application notes are available to easehardware development and reduce time to market.

The EVM comes with a full complement of on-board devices that suit a widevariety of application environments. Key features include:

• A Texas Instruments TMS320C5515 DSP operating up to 100 Mhz.

• 128 Mbytes of Mobile SDRAM

• 16 Megabytes of NOR Flash

• 64 Megabytes of NAND Flash

• 128 x 128 bit mapped color LCD display

Figure 1-1, TMS320C5515 EVM


1-3

• TPS65023 Power Management IC for individual C5515 power rail control

• TLV320AIC3204 stereo codec with line in, line out, headphone, mic in, on board microphones

• MMC / SD Media Card Connector

• User USB 2.0 port via C5515

• I2C EEPROM (256Kbits) and SPI EEPROM (256Kbits)

• Expansion connectors for Blue Tooth interface

• RS-232 Interface

• External JTAG emulation interface

• Embedded JTAG controller

• 10 User push button switches

• INA219 power measurement devices

• Optional battery power

1.2 Development Tools

The EVM is designed to work with TI’s Code Composer Studio (CCS) IntegratedDevelopment Environment (IDE). Code Composer Studio communicates with the EVMboard through the external emulator header, or on board emulation. An EVM specificversion of Code Composer Studio ships with the EVM.

1.3 Power Supply

The EVM operates from a +5V external power supply or battery.

WARNINGTo minimize risk of electric shock hazard, use only the following power supply for the EVM module with Medical DevelopmentApplications: SL Power AULT Model MW173KB0503F01.



1.4 C5515 GPIO Terminal Functions

The C5515 has multiple GIO signals that can be used for system level tasks. The GIOsignals are connected to various connectors on the EVM. Refer to the discussion of theconnectors later in this document for details. The next table describes how the GIOlines are used on the EVM.


1-5

Table 1: C5515 GPIO Terminal Functions

C5515 Pin # C5515 Default

Multiplexed Function

GPIO Pin Routed To

M8 XF XF LED D2, TP4

L10 MMC0_CLK GP[0] MMC0_CLK = SH16, J15-5, MMC/SD connectorGP[0] = SH18, ADS_GPIO0, J13-12

M11 MMC0_CMD GP[1] MMC0_CMD = SH16, J15-2, MMC/SD connectorGP[1] = SH18, ADS_GPIO1, J13-8

L9 MMC0_DATA0 GP[2] MMC0_DATA0 = SH16, J15-7, MMC/SD connectorGP[2] = SH18, ADS_GPIO2, J13-22

M10 MMC0_DATA1 GP[3] MMC0_DATA1 = SH16, J15-8, MMC/SD connectorGP[3] = SH18, ADS_GPIO3, J13-21

L12 MMC0_DATA2 GP[4]MMC0_DATA2 = SH16, J15-9, MMC/SD connector

GP[4] = SH5, GPIO4, P1-10GP[4] = SH18, ADS_GPIO4, J13-1

L11 MMC0_DATA3 GP[5]MMC0_DATA3 = SH16, J15-1, MMC/SD connector

GP[5] = SH5, GPIO, P1-12GP[5] = SH18, ADS_GPIO5, TP14

M13 MMC1_CLK GP[6]MMC1_CLK, SH5, P1-15, Blue Tooth Board Interface

GP[6] = SH18, I2S1_CLK, J13-5GP[6] = SH5, I2S1_CLK_CC, P2-17

GP[6] = SH16, MMC0_WP, J15-WP, TP19

L14 MMC1_CMD GP[7]MMC1_CMD = SH5, P1-17, Blue Tooth Board Interface

GP[7] =I2S1_FS, SH18, J13-9GP[7] = I2S1_FS_CC, SH5, P2-11

GP[7] = MMC0_INS, SH16, J15-Card Detect, TP22

M14 MMC1_DATA0 GP[8]MMC1_DATA0 = SH5, P1-2, Blue Tooth Board Interface

GP[8] = I2S1_DX, SH18, J13-19GP[8] = I2S1_DX_CC, SH5, P2-8

M12 MMC1_DATA1 GP[9]MMC1_DATA1 = SH18, P1-4, Blue Tooth Board Interface

GP[9] = I2S1_RX, SH18, J13-14GP[9] = I2S1_RX_CC, SH5, P2-10

K14 MMC1_DATA2 GP[10]MMC1_DATA2, SH5, P1-6, Blue Tooth Board Interface

GP[10] = AIC_RST, SH19, U12-31GP[10] = ADS_GPIO10, SH18, J13-6

L13 MMC1_DATA3 GP[11]MMC1_DATA3 = SH5, P1-8, Blue Tooth Board Interface

GP[11] = GPIO, SH18, J13-11GP[11] = GPIO11_LCD_PWR, SH20, J19-??

P6 LCD_DATA0 SPI_RX LCD_DATA0 = SH20, J19-14Input LCD_DATA0 = SPI_ALT_RX , SH5, P1-20

N6 LCD_DATA1 SPI_TX LCD_DATA1 = SH20, J19-13LCD_DATA1 = SPI_ALT_D, SH5, P1-18

P7 LCD_DATA2 GP[12] LCD_DATA2 = SH20, J19-12LCD_DATA2 = GPIO12, SH5, P2-13

N7 LCD_DATA3 GP[13] LCD_DATA3 = SH20, J19-11LCD_DATA3 = GPIO13, SH5, P2-20

N8 LCD_DATA4 GP[14] LCD_DATA4 = SH20, J19-10LCD_DATA4 = GPIO14_CC, SH5, P2-15

P9 LCD_DATA5 GP[15] LCD_DATA5 = SH20, J19-9

N9 LCD_DATA6 GP[16] LCD_DATA6 = SH20, J19-8

P10 LCD_DATA7 GP[17] LCD_DATA7 = SH20, J19-7

N10 LCD_DATA8 GP[18]LCD_DATA8 = I2S2_CLK, SH19, U12-2LCD_DATA8 = SPI_CLK, SH17, U9-6LCD_DATA8 = SPI_CLK, SH18, J13-3

LCD_DATA8 = I2S2_CLK, SH19, U12-2



P11 LCD_DATA9 GP[19]LCD_DATA9 = I2S2_FS, SH19, U12-3LCD_DATA9 = SPI_CS0, SH17, U9-1LCD_DATA9 = SPI_CS0, SH18, J13-7LCD_DATA9 = I2S2_FS, SH19, U12-3

N11 LCD_DATA10 GP[20]LCD_DATA10 = I2S2_RX, SG 19, U12-5

LCD_DATA10 = SPI_RX, SH17, U9-2LCD_DATA10 = SPI_RX, SH18, J13-13LCD_DATA10 = I2S2_RX, SH19, U12-5

P12 LCD_DATA11 GP[27]LCD_DATA11 = I2S2_DX, SH19, U12-4LCD_DATA11 = SPI_DX, SH17, U9-5

LCD_DATA11 = SPI_DX, SH18, J13-11LCD_DATA11 = I2S2_DX, SH19, U12-4

N12 LCD_DATA12 GP[28] LCD_DATA12 = UART_RTS, SH5, P1-3LCD_DATA12 = UART_RTX, SH17, U5-12

P13 LCD_DATA13 GP[29] LCD_DATA13 = UART_CTS, SH5, P2-18LCD_DATA12 = UART_CTS, SH 17, U5-10

N13 LCD_DATA14 GP[30] LCD_DATA14 = UART_RX, SH5, P1-7LCD_DATA14 = UART_RX, SH17, U5-15

P14 LCD_DATA15 GP[31] LCD_DATA15 = UART_TX, SH5, P1-9LCD_DATA15 = UART_TX, SH17, U5-13

N3 LCD_EN_RDB SPIO_CLK LCD_EN_RDB = LCD_RE, SH20, J19-15LCD_EN_RDB = LCD_RE = SPI_ALT_CLK, SH5, P1-16

P4 LCD_CS0_E0 SPI_CS0 LCD_CS0_E0 = LCD_BIAS_OE, SH20, J19-19

N4 LCD_CS1_E1 SPI_CS1 LCD_CS1_E1 = LCD_MCLK = SPI_ALT_CS1, SH5, P1-14

P5 LCD_RW_WRB SPI_CS2 LCD_RW_WRB = LCD_nWE, SH20, J19-16

N5 LCD_RS SPI_CS3 LCD_RS = LCD_ALE, SH20, J19-20

Table 1: C5515 GPIO Terminal Functions

C5515 Pin # C5515 Default

Multiplexed Function

GPIO Pin Routed To


1-7

1.5 C5515 EVM Memory Map

The C5515 EVM supports on chip DARAM, off chip SDRAM, off chip NOR flash, andoff chip NAND Flash. The addressing for each of these memory blocks is shown in thefigure below.

MEMORY BLOCKS

Internal DARAM

Internal DARAM

Mobile SDRAM

NOR Flash

Not Used

NAND Flash

Not Used

ROM(if MPNMC=0)

External-CS5 Space(if MPNMC=1)

External-CS0 Space

External-CS2 Space

External-CS3 Space

External-CS4 Space

External-CS5 Space

CPU ByteAddress000000h

0000C0h

010000h

050000h

800000h

C00000h

E00000h

F00000h

FE0000h

FFFFFFh

Figure 1-2, EVM C5515 Memory Map

(MMR Reserved)



1.6 C5515 I2C Addressing

The C5515 EVM has multiple I2C devices for different purposes. The table belowshows the addresses of these devices on the I2C bus.

Table 2: C5515 GIO Schedule

EVM I2C Device I2C Address Function

TLV320AIC3204 0x18 Audio CODEC

INA219 0x40 CPU core power measurement,VDDC, U3

INA219 0x42 CPU DVDD EMIF power measurement,DC_VDD_IO2 U7

INA219 0x43 CPU USB LDO power measurement,USB_VDD_IN, U21

INA219 0x44 CPU DVDD IO power measurement, DC_VDD_IO1, U20

INA219 0x45 CPU 3V3 power measurement,3.3V, U27

INA219 0x46 CPU 1V8 power measurement,1.8V, U23

INA219 0x47 CPU 5V0 power measurement,5V, U24

TPS62023 0x48 PMIC - Not Used

CAT24WC256X 0x50 I2C Interface EEPROM

2-1

Chapter 2

Physical Description

This chapter describes the physical layout of the TMS320C5515 EVMand its connectors.

Topic Page

2.1 Board Layout 2-32.2 Connector Index 2-52.2.1 J1, RS-232 Connector 2-62.2.2 J2, Embedded USB Emulation Connector 2-72.2.3 J3, I2C Probe 2-72.2.4 J4, Headphone Connector 2-82.2.5 J5, HDR4 Connector 2-82.2.6 J6, I2C Probe 2-92.2.7 J7, Stereo Out Connector 2-92.2.8 J8, External JTAG Header 2-102.2.9 J9, Stereo In 1 Connector 2-102.2.10 J10, Daughter Card Interface 2-112.2.11 J11, USB Type B Connector 2-112.2.12 J12, Stereo In 2 Connector 2-122.2.13 J13, Daughter Card Interface 2-122.2.14 J14, Daughter Card Interface 2-132.2.15 J15, MMC/SD Connector 2-142.2.16 J16, +5 Volt In Connector 2-152.2.17 J18, Battery Holder 2-152.2.18 J19, Display Interface 2-162.2.19 M1, Left Microphone 2-162.2.20 M2, Right Microphone 2-162.2.21 Blue Tooth Board Interface 2-172.2.21.1 P1, Blue Tooth Board Interface Connector 2-172.2.21.2 P2, Blue Tooth Board Interface Connector 2-18



Topic Page2.3 System LEDs 2-182.4 C5515 EVM Switches 2-192.4.1 SW1, RESET Switch 2-192.4.2 SW2, WAKEUP Switch 2-192.4.3 SW4, LDO Option DIP Switches 2-202.4.4 SW5, On/Off Switch 2-202.4.5 SW6-SW15, Function Switches 2-212.5 Jumpers 2-222.5.1 C5515 EVM Option Jumpers 2-232.5.1.1 JP2, nRESET Source Select 2-252.5.1.2 JP3, UART_EN Select 2-252.5.1.3 JP5, WAKEUP Source Select 2-262.5.1.4 JP6, LDO_EN Source Select 2-262.5.1.5 JP9, CLK_SEL Source Select 2-272.5.1.6 JP12, MIC_BIAS Source Select 2-272.5.1.7 JP39, VIN Source Select 2-282.5.2 C5515 EVM Power Domain Probe Points 2-292.6 Test Points 2-31


2-3

2.1 Board Layout

The C5515 EVM is a 6.35 x 5.75 inch (161 x 146 mm.) ten (10) layer board whichis powered by an external +5 volt only power supply. Figure 2-1 shows the layout of the top side of the C5515 EVM.

Figure 2-1, TMS320C5515 EVM (Top)

J8

J2

J14

J12

J10

J5

SW2SW1

SW5

J13

SW8

SW12

SW7SW15SW11SW13SW10SW9

J6

D8

DS1M1

M2

J1

J11

J15

SW6 SW14

J16

J9

J7

J4

P1 J3P2

SW4

D2



Figure 2-2 shows the layout of the bottom side of the C5515 EVM.

Figure 2-2, TMS320C5515 EVM (Bottom)

J19

J18


2-5

2.2 Connector Index

The TMS320C5515 EVM has twenty-three (23) connectors which provide the useraccess to the various signals on the EVM.

Table 1: New TMS320C5515 EVM Connectors

Connector / Schematic

Page# Pins Function

Board Side

J1 / 17 9 RS-232 Top

J2 / 25 5 Embedded USB Emulation Port Top

J3 / 15 3 I2C Probe Top

J4 / 19 2 Headphones Out Top

J5 / 19 4 HDR4 Connector Top

J6 / 2 3 I2C Probe Headers Top

J7 / 19 2 Stereo Out Top

J8 / 4 14 JTAG Header Top

J9 / 19 2 Stereo In 1 Top

J10 / 18 10 Daughter Card Interface Top

J11 / 3 4 USB Type B Connector Top

J12 / 19 2 Stereo In 2 Top



J15 / 16 18 MMC/SD Card Top

J16 / 13 2 +5 Volt In Top

J17 / 23 10 Factory use only Bottom

J18 / 13 2 Battery Holder Bottom

J19 / 20 30 Display Interface Bottom

M1 / 19 2 Left Microphone Top

M2 / 19 2 Right Microphone Top

P1 / 5 20 Blue Tooth Board Interface Top

P2 / 5 20 blue tooth Board Interface Top



2.2.1 J1, RS-232 Connector

The C5515 EVM has an RS-232 connector, J1, which brings out the transmit andreceive of the processor. This EVM uses the MAX3222 RS-232 line driver. The pinpositions for the J1 connector as viewed from the edge of the printed circuit board areshown below.

The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a DB-9 connector interface used on personal computers.

Table 2: J1, RS-232 UART Pinout

Pin # Signal Name

1 No Connect

2 RXD

3 TXD

4 No Connect

5 No Connect

6 No Connect

7 RTS

8 CTS

9 GND

10 GND_SHIELD

11 GND_SHIELD

Figure 2-3, J1, DB9 Male Connector

6 7 8 9

1 2 3 4 5


2-7

2.2.2 J2, Embedded USB Emulation Connector

Connector J2 provides a Mini-B Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the EVM. This allows for code development and debugwithout the use of an external emulator. This USB connector is for embedded emulationsupport only.

2.2.3 J3, I2C Probe Headers

Connector J3 brings out the I2C signals from the C5515 processor. The signals areshown in the table below.

Shown below is a top view of the J3 connector.

Table 3: J3, I2C Probe Headers

Pin # Signal Name

1 I2C_SDA

2 I2C_SCL

3 GND

GND

Figure 2-4, Top View of the J3 Connector

SCLSDA

1

J3



2.2.4 J4, Headphone Connector

Connector J4 is a headphone/speaker jack. It can drive standard headphones or ahigh impedance speaker directly. These outputs connect to HEADPHONE LOUT and HEADPHONE_ROUT of the TLV320AIC3204. The standard 3.5 mm jack isshown in the figure below.

2.2.5 J5, HDR4 Connector

The HDR4 connector brings out 4 signals from the TLV320AIC3204. These signals areshown in the table below.


Table 4: J5, HDR4 Connector

Pin # Signal Name

1 AIC_SCLK

2 AIC_MISO

3 AIC_SPI_SEL

4 AIC_MOSI

Left Headphone

Ground

Figure 2-5, Headphone Connector

Right Headphone


AIC_SCLK1J5

AIC_MISO

AIC_SPI_SELAIC_MOSI


2-9

2.2.6 J6, I2C Probe

Connector J6 brings out the I2C signals from the C5515 processor. The signals areshown in the table below.


2.2.7 J7, Stereo Out Connector

The audio line out, J7, is a stereo output. These outputs connect to AIC3254_LOUT and AIC3254_ROUT of the TLV320AIC3204.The output connector is a 3.5 mm stereojack. The signals on the mating plug are shown in the figure below.

Table 5: J6, I2C Probe Headers

Pin # Signal Name

1 I2C_SDA

2 I2C_SCL

3 GND

GND


SCLS

DA

1

J6

Left Line Out

Ground

Figure 2-8, Stereo Out Connector

Right Line Out



2.2.8 J8, External JTAG Header

The TMS320C5515 EVM is supplied with a 14 pin header interface, J8. This is thestandard interface used by JTAG emulators to interface to Texas Instrumentsprocessors. The pinout for the connector is shown in the figure below.

2.2.9 J9, Stereo In 1 Connector

The J9 connector in is a stereo input. The input connector is a 3.5 mm stereo jack.These inputs connect to AIC_LINE2L and AIC_LINE2R of the TLV320AIC3204. Thesignals on the mating plug are shown in the figure below.

1 23 4

5 67 89 1011 1213 14

TMSTDI

VccTDO

RTCK

TCKEMU0

TRST-GNDno pin (key)GND *GND

GNDEMU1

Header DimensionsPin-to-Pin spacing, 0.100 in. (X,Y)

Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 2-9, JTAG INTERFACE

* Embed/External EMU Select

Left Line In

Ground

Figure 2-10, Stereo In 1 Jack

Right Line In


2-11

2.2.10 J10, Daughter Card Interface

The TMS320C5515 EVM has 3 daughter card interfaces, J10, J13, and J14. TheMedical Development Kit (MDK) daughter cards from Texas Instruments use theseinterfaces. For more information about these cards refer to the following web sites:

http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkek1258.htmlhttp://focus.ti.com/docs/toolsw/folders/print/tmdxmdkds3254.htmlhttp://focus.ti.com/docs/toolsw/folders/print/tmdxmdkpo8328.html

Connector J10 is a 2 x 5 double row male header (.1 in. centers) used to interface toplug on daughter cards. The signals on this connector are shown in the table below.

2.2.11 J11, USB Type B Connector

The J11 connector is a USB Type B connector. This connector interfaces directly to theC5515 processor. The signals on this connector are shown in the table below.

Table 6: J10, Daughter Card Interface

Pin # Signal Name Pin # Signal Name

2 NC 1 NC

4 NC 3 NC

6 NC 5 GND

8 NC 7 V1.8

10 V5 9 V3.3

Table 7: J11, USB Type B Connector

Pin # USB Signal C5515 Signal, Pin

1 VBUS USB VBUS, J12

2 D- USB_DM, J14

3 D+ USB_DP, H14

4 GND

5 GND

5 GND



2.2.12 J12, Stereo In 2 Connector

The J12 connector in is a stereo input. The input connector is a 3.5 mm stereo jack.These inputs connect to AIC_LINE3L and AIC_LINE3R of the TLV320AIC3204. Thesignals on the mating plug are shown in the figure below.





1 ADS_GPIO4 2 GPIO11

3 SPI_CLK 4 GND

5 GPIO6 / I2S1_CLK 6 ADS_GPIO10

7 SPI_CS0 8 ADS_GPIO1

9 GPIO7 / I2S1_FS 10 GND

11 SPI_DX 12 ADS_GPIO0

13 SPI_RX 14 GPIO9 / I2S1_RX

15 INT1 16 I2C_SCL

17 XF 18 GND

19 GPIO8 / I2S1_DX 20 I2C_SDA

21 ADS_GPIO3 22 ADS_GPIO2

Left Line In

Ground

Figure 2-11, Stereo In 2 Jack

Right Line In


2-13





2 GPAIN0 1 No connect




10 NC 9 GND

12 NC 11 GND

14 NC 13 GND

16 NC 15 NC

18 NC 17 GND

20 NC 19 GND



2.2.15 J15, MMC/SD Connector

Connector J15 is used to provide a MMC/SD interface to the C5515 processor. Thesignals on this connector are shown in the table below.

Table 10: J15, MMC/SD Connector

Pin # Signal Name

1 MMC0_DATA3

2 MMC0_CMD

3 GND

4 VDD_IO1

5 MMC0_CLK

6 GND

7 MMC0_DATA0

8 MMC0_DATA1

9 MMC0_DATA2

10 WP

11 COM / GND

12 CARD_DETECT

13 No Connect

14 No Connect

15 No Connect

16 No Connect

17 No Connect

18 No Connect


2-15

2.2.16 J16, +5 Volt In Connector

Power (+5 volts) is brought onto the TMS320C5515 EVM via the J16 connector. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. Thediagram of J7 is shown below.

2.2.17 J18, Battery Holder

Connector J18 is a battery holder on the bottom side of the board. This battery holderwill accommodate two (2) “AA” size batteries. The ground and positive voltage from thebattery go to the voltage regulator U26, TPS61030-ADJ. Jumper JP39 is used to selectthe voltage input source (power jack or the battery holder).

PC Board

J16+5V

Ground

Front ViewFigure 2-12, J16, TMS320C5515 EVM Power Connector



2.2.18 J19, Display Interface

Connector J19 provides an interface to a display module. This connector is located onthe bottom side of the board. The signals on this connector are shown in the tablebelow.

2.2.19 M1, Left Microphone

The M1 microphone (left channel) connects to the AIC_MIC1L input of theTLV320AIC3204.

2.2.20 M2, Right Microphone

The M2 microphone (right channel) connects to the AIC_MIC1R input of theTLV320AIC3204.

Table 11: J19, Display Interface


1 GND 16 LCD_nWE / R/Wn

2 V13 17 GND / BS0

3 VCOMH 18 VDD_IO1 / BS1

4 VDD_IO1 / VDDIO 19 LCD_BIAS_OE / CEn

5 VSL 20 LCD_ALE / D/Cn

6 NC 21 nRESET / RESETn

7 LCD_DATA7 / D7 22 IREF

8 LCD_DATA6 / D6 23 GPIO1

9 LCD_DATA5 / D5 24 GPIO0

10 LCD_DATA4 / D4 25 NC-25

11 LCD_DATA3 / D3 26 VDD

12 LCD_DATA2 / D2 27 VDD_IO1 / VCI

13 LCD_DATA1 / D1 28 GND / VSS

14 LCD_DATA0 / D0 29 NC-29

15 LCD_RE / E/RDn 30 GND / NC-30


2-17

2.2.21 Blue Tooth Board Interface Connectors

Connectors P1 and P2 make up the Blue Tooth Board Interface. Both connectors are2 x 10 double row headers and are specifically spaced to interface directly to TexasInstruments Blue Tooth modules.

2.2.21.1 P1, Blue Tooth Board Interface Connector

Connector P1 is a 2 x 10 double row used to interface to plug on daughter cards. Thesignals on this connector are shown in the table below.

Table 12: P1, Blue Tooth Board Interface


1 GND 2 MMC1_DATA0

3 UART_RTS 4 MMC1_DATA1

5 RTC_CLKOUT 6 MMC1_DATA2

7 UART_RX 8 MMC1_DATA3

9 UART_TX 10 GPIO4

11 I2C_SDA 12 GPIO5

13 I2C_SCL 14 SPI_ALT_CS1

15 MMC1_CLK 16 SPI_ALT_CLK

17 MMC1_CMD 18 SPI_ALT_DX

19 GND 20 SPI_ALT_RX



2.2.21.2 P2, Blue Tooth Board Interface Connector

Connector P2 is a 2 x 10 double row used to interface to plug on daughter cards. Thesignals on this connector are shown in the table below.

2.3 System LEDs

TheTMS320C5515 EVM has three light emitting diodes (LEDs). These LEDs indicatevarious conditions on the EVM. These function of each LED is shown in the tablebelow.

Table 13: P2, Blue Tooth Board Interface


1 NC 2 GND

3 NC 4 NC

5 NC 6 NC

7 V3.3 8 I2S1_DX_CC

9 V3.3 10 I2S1_RX_CC

11 I2S1_FS_CC 12 NC

13 GPIO12 14 NC

15 GPIO14_CC 16 NC

17 I2S1_CLK_CC 18 UART_CTS

19 GPIO14_CC 20 GPIO13

Table 14: System LEDs

Reference Designator

Color FunctionSchematic

Page

D2 Green Connected to the XF bit on the C5515 processor 2

D8 Red Indicates +5 volts is applied at the J7 connector 13

DS1 Green Emulator busy N/A


2-19

2.4 C5515 EVM Switches

The C5515 EVM has 14 switches. A list of the switches is shown in the table below:

2.4.1 SW1, RESET Switch

This switch asserts the nRESET signal to all major components on the C5515 EVMboard.

2.4.2 SW2, WAKEUP Switch

“Wakeup” is an active high external input signal used to wake up the core from thepower off state. It can be configured as an active low open drain output signal. Apull up / pull-down jumper (JP5) is provided to accommodate both active high andactive low states.

Table 15: TMS320C5515 EVM Switches

SwitchSilkscreen

Nomenclature/Function

Schematic Page

Board Side

SW1 RESET 14 Top

SW2 WAKEUP 2 Top

SW4 2 Position DIP 14 Top

SW5 Power On/Off 13 Top

SW6 MENU 18 Top

SW7 UP 18 Top

SW8 MODE 18 Top

SW9 SHIFT 18 Top

SW10 REWIND (RWD) 18 Top

SW11 PLAY 18 Top

SW12 FORWARD (FWD) 18 Top

SW13 STOP 18 Top

SW14 DOWN (DN) 18 Top

SW15 REC 18 Top



2.4.3 SW4, LDO Option DIP Switches

SW4 is a 4 position DIP used to select LDO options. The table below shows thefunctions of the 4 positions. When switch is in the “ON” position a logic “0” is applied tothe signal. When the switch is in the “OFF” position a logic “1” is applied to the signal.

* default position

2.4.4 SW5, Power On/Off Switch

The On/Off switch provides +5 volts to the logic on the board. In the “OFF” position thisswitch interrupts the power from the power supply as well as the battery holder.

Table 16: LDO Option DIP Switches

SwitchPosition

SignalState

Signal FunctionDefaultSetting

1 - ON * Low V_CORE_SEL = 1.3V For proper device operation, thisswitch must be in the ON position ON/Low

1 - OFF High V_CORE_SEL = 1.05V

2 - ON * Low VDD_IO1_SEL = 3.3V For proper device operation, thisswitch must be in the ON position ON/Low

2 - OFF High VDD_IO1_SEL = 1.8V

SW4 V_CORE_SEL

VDD_IO1_SELTied to DEFLDO2 on TPS65023

Tied to DEFCDCD1 on TPS65023

Figure 2-13, SW4 Switch

12

ON


2-21

2.4.5 SW6 - SW15, Function Switches

Switches SW6-SW15 are push button momentary switches which are read by theprocessor. These switches can take on any function defined by user software. The silkscreen nomenclature is provided for user convenience and are shown in the tablebelow.

Table 17: Function Switches

Switch # Silk Screen Name

SW6 MENU

SW7 UP

SW8 MODE

SW9 SHIFT

SW10 REWIND (RWD)

SW11 PLAY

SW12 FORWARD (FWD)

SW13 STOP

SW14 DOWN (DN)

SW15 REC



2.5 Jumpers

The C5515 EVM has twenty-nine (29) jumpers locations. These jumpers can bedivided into 3 classes; factory installed options, user options, and power domain probepoints. The following sections describe the jumpers in these classes. The position ofthese jumpers on the top side of the EVM board are shown in the figures below.

JP37

Figure 2-14, TMS320C5515 EVM Jumpers (Top)

JP3 JP4JP1

JP8

JP7JP9JP11

JP17

JP15JP38

JP40

JP13

JP14

JP24

JP21

JP39

JP22

JP12

JP2 JP5

JP18

JP16

JP6

JP19

JP20

JP23

JP26

JP25


2-23

2.5.1 C5515 EVM Option Jumpers

The C5515 EVM’s option jumpers fall into two categories; user selectable, and factoryinstalled. The table below shows lists the user option jumpers and their function.

* Factory default

Table 18: C5515 EVM User Option Jumpers

Jumper #/Schematic

PageNomenclature

# of Positions

Setting Function

JP2 / 12 nRESET Select 31 - 2 * Use RESET from TPS65023

2 - 3 Use RESET from SW1

JP3 / 17 UART_EN 2Shorted * UART transceiver enabled

Open UART transceiver disabled

JP5 / 2 WK_PU_PD_SEL 31 - 2 WAKEUP pin uses pull up

2 - 3 * WAKEUP pin uses pull down

JP6 / 10 LDO_EN 2Shorted * Enable internal DSP LDO

Open Disable internal DSP LDO

JP9 / 3 CLK_SEL 2Shorted CLK_SEL tied to VDD_IO1

Open * CLK_SEL tied to GND

JP12 / 10 MIC_BIAS 31 - 2 Use 3.3V

2 - 3 * Use AIC output

JP39 / 13 VIN Select 31 - 2 Power is from battery

2 - 3 * Power is from external 5v supply



The factory installed jumpers are pre-configured with a zero (0) ohm resistor at thefactory and are not meant to be changed by users. These jumpers are not populatedwith a jumper header. The table below lists the factory installed option jumpers andtheir function.

* Default+ JP6 must be installedZ USB LDO must be enabled in software

Table 19: C5515 EVM Factory Installed Power Domain Configuration

Jumper #/Schematic

PageNomenclature

# of Positions

Setting Function

JP1 / 11 CPU VDDC Select 31 - 2 *+ Internal DSP-LDO used

2 - 3 DSP will use external 1.3 volt

JP4 / 3 RTC 3 1 - 2 * CVDDRTC tied to V1.3

2 - 3 Do Not Use

JP11 / 10 LDOI Select 31 - 2 * LDO_IN tied to V1.8

2 - 3 LDO_IN tied to V3.3

JP15 / 11 USB_VDD_IN Select 31 - 2 *z DSP will use internal USB LDO

2 - 3 DSP will use external 1.3V

JP16 / 10 VDDA_ANA Select 31 - 2 * Internal Analog-LDO used


JP18 / 10 VDDA_PLL Select 31 - 2 * Internal Analog-LDO used



2-25

2.5.1.1 JP2, nRESET Source Select

Jumper JP2 is a three position jumper that allows the user to the select the source ofthe nRESET signal to the C5515 processor. This jumper is pre-configured at thefactory with a jumper in the 2-3 position (*).The table below shows the positions andtheir function.

Shown below is a top view of the JP2.

2.5.1.2 JP3, UART_EN Select

Jumper JP3 is a two position populated jumper that enables/disables the UART driveron the EVM. This jumper is pre-configured at the factory with a jumper in place (*). Thetable below shows the positions and their function.


Table 20: JP2, nRESET Source Select

JumperPosition

Function

1-2 * PWR_RSTn is the source of the nRESET signal to the C5515 Processor

2-3 SW1 is the source of the nRESET signal to the C5515 Processor

Table 21: JP3, UART Enable Jumper

JumperPosition

Function

Open EN_L pulled to GND thereby disabling the MAX3222 line driver

Shorted * EN_L pulled to +3.3 thereby enabling the MAX3222 line driver

Figure 2-15, Top View of the Jumper JP2

JP2

1-2 Position

JP2

2-3 Position

1 1


JP22

ShortedOpen

JP22

UA

RT

_EN

UA

RT

_EN

FactoryConfiguration



2.5.1.3 JP5, WAKEUP Source Select

Jumper JP5 is a three position jumper that allows the user to the select the a pull up orpull down WAKEUP signal to the C5515 processor (U13-E8). This jumper is pre-configured at the factory with a jumper in the 2-3 position (*). The 1-2 positionallows the switch, SW2, to wake up the processor. The table below shows the positionsand their function.


2.5.1.4 JP6, LDO_EN Source Select

Jumper JP6 is a two position jumper located on the top side of the circuit board thatselects the level of the LDO_EN signal. When the jumper is shorted, LDO_EN is pulledto GND enabling on-chip LDO’s. If the jumper is open, LDO_EN is pulled high disablingon-chip LDO’s. This jumper must be installed. The table below shows the positions andtheir function.

* DefaultShown below is a top view of the JP6.

Table 22: JP5, WAKEUP Source Select

JumperPosition

Function

1-2 Depressing switch SW2 wakes up the C5515 Processor (uses pull up)

2-3 * WAKEUP pin uses Pull Down

Table 23: JP6, LDO_EN Select

JumperPosition

Function

Open LDO_EN, is pulled high, LDO’s enabled

Shorted * LDO_EN is low, the internal LDO is enabled

Figure 2-17, Top View of the Jumper JP5 1-2 Position

WK

_PU

_PD

2-3 Position

1JP

5

JP5

1WK

_PU

_PD


JP6

1

JP6

1

ShortedOpen


2-27

2.5.1.5 JP9, CLK_SEL Source Select

Jumper JP9 is a two position jumper that determines if the DSP uses an external orinternal oscillator. The shorted state allows an external oscillator to be used when anoscillator is populated in the 8 pin OSC1 socket. An open jumper means the DSP willuse an internal oscillator. The jumper is pre-configured at the factory in the open state.The table below shows the positions and their function.


2.5.1.6 JP12, MIC_BIAS Source Select

Jumper JP12 is a three position populated jumper that selects the source of themicrophone bias used for AIC MIC1L and AIC MIC1R on the TLV320AIC3204. Thetable below shows the positions and their function.


Table 24: JP9, CLK_SEL Select

JumperPosition

Function

Open * Use internal oscillator for DSP clock

Shorted Use external oscillator for DSP clock

Table 25: JP12, Microphone Bias Select

JumperPosition

Function

1-2 When R209 is installed bias is 3.3 volts

2-3 * Bias from TLV320AIC3204 MICBIAS pin


JP9

CLK

_SE

L

ShortedOpen

FactoryConfiguration

11

JP9

CLK

_SE

L

Figure 2-20, Top View of the Jumper JP12 1-2 Position

MIC

_BIA

S

2-3 Position

MIC

_BIA

S1

JP12

JP12

1



2.5.1.7 JP39, VIN Source Select

Jumper JP39 is a three position populated jumper located on the top side of the circuitboard that selects the source of the incoming +5 volts. The table below shows thepositions and their function.

* defaultShown below is a top view of the JP39 with silkscreen markings.

Table 26: JP39, VIN Source Select

JumperPosition

Function

1 - 2 Battery is selected as source for +5 volts input

2 - 3 * External power supply is selected as source for +5 volts input, J16

Figure 2-21, Top View of the Jumper JP39 1-2 Position 2-3 Position

VIN_SEL VIN_SEL

BATBAT1-2 BAT2-3 5V

1-2 BAT2-3 5V

EXT EXT

JP39 JP39FactorySetting


2-29

2.5.2 C5515 EVM Power Domain Probe Points

The C5515 EVM has pre-designed probe points in the circuitry which could be used toobserve power domains. Several of the power domains have INA219 power monitorsand these domains have a 1 ohm resistor shunted on the EVM. The probe points withpower monitors are shown in the table below.

Shown below is a diagram of a typical Power Domain Probe Point with a one (1) ohmresistor.

Table 27: C5515 EVM Power Probe Points With Power Monitors

Jumper #/Schematic

PageSignal # of Positions

1 Ohm ShuntResistor

Installed atfactory

JP8 / 11 TPS65023_VCC_1V8 2 Monitor

JP17 / 11 C5515 VDD_IO1 2 Monitor

JP20 / 15 V1.8 2 Monitor

JP22 / 13 VIN_EVM 2 Monitor

JP23 / 15 VDD_IO2 2 Monitor - 0

JP25 / 15 V3.3 2 Monitor

JP37 / 11 VDDC 2 Monitor

JP38 / 11 USB_VDD_IN 2 Monitor

Figure 2-22, Diagram of a typical jumper

One (1) ohmresistor



The remaining pre-configured power probe points are shunted with zero (0) ohmresistors as shown below.

Shown below is a diagram of a typical Power Domain Probe Point with a zero (0) ohmresistor.

Table 28: C5515 EVM Power Probe Points With 0 Ohm Resistors

Jumper #/Schematic

PageSignal # of Positions

0 Ohm ShuntResistor

Installed atfactory

JP7 / 19 AIC HPVDD 2 Yes

JP13 / 2 C5515 VDDIO4 2 Yes

JP14 / 19 AIC IOVDD 2 Yes

JP19 / 10 USB_VDDA3P3 2 Yes

JP21 / 15 V1.3 2 Yes

JP24 / 15 VDD_IO1 2 Yes

JP26 / 15 CPU_VCC_CORE 2 Yes

JP40 / 19 AIC AVDD 2 Yes

Figure 2-23, Diagram of a typical jumper

Zero (0) ohmresistor


2-31

2.6 Test Points

The C5515 EVM has forty-one (41) test points. The position of these test pointson the top side of the C5515 EVM are shown in the figures below.

TP28

Figure 2-24, TMS320C5515 EVM Test Points (Top)

TP1

TP5

TP3TP2

TP6

TP8

TP9

TP12

TP29

TP18

TP33

TP30

TP27

TP19

TP15

TP23

TP34

TP14

TP4

TP7

TP24

TP31

TP32

TP25

TP26

TP16

TP11

TP17

TP10

TP22

TP21

TP20



Figure below shows the location of test points on the bottom side of the C5515 EVM.

Figure 2-25, TMS320C5515 EVM Test Points (Bottom)

TP40

TP37

TP36 TP35TP38TP39TP41


2-33

The table below shows the signals present on each user test point.

Table 29: C5515 EVM User Test Points

Test Point #

SignalSchematic

Page #

TP1 GND 11

TP2 nRESET 12

TP3 WAKUP 2

TP4 XF 2

TP5 AIC_GPIO 19

TP6 INT1 2

TP7 INT0 2

TP8 RTC_CLKOUT 2

TP9 CLKOUT 3

TP12 GND 15

TP13 USB_3.3V 27

TP14 GPIO5 18

TP15 GND 19

TP16 VBUS 3

TP17 TPS65023_VCC_3V3 15

TP18 V_PWR_MON 15

TP19 MMC0.WP 16

TP20 INTn 14

TP21 LOWBATn 14

TP22 MMC0.INS 16

TP23 VPWR_IN 13

TP24 GND 17

TP25 PWRFAILn 14

TP26 PWRFAIL_SNS 14

TP27 LOWBAT_SNS 14

TP28 VBATOUT 13

TP29 GND 18

TP30 GND 13

TP31 +5V Input 13

TP32 Battery + 13

TP33 Battery - 13

TP34 GND 3



The table below shows the signals present on each test point used exclusively by thefactory.

Table 30: C5515 EVM Factory Test Points

Test Point #

SignalSchematic

Page #

TP10 USB_1.6V 27

TP11 USB_3.3V 27

TP35 GPIO_1 24

TP36 GPIO_0 24

TP37 CLKOUT 23

TP38 ODEMU1n 24

TP39 ODEMU0n 24

TP40 TCKR 24

TP41 USB_2.5V 27

A-1

Appendix A

Schematics

This appendix contains the schematics for the TMS320C5515 EVM.Board components with designators over 200 (e.g. DS210, R211) arepart of Spectrum Digital’s embedded JTAG emulator and are notincluded in these schematics.


A-2 TMS320C5515 EVM Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

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Titl

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Pa

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Co

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nts

:

B

SP

EC

TR

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DIG

ITA

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NC

OR

PO

RA

TE

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5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01

, 2

01

01

20

B

TM

S32

0C5

515

EV

ALU

AT

ION

MO

DU

LE

TIT

LE S

HE

ET

4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS

OTHERWISE NOTED. THEY ARE SHOWN

ON THE PAGE WITH THE INTEGRATED

CIRCUITS THEY SHOULD BE PLACED NEAR.

NOTES, UNLESS OTHERWISE SPECIFIED:

1. RESISTANCE VALUES IN OHMS.

2. CAPACTITANCE VALUES IN MICROFARADS.

3. REFERENCE DESIGNATORS USED:

Schematic

Contents

01 - TITLE PAGE

02 - TMS320C5515 GPIO / MMC / SPI / I2C

03 - TMS320C5515 CLOCKS / JTAG / USB

04 - EMULATION - JTAG

05 - CC Board Interface

06 - TMS320C5515 EMIF

07 - Mobile DRAM Interface

08 - NAND Flash Interface

09 - NOR Flash Interface

10 - TMS320C5515 Power

11 - CPU Decoupling Caps

12 - RESET

13 - Power Input

14 - TPS65023 Power Management

15 - POWER Router

16- MMC / SD

17 - UART / EEPROMs

18 - SAR Resistor Network

19 - CODEC

20 - COLOR LCD INTERFACE

SHEET

SHEET

SHEET

SHEET

REV

REV

REV

REV

ENGR

2

REVISION STATUS OF SHEETS

1

DATE

DATE

ENGR-MGR

MFG

7

DWN

DATE

8

DATE

DATE

CHK

RLSE

APPLICATION

35

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

4

AA

AA

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

10/15/2009

10/15/2009

10/15/2009

10/15/2009

10/15/2009

10/15/2009

10/15/2009

BA

AA

A

10

11

12

13

14

15

16

A

AB

AB

AA

AA

A

17

18

19

Initial schematic for layout

DESCRIPTION

REV

APPROVED

DATE

10/15/2009

RRP

A

20

A

BUpdate TPS65023 Enable Logic

12/15/2009

RRP


A-3

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GP

AIN

3G

PA

IN2

GP

AIN

1G

PA

IN0

I2C

_S

CL

I2C

_S

DA

GP

[3]

GP

[2]

GP

[1]

GP

[0]

GP

[5]

GP

[4]

LC

D_

RE

LC

D_D

AT

A10

LC

D_D

AT

A11

LC

D_

DA

TA

9L

CD

_D

AT

A8

LC

D_

BIA

S_

OE

LC

D_

MC

LKL

CD

_n

WE

LC

D_

ALE

AD

S_

GP

IO1

0

GP

[9]

GP

[8]

GP

IO1

1

GP

[9]

GP

[8]

GP

[7]

GP

[6]

GP

[11

]G

P[1

0]

LC

D_

DA

TA

2L

CD

_D

AT

A3

LC

D_

DA

TA

4L

CD

_D

AT

A5

LC

D_

DA

TA

6L

CD

_D

AT

A7

LC

D_

DA

TA

8L

CD

_D

AT

A9

LC

D_

DA

TA

10

LC

D_

DA

TA

11

LC

D_

DA

TA

12

LC

D_

DA

TA

13

LC

D_

DA

TA

14

LC

D_

DA

TA

15

LC

D_

DA

TA

0L

CD

_D

AT

A1

WA

KE

UP

RT

C_C

LKO

UT

LC

D_D

AT

A1

5

LC

D_D

AT

A1

2

LC

D_D

AT

A1

3

LC

D_D

AT

A1

4U

AR

T_R

X

UA

RT

_CT

S

UA

RT

_RT

S

UA

RT

_TX

LC

D_

DA

TA

10

LC

D_

DA

TA

9

LC

D_

DA

TA

8

LC

D_

DA

TA

11

SP

I_C

LK

SP

I_C

S0

SP

I_R

X

SP

I_D

X

GP

[5]

GP

[4]

AIC

_R

ST

GP

[10

]

GP

[9]

GP

[8]

GP

[7]

GP

[6]

GP

[11

]

GP

IO1

4_

CC

GP

IO1

1_

LC

D_P

WR

LC

D_

DA

TA

0

LC

D_

DA

TA

1

LC

D_

DA

TA

2

LC

D_

DA

TA

3

GP

IO12

GP

IO13

LC

D_

RE

LC

D_

MC

LK

GP

[3]

GP

[2]

GP

[1]

GP

[0]

GP

[6]

GP

[7]

LC

D_

DA

TA

4

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

VD

DIO

4

XF

18

I2C

_S

DA

5,1

4,1

5,1

7,1

8,19

I2C

_S

CL

5,1

4,1

5,1

7,1

8,1

9INT

013

INT

118

nRE

SE

T1

2,1

9,2

0

GP

AIN

018

GP

AIN

118

GP

AIN

218

GP

AIN

318

LC

D_

RE

20

LC

D_

BIA

S_O

E20

LC

D_

AL

E20

LC

D_

nW

E2

0

I2S

2_

CL

K19

I2S

2_

FS

19

I2S

2_R

X1

9

MM

C0

_CM

D16

MM

C0

_DA

TA

21

6M

MC

0_D

AT

A3

16

MM

C0

_DA

TA

01

6M

MC

0_D

AT

A1

16

MM

C0

_CLK

16

SP

I_C

S0

17,

18

SP

I_C

LK

17,

18

SP

I_D

X17

,18

MM

C1

_CM

D5

MM

C1

_DA

TA

25

MM

C1

_DA

TA

35

MM

C1

_DA

TA

05

MM

C1

_DA

TA

15

MM

C1

_CLK

5

I2S

2_D

X1

9

SP

I_R

X17

,18

UA

RT

_RX

5,1

7

UA

RT

_C

TS

5,1

7

UA

RT

_R

TS

5,1

7

UA

RT

_TX

5,1

7

AD

S_G

PIO

10

18

GP

IO11

18

AD

S_G

PIO

418

AD

S_G

PIO

518

LC

D_

DA

TA

020

LC

D_

DA

TA

120

LC

D_

DA

TA

220

LC

D_

DA

TA

320

LC

D_

DA

TA

420

LC

D_

DA

TA

520

LC

D_

DA

TA

620

LC

D_

DA

TA

720

LC

D_

DA

TA

819

LC

D_

DA

TA

919

LC

D_D

AT

A10

19L

CD

_DA

TA

1119

RT

C_

CLK

OU

T5

GP

IO4

5

GP

IO5

5

AIC

_R

ST

19

I2S

1_F

S18

I2S

1_D

X18

I2S

1_

CL

K1

8

I2S

1_R

X18

I2S

1_

FS

_C

C5

I2S

1_D

X_C

C5

I2S

1_

CLK

_C

C5

I2S

1_R

X_C

C5

GP

IO1

4_C

C5

GP

IO1

1_

LC

D_P

WR

20

SP

I_A

LT_

DX

5

SP

I_A

LT_

RX

5

GP

IO12

5

GP

IO13

5

SP

I_A

LT

_CS

15

SP

I_A

LT

_CL

K5

AD

S_

GP

IO0

18

AD

S_

GP

IO1

18

AD

S_

GP

IO2

18

AD

S_

GP

IO3

18

MM

C0.

WP

16

MM

C0

.IN

S1

6

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01

, 2

01

02

20

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

GP

IO,M

MC

-SD

,SP

I,I2

C,I

2S

I2C

Pro

be P

oint

Hea

ders

PWR JP

C9

30.

1u

F

R2

08

0

R3

90

R2

88

0

R2

80

C1

350

.1u

F

R2

40

R2

02

0

R2

05

0

TP

8R

TC

_CL

KO

UT

R2

870

R2

90

C5

01

uF

R4

60

R4

70

TP

3W

AK

EU

P

R2

70

R1

96

0

R1

41

00K

R2

89

0

R5

10

TP

4X

F

R3

20

I2C DVDDIO

ADC

VDDA_ANA

DVDDIO

DVDDRTC

DVDDIO

DVDDIO

DVDDIO

U1

3A

TM

S32

0C55

15

MM

C0_

CLK

/I2S

0_C

LK/G

P[0

]L1

0

MM

C0_

CM

D/I2

S0_

FS

/GP

[1]

M11

MM

C0_

D0/

I2S

0_D

X/G

P[2

]L9

MM

C0_

D1/

I2S

0_R

X/G

P[3

]M

10

MM

C0_

D2/

GP

[4]

L12

MM

C0_

D3/

GP

[5]

L11

MM

C1_

CLK

/I2S

1_C

LK/G

P[6

]M

13

MM

C1_

CM

D/I2

S1_

FS

/GP

[7]

L14

MM

C1_

D0/

I2S

1_D

X/G

P[8

]M

14

MM

C1_

D1/

I2S

1_R

X/G

P[9

]M

12

MM

C1_

D2/

GP

[10]

K14

MM

C1_

D3/

GP

[1]1

L13

LCD

_D[0

]/SP

I_R

XP

6

LCD

_D[1

]/SP

I_T

XN

6

LCD

_D[2

]/GP

[12]

P7

LCD

_D[3

]/GP

[13]

N7

LCD

_D[4

]/GP

[14]

N8

LCD

_D[5

]/GP

[I5]

P9

LCD

_D[6

]/GP

[16]

N9

LCD

_D[7

]/GP

[17]

P10

LCD

_D[8

]/I2S

2_C

LK/G

P[1

8]/S

PI_

CLK

N10

LCD

_D[9

]/I2S

2_F

S/G

P[1

9]/ S

PI_

CS

0P

11

LCD

_D[1

0]/I2

S2_

RX

/GP

[20]

/SP

I_R

XN

11

LCD

_D[1

1]/I2

S2_

DX

/GP

[27]

/SP

I_T

XP

12

LCD

_D[1

2]/U

AR

T_R

TS

/GP

[28]

/I2S

3_C

LKN

12

LCD

_D[1

3]/U

AR

T_C

TS

/GP

[29]

/I2S

3_F

SP

13

LCD

_D[1

4]/U

AR

T_R

X/G

P[3

0]/I2

S3_

RX

N13

LCD

_D[1

5]/U

AR

T_D

X/G

P[3

1]/I2

S3_

DX

P14

LCD

_EN

_RD

B/S

PI0

_CLK

N3

LCD

_CS

0_E

0/S

PI_

CS

0P

4

LCD

_CS

1_E

1/S

PI_

CS

1N

4

LCD

_RW

_WR

B/S

PI_

CS

2P

5

LCD

_RS

/SP

I_C

S3

N5

INT

1nE

7

INT

0nC

6

RE

SE

Tn

D6

XF

M8

WA

KE

UP

E8

RS

V5_

(GN

D)

C13

RS

V4_

(GN

D)

C14

GP

AIN

3C

11

GP

AIN

2B

11

GP

AIN

1A

11

GP

AIN

0D

10

SC

LB

7S

DA

B8

RT

C_C

LKO

UT

D8

DV

DD

RT

CF

8

R4

20

JP1

3N

O-P

OP

12

R2

04

0

R1

60

R1

20

10K

R1

91

0

R12

41

K

R3

10

R2

01

00K

R3

00

D2

XF

R1

80

R5

00

R2

6

10K

TP

7IN

T0

R4

30

R1

95

0

SW

2

Wak

eup

143

2

R1

30

R3

60

R3

50

R1

930

TP

6IN

T1

R2

20

R3

70

R3

40

R1

9

10K

J6

HE

AD

ER

3

1 2 3

R1

20

R3

30

R2

15

0

R2

50

R1

12

10K

JP

5

WA

KE

UP

_PU

-PD

_S

EL

1 2 3

R4

00



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

US

B_X

I

CL

KIN

OS

C_V

NC

-CL

KO

UT

US

B_X

O

US

B_R

1

US

B_V

BU

S

US

B_D

MU

SB

_D

P

VD

D_

IO1

V3

.3

V3

.3

CP

U_

3V

3_U

SB

AG

ND

V1

.3

VD

DC

VD

D_

IO1

AU

DIO

_M

CL

K19

TA

RG

ET

_TM

S4

TA

RG

ET

_TR

ST

n4

TA

RG

ET

_TD

I4

TA

RG

ET

_TD

O4

TA

RG

ET

_TC

K4

TA

RG

ET

_EM

U0

4

TA

RG

ET

_EM

U1

4

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-0

001

We

dn

esd

ay,

Fe

bru

ary

03

, 2

01

03

20

B

TM

S32

0C5

515

EV

ALU

AT

ION

MO

DU

LE

CL

OC

K,J

TA

G,U

SB

DIR=H : A to B

DIR=L : B to A

Place as

close as

possible

to Y2

PLACE CLOSE TO TCK PIN

CLK_SEL

C5

81

0uF

R1

89 0

R2

0710

K

C3

93

3pF

C1

77

0.1

uF

C1

61

0.0

1u

F

R1

13

NO

-PO

P

R1

74

100

R5

5N

O-P

OP

R5

40

R2

30

C1

62

1u

F

JP4

NO

-PO

P

1 2 3

Y1

32.

768

KH

z

14

23

R1

79

0

Y2

12.

000

MH

z

OS

C1

Osc

illat

or

So

cke

t

OE

_81

NC

-22

NC

-33

GN

D4

VC

C_8

8

NC

-77

NC

-66

OU

T5

C3

13

3pF

R1

16

0

TP

16V

BU

S

USBVDD_OSC

DVDDIO

DVDDIO

CVDDRTC

U1

3D

TM

S32

0C55

15

US

B_M

XI

G13

US

B_M

XO

G14

CLK

INA

8

CLK

OU

TA

7

TR

ST

NM

9

TM

SL8

TD

IL7

TD

OM

7

TC

KM

6

EM

U0

L6

EM

U1

M5

US

B_D

PH

14U

SB

_DM

J14

US

B_R

1G

9

RT

CX

OA

9

RT

CX

IB

9

US

B_V

BU

SJ1

2

CLK

_SE

LC

7

US

B_V

SS

RE

FG

10

VS

S_R

TC

C9

US

B_V

SS

OS

CF

11

US

BV

DD

_OS

CG

12

CV

DD

RT

CC

8

R2

10

47K

R1

5710

K

R1

17

0

R2

17

NO

-PO

P

FB

6

BLM

21P

G22

1SN

1D1

2

C4

73

3pF

TP

9

CL

KO

UT

R56

0

R2

01

10K

1%

R16

8

10K

R2

36

100K

D3

6.2

V

R57

0

C5

7

10

uF

J11

US

B-B

co

nn

ect

or

VB

US

1

D-

2

D+

3

GN

D4

S2

5

S1

6

U1

1

SN

74A

VC

1T

45

VC

CA

1

GN

D2

A3

B4

DIR

5V

CC

B6

R1

9933

JP

9PO

P1

2

C1

52

0.1

uF

C4

83

3pF

C16

9

100

0pF

C9

91

uF

C1

30

15p

F

TP

34

GN

D

R4

9N

O-P

OP


A-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

T_

TC

K

T_

TD

OT

_E

MU

0

EM

BE

D_

EM

U_X

RS

pT

_TR

ST

nT_

TM

ST

_T

DI

EM

BE

D_E

MU

_SE

Ln

TA

RG

ET

_TR

ST

n

TA

RG

ET

_T

MS

TA

RG

ET

_TD

I

TA

RG

ET

_TC

K

T_

TC

K_R

ET

TA

RG

ET

_TD

O

TA

RG

ET

_EM

U0

TA

RG

ET

_EM

U1

T_

EM

U1

EM

BE

D_

EM

U_S

ELn

GN

D

EM

BE

D_

EM

U_S

ELn

3V3

_EM

U

3V

3_E

MU

VD

D_

IO1

3V3

_EM

UV

DD

_IO

1

VD

D_I

O1

VD

D_

IO1

3V3

_EM

U

3V

3_E

MU

VD

D_

IO1

TA

RG

ET

_EM

U1

3

TA

RG

ET

_EM

U0

3

TA

RG

ET

_TC

K3

TA

RG

ET

_TM

S3

TA

RG

ET

_TR

ST

n3

TA

RG

ET

_TD

I3

TA

RG

ET

_TD

O3

EM

BE

D_E

MU

_X

RS

p12

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-

000

1

Mo

nd

ay,

Fe

bru

ary

01

, 2

010

42

0

B

TM

S3

20C

5515

EV

ALU

AT

ION

MO

DU

LE

JTA

G I

NT

ER

FA

CE

USBSEL - HIGH, SELECT EMBEDDED EMULATION

USBSEL - LOW, SELECT EXTERNAL XDS EMULATION

DIR AND OEn ARE ON A POWER DOMAIN

OEn DIR FUNCTION

L L B->A

L H B<-A

OEn DIR FUNCTION

L L B->A

L H B<-A

REMOVE IF USING BOARD ON QUICKTURN

C4

5

10

0nF

R2

32

33

R1

76

NO

-PO

P

R22

0

100K

R2

29

33

R2

21N

O-P

OP

R2

25

33

C1

67

0.1

uF

R1

75

10K

R2

33

10K

R2

16

10K

Q3

BS

S13

8G

D S

R2

14

33

R4

8

10K

R2

30

33

C1

63

0.1

uF

R2

13

33

R2

00

1K

R2

12

0

R2

110

U2

2

SN

74A

VC

4T24

5PW

RE

4

1B1

13

1B2

12

2B1

11

2B2

10

1A1

4

1A2

5

2A1

6

2A2

7

1DIR

2

1OE

n15

2DIR

3

2OE

n14

VC

CB

16V

CC

A1

GN

D.2

9G

ND

.18

R1

85

NO

-PO

P

R2

22

100K

R2

28

33

U1

9

SN

74A

VC

4T24

5PW

RE

4

1B1

13

1B2

12

2B1

11

2B2

10

1A1

4

1A2

5

2A1

6

2A2

7

1DIR

2

1OE

n15

2DIR

3

2OE

n14

VC

CB

16V

CC

A1

GN

D.2

9G

ND

.18

C1

75

0.1

uF

US

B1_

1

Em

bed

ded

_US

B

GN

D

3V3_

EM

U

T_T

CK

_RE

TT

_TC

K

T_T

MS

T_T

DI

T_T

DO

T_E

MU

0T

_EM

U1

T_T

RS

Tn

DS

P_R

S_O

UT

p

T_P

WR

LOS

Sn

C1

74

0.1

uF

Key

J8

JTA

GTM

S1

nTR

ST

2

TD

I3

44

Vcc

5

TD

O7

88

RT

CK

910

10

TC

K11

1212

EM

U0

13E

MU

114

66



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GP

IO4

GP

IO5

V3.

3

I2C

_S

DA

2,1

4,1

5,17

,18

,19

I2C

_S

CL

2,1

4,1

5,1

7,1

8,1

9I2

S1

_C

LK

_C

C2

UA

RT

_R

X2

,17

GP

IO4

2G

PIO

52

UA

RT

_R

TS

2,1

7

UA

RT

_TX

2,1

7 MM

C1

_CLK

2

MM

C1_

DA

TA

32

I2S

1_

RX

_CC

2I2

S1_

DX

_C

C2

I2S

1_

FS

_C

C2

UA

RT

_C

TS

2,1

7G

PIO

14

_C

C2

MM

C1_

DA

TA

22

MM

C1_

DA

TA

12

MM

C1_

DA

TA

02

MM

C1

_CM

D2R

TC

_C

LK

OU

T2

GP

IO1

22

GP

IO13

2S

PI_

ALT

_DX

2S

PI_

ALT

_RX

2

SP

I_A

LT_

CLK

2S

PI_

ALT

_C

S1

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

52

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

CC

BO

AR

D I

NT

ER

FA

CE

NOTE: DIMENSIONS AND LOCATIONS OF THESE CONNECTORS MUST MEET SPECIFICATION FOR INTERFACE MODULES

P1

HE

AD

ER

10X

2

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

P2

HE

AD

ER

10

X2

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_WA

IT4

EM

_WA

IT5C

PU

_A

9

CP

U_

A7

CP

U_

A1

1

CP

U_

A8

CP

U_

A6

CP

U_

A1

0

CP

U_

A1

2

CP

U_

A1

4

CP

U_

A1

3

CP

U_

A1

5

CP

U_

A1

7C

PU

_A

18

CP

U_

A1

9

CP

U_

A1

6

CP

U_

A2

0

CP

U_

A5

CP

U_

A2

CP

U_

A0

CP

U_

A4

CP

U_

A3

CP

U_

A1

CP

U_

BA

1C

PU

_B

A0

CP

U_

EM

_C

S5n

CP

U_

EM

_C

S2n

CP

U_

EM

_C

S3n

EM

_CS

2n

CP

U_

EM

_C

S4n

D1

5

D8

D1

3D

14

D1

0

D1

2D

11

D9

SD

CA

S

DQ

M0

SD

CK

E

SD

CL

K

DQ

M1

SD

RA

S

CP

U_

SD

CL

K

CP

U_

SD

CA

S

CP

U_

SD

CK

E

CP

U_

DQ

M1

CP

U_

DQ

M0

CP

U_

SD

RA

S

D7

D0

D2

D4

D6

D1

D3

D5

OE

WE

CP

U_

Rn

W

CP

U_

WE

CP

U_

OE

CP

U_

SD

CE

0

EM

_CS

4n

A2

CP

U_

A14

CP

U_

A15

CP

U_

A18

CP

U_

A19

CP

U_

A20

A14

A15

A17

A18

A19

A16

A20

A6

A10

A13

CP

U_

A16

CP

U_

A6

CP

U_

A17

CP

U_

A9

CP

U_

A7

CP

U_

A8

CP

U_

A11

CP

U_

A12

CP

U_

A10

CP

U_

A13

A9

A7

A11

A8

A12

CP

U_

A2

CP

U_

A5

CP

U_

A3

CP

U_

A4

CP

U_

A0

CP

U_

A1

CP

U_

BA

1C

PU

_B

A0

A5

A0

A4

A3

A1

BA

1B

A0

EM

_WA

IT2

EM

_WA

IT3

SD

_C

EX

n

EM

_WA

IT2

9

EM

_WA

IT4

8

EM

_CS

2n9

D8

7,9

D9

7,9

D1

07

,9D

11

7,9

D1

27

,9D

13

7,9

D1

47

,9D

15

7,9

SD

RA

S7

SD

CA

S7

DQ

M0

7

DQ

M1

7

SD

CL

K7

SD

CK

E7

D0

7,8

,9D

17

,8,9

D2

7,8

,9D

37

,8,9

D4

7,8

,9D

57

,8,9

D6

7,8

,9D

77

,8,9

OE

8,9

WE

7,8

,9

SD

_C

EX

n7

EM

_CS

4n

8

A2

7,9

A14

9A

159

A16

9

A17

9A

189

A19

9

A20

9

A6

7,9

A10

7,9

A13

9

A7

7,9

A8

7,9

A9

7,9

A11

7,8

,9A

128

,9

A0

7,9

A1

7,9

A3

7,9

A4

7,9

A5

7,9

BA

17

,9B

A0

7,9

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01

, 2

01

06

20

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

TM

S32

0C55

15 E

MIF

R15

10

R15

42

2

R11

92

2

R1

710

KR

15

10K

R15

02

2R

283

NO

-PO

P

R11

82

2

RN

6R

PA

CK

8-2

2

123456789 10 11 12 13 14 15 16

RN

7R

PA

CK

8-2

2

123456789 10 11 12 13 14 15 16

R15

32

2

R15

22

2

R15

62

2

R15

92

2

DVDDEMIF

U1

3C

TM

S32

0C55

15

EM

_A[0

]B

2E

M_A

[1]

C2

EM

_A[2

]E

1E

M_A

[3]

D2

EM

_A[4

]C

1E

M_A

[5]

D1

EM

_A[6

]F

1E

M_A

[7]

H2

EM

_A[8

]J1

EM

_A[9

]J2

EM

_A[1

0]L2

EM

_A[1

1]/(

ALE

)K

2E

M_A

[12]

/(C

LE)

K1

EM

_A[1

3]L1

EM

_A[1

4]M

1E

M_A

[15]

/GP

[21]

N1

EM

_A[1

6]/G

P[2

2]E

2E

M_A

[17]

/GP

[23]

F2

EM

_A[1

8]/G

P[2

4]G

2E

M_A

[19]

/GP

[25]

G4

EM

_A[2

0]/G

P[2

6]J3

EM

_BA

[0]

A1

EM

_BA

[1]

B1

SD

CK

EN

2

SD

CA

Sn

B4

SD

RA

Sn

A6

EM

_DQ

M1

P1

EM

_DQ

M0

B5

EM

_SD

CLK

M3

EM

_WE

nH

1

EM

_OE

nE

4

SD

_CE

0nB

3

SD

_CE

1nA

4

EM

_WA

IT4

G1

EM

_WA

IT5

H4

EM

_WA

IT2

D5

EM

_WA

IT3

K6

EM

_CS

2nC

5

EM

_CS

3nM

4

EM

_R/W

nB

6

EM

_CS

5nA

3E

M_C

S4n

C3

EM

_D[0

]G

3E

M_D

[1]

E5

EM

_D[2

]F

3E

M_D

[3]

D4

EM

_D[4

]L4

EM

_D[5

]M

2E

M_D

[6]

K5

EM

_D[7

]H

3

EM

_D[8

]E

3E

M_D

[9]

F4

EM

_D[1

0]D

3E

M_D

[11]

C4

EM

_D[1

2]L3

EM

_D[1

3]K

4E

M_D

[14]

K3

EM

_D[1

5]J4

R15

52

2

RN

5R

PA

CK

8-2

2

123456789 10 11 12 13 14 15 16

R15

82

2



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

A2

A1

A0

A5

A4

A3

A11

A10

A9

A7

A8

A6 B

A1

BA

0

WE

SD

_C

EX

n

SD

CLK

SD

CA

SS

DC

KE

DQ

M1

DQ

M0

SD

RA

S

SD

RA

M_D

10S

DR

AM

_D11

SD

RA

M_D

6S

DR

AM

_D7

SD

RA

M_D

0S

DR

AM

_D1

SD

RA

M_D

13S

DR

AM

_D12

SD

RA

M_D

2S

DR

AM

_D3

SD

RA

M_D

5S

DR

AM

_D4

SD

RA

M_D

15S

DR

AM

_D14

SD

RA

M_D

8S

DR

AM

_D9

D2

D3

D5

D4

D1

5D

14

D8

D9

D1

0D

11

D6

D7

D0

D1

D1

3D

12

SD

RA

M_

D2

SD

RA

M_

D3

SD

RA

M_

D5

SD

RA

M_

D4

SD

RA

M_

D1

5S

DR

AM

_D

14

SD

RA

M_

D8

SD

RA

M_

D9

SD

RA

M_

D1

0S

DR

AM

_D

11

SD

RA

M_

D6

SD

RA

M_

D7

SD

RA

M_

D0

SD

RA

M_

D1

SD

RA

M_

D1

3S

DR

AM

_D

12

VD

D_

IO2

DQ

M1

6D

QM

06

WE

6,8

,9 SD

_C

EX

n6

SD

RA

S6

SD

CA

S6

SD

CLK

6

SD

CK

E6

A0

6,9

A1

6,9

A2

6,9

A3

6,9

A4

6,9

A5

6,9

A6

6,9

A7

6,9

A8

6,9

A9

6,9

A10

6,9

BA

06

,9

A11

6,8

,9

BA

16

,9

D0

6,8

,9D

16

,8,9

D2

6,8

,9D

36

,8,9

D4

6,8

,9D

56

,8,9

D6

6,8

,9D

76

,8,9

D8

6,9

D9

6,9

D10

6,9

D11

6,9

D12

6,9

D13

6,9

D14

6,9

D15

6,9

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

72

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

MO

BIL

E S

DR

AM

C9

7

0.1

uF

C8

8

0.1

uF

C9

0

0.1

uF

C9

4

0.1

uF

C8

9

0.1

uF

C10

1

0.1

uF

+ C8

74

.7u

F

RN

1R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

U4

MT

48H

4M16

LF

VC

C1

A9

DQ

0A

8

VC

CQ

1A

7

DQ

1B

9

DQ

2B

8

DQ

3C

9

DQ

4C

8

VC

CQ

2B

3

DQ

5D

9

DQ

6D

8

DQ

7E

9

VC

C2

E7

WE

F9

RA

SF

8

CS

G9

BA

0G

7

BA

1G

8

A10

H9

A0

H7

A1

H8

A2

J8

A3

J7

VC

C3

J9

A4

J3

A5

J2

A6

H3

A7

H2

A8

H1

A9

G3

A11

G2

CLK

F2

VC

CQ

3C

7

DQ

10D

1

VC

CQ

4D

3

DQ

8E

1

DQ

9D

2

CA

SF

7

CK

EF

3

DQ

MH

F1

DQ

ML

E8

DQ

11C

2

DQ

12C

1

DQ

13B

2

DQ

14B

1

DQ

15A

2

VS

SQ

1A

3

VS

SQ

2B

7

VS

SQ

3C

3

VS

SQ

4D

7

NC

1E

2

VS

S1

A1

VS

S2

E3

VS

S3

J1

NC

2G

1

RN

2R

PA

CK

8-1

01 2 3 4 5 6 7 8

910111213141516

C9

8

0.1

uF


A-9

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

A11

ALE

A12

CL

E

D1

D2

D3

D4

D5

D6

D7

D0

VD

D_

IO2

VD

D_

IO2

OE

6,9

WE

6,7

,9EM

_C

S4

n6E

M_W

AIT

46

D0

6,7

,9D

16

,7,9

D2

6,7

,9D

36

,7,9

D4

6,7

,9D

56

,7,9

D6

6,7

,9D

76

,7,9

A12

6,9

A11

6,7

,9

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01

, 2

01

08

20

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

NA

ND

FL

AS

H

NA

ND

C8

2

0.1

uF

C8

6

0.1

uF

+C

78

10

uF

R1

07

10K

R10

4

10K

U2A

K9

F1

20

8R

0C-J

IB0

Vss

.1A

3

R/B

A6

RE

B2

CE

A4

Vcc

F6

Vss

.2H

1

CLE

B3

ALE

A2

WE

A5

WP

A1

I/O7

G6

I/O6

H5

I/O5

G5

I/O4

H4

Vcc

QG

4

Vss

.3H

6

I/O3

H3

I/O2

H2

I/O1

G2

I/O0

F2

U2

B

K9

F1

20

8R

0C

-JIB

0

N.C

.11

N.C

.22

N.C

.33

N.C

.44

N.C

.55

N.C

.66

N.C

.77

N.C

.88

N.C

.99

N.C

.10

10

N.C

.11

11

N.C.12 12

N.C.13 13

N.C.14 14

N.C.18 B5N.C.17 B4N.C.16 B1N.C.15 15

23.N

.C.

C4

N.C.22 C3N.C.21 C2N.C.20 C1N.C.19 B6

28.N

.C.

D3

26.N

.C.

D1

25.N

.C.

C6

24.N

.C.

C5

29.N

.C.

D4

30.N

.C.

D5

31.N

.C.

D6

32.N

.C.

E1

33.N

.C.

E2

34.N.C.E335.N.C.E436.N.C.E537.N.C.E638.N.C.F139.N.C.F340.N.C.F441.N.C.F542.N.C.G143.N.C.G3

27.N

.C.

D2



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

1V

8_S

YS

_RE

SE

Tz

FL

AS

H_

WP

n

EM

_C

S2n

D1

5

D7

D0

D2

D4

D6

D1

D3

D5

D8

D1

3

D9

D1

1D

12

D1

0

D1

4

A9

A7

A11

A8

A5

A6

A10

A12

A14

A13

A15

A4

A17

A3

A18

A19

A16

A20

A0

A1

A2

BA

1

BA

0V

DD

_IO

2

VD

D_I

O2

VD

D_

IO2

D0

6,7

,8D

16,

7,8

D2

6,7

,8D

36,

7,8

D4

6,7

,8D

56,

7,8

D6

6,7

,8D

76,

7,8

D8

6,7

D9

6,7

D1

06

,7D

11

6,7

D1

26

,7D

13

6,7

D1

46

,7D

15

6,7

A0

6,7

A1

6,7

A2

6,7

A3

6,7

A4

6,7

A5

6,7

A6

6,7

A7

6,7

A8

6,7

A9

6,7

A10

6,7

A11

6,7

,8A

126

,8A

136

A14

6A

156

A16

6A

176

A18

6A

196

A20

6

BA

16

,7

BA

06

,7

OE

6,8

WE

6,7

,8EM

_CS

2n6

EM

_W

AIT

26

1V

8_S

YS

_R

ES

ET

z12

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

92

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

NO

R F

LA

SH

U1

PC

28F

12

8P30

T85

A1

A1

A2

B1

A3

C1

A4

D1

A5

D2

A6

A2

A7

C2

A8

A3

A9

B3

A10

C3

A11

D3

A12

C4

A13

A5

A14

B5

A15

C5

A16

D7

A17

D8

A18

A7

A19

B7

A20

C7

D0

F2

D1

E2

D2

G3

D3

E4

D4

E5

D5

G5

D6

G6

D7

H7

D8

E1

D9

E3

D10

F3

D11

F4

D12

F5

D13

H5

D14

G7

D15

E7

VS

S.3

H2

VS

S.1

B2

VS

S.2

H4

CE

B4

OE

F8

WE

G8

RS

Tn

D4

WP

nC

6

A21

C8

CLK

E6

AD

VF

6

WA

ITF

7

A22

A8

A23

G1

NC

/A24

H8

VC

C.1

H3

VC

C.2

A6

VC

CQ

.1D

5

VS

S.4

H6

VC

CQ

.3D

6

VP

PA

4

RF

U.3

G2

RF

U.2

H1

RF

U.1

F1

NC

/A25

B6

VC

CQ

.2G

4

RF

U.5

E8

RF

U.4

B8

C7

6.1

uF

R1

06

0

C77

.1uF

C8

1.1

uF

R1

03

NO

-PO

P

R1

01

NO

-PO

P

C8

4.1

uF

R1

05

10K


A-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PM

_C

TL

LD

O_

EN

RS

V6

PO

R_

BG

RS

T

LD

O_I

N

DC

_V

DD

_IO

1

DC

_V

DD

_S

AR

SA

R_

LDO

12

LD

O_

IN

DS

P_

LD

O1

.3D

SP

_LD

O_O

UT

US

B_

LDO

_O

UT

LD

O_

IN

SA

R_

LDO

12

LD

O_

IN

DC

_V

DD

_IO

2

PO

R_B

GR

ST

RS

V6

PM

_CT

LL

DO

_E

N

V3

.3

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

PLL

V1

.3

VD

D_

SA

R

CP

U_

3V

3_U

SB

AG

ND

PLL

AG

ND

AG

ND

CP

U_

3V3

_U

SB

US

B_

LDO

_OU

T

LD

O_

IN

DS

P_

LDO

_OU

T

V3

.3

V1

.8

SA

R_

LDO

12

SA

R_

LD

O1

2

DC

_V

DD

_IO

2

DC

_V

DD

_IO

1

VD

DC

LD

O_

IN

US

B_V

DD

_IN

LD

O_

IN

LD

O_I

N

V1

.3

VD

D_

SA

R

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01

, 2

01

010

20

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

TM

S32

0C55

15 P

OW

ER

PWR JP

SAR LDOI SEL

PWR JP

DSP LDOI SEL

DSP_LDO_EN:

If high, the DSP_LDOO is tri-stated

If low, the DSP_LDOO is 1.3V or 1.05V

depending on DSP_LDO_V

C1

72

10

00pF

C1

50

0.1

uF

JP11

NO

-PO

P

A1 B2

C 3

FB

10

BLM

21P

G22

1S

N1D

12

R66100K

C1

39

0.1

uF

C1

70

10

00p

F

R2

230

R1

82N

O-P

OP

C1

55

0.1

uF

FB

9

BLM

21P

G22

1S

N1D

12

FB

7

BL

M2

1P

G22

1SN

1D1

2

R2

18

NO

-PO

P

FB

5

BLM

21A

G1

51S

N1D

12

R2

840

C5

51

0uF

JP18

NO

-PO

P

A1 B2

C 3

R2

85

0

C1

58

0.1

uF

C1

54

0.1

uF

C1

510

.1u

F

C1

34

0.0

1uF

R2

26

0

JP19

NO

-PO

P1

2

R2

82N

O-P

OP

R65100K

R2

860

C5

1

1uF

R2

31

0

JP1

6N

O-P

OP

A1 B2

C 3

C1

37

0.1

uF

FB

3

BL

M2

1A

G1

51S

N1D

12

R64100K

C54

10

uF

U1

3B

TM

S32

0C55

15

DV

DD

EM

IF.1

A2

DV

DD

EM

IF.2

A5

DV

DD

EM

IF.3

E6

DV

DD

EM

IF.4

F5

DV

DD

EM

IF.5

G5

DV

DD

EM

IF.6

H5

DV

DD

EM

IF.8

J5

CV

DD

.5L5

DV

DD

EM

IF.9

P2

VS

SA

_AN

A.1

B10

VS

S.1

A13

VS

S.2

A14

VS

S.7

E12

VS

S.8

E13

CV

DD

.1F

6

CV

DD

.2H

8

CV

DD

.3J6

CV

DD

.4K

10

US

B_V

DD

PLL

G8

US

B_V

SS

PLL

G11

US

B_V

DD

A1P

3H

10

US

B_V

SS

A1P

3H

9

US

B_V

DD

A3P

3H

12

US

B_V

SS

A3P

3H

11

US

B_V

DD

1P3

J13

US

B_V

SS

1P3

H13

RS

V6

D13

DS

P_L

DO

_EN

D12

LDO

I.3F

13

US

B_L

DO

OF

12

LDO

I.1B

12

AN

A_L

DO

A12

VD

DA

_AN

AA

10

VS

SA

_AN

A.2

B14

VD

DA

_PLL

C10

VS

SA

_PLL

D9

RS

V1(

CV

DD

)J1

1

RS

V2(

CV

DD

)J1

0

(RS

V3)

PM

_CT

LD

14

BG

_CA

PB

13

(RS

V0)

PO

R_B

GR

ST

C12

LDO

I.2F

14

DS

P_L

DO

OE

10

DV

DD

IO.1

F7

DV

DD

IO.2

K7

DV

DD

IO.3

K12

DV

DD

IO.4

N14

DV

DD

IO.5

P3

DV

DD

IO.6

P8

VS

S.5

E9

VS

S.1

1F

10

VS

S.1

9K

9V

SS

.18

K8

VS

S.1

7J9

VS

S.1

5J7

VS

S.2

0K

11

VS

S.1

6J8

VS

S.1

4H

6

VS

S.2

1K

13

VS

S.1

3G

7V

SS

.12

G6

VS

S.6

E11

VS

S.4

D11

VS

S.1

0F

9

VS

S.3

D7

VS

S.9

E14

DV

DD

EM

IF.7

H7

R2

340

R1

94

0

C1

470

.1u

F

FB

2

BLM

21A

G1

51S

N1D

12

C53

1u

F

JP6

JUM

PE

R 2

A 1B2

FB

8

BLM

21P

G22

1S

N1D

12

R6

71

00K

C5

6

10

uF

C1

73

0.0

1u

F

R1

810

C1

42

0.1

uF

C1

71

1000

pF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VD

DC

DC

_V

DD

_IO

1

DC

_V

DD

_IO

2

I2C

_S

DA

_P

WR

I2C

_S

CL_

PW

R

I2C

_S

DA

_P

WR

I2C

_S

CL

_P

WR

DS

P_L

DO

_O

UT

I2C

_S

DA

_P

WR

I2C

_S

CL

_P

WR

I2C

_S

DA

_P

WR

I2C

_S

CL

_P

WR

US

B_L

DO

_O

UT

VD

DC

DC

_V

DD

_IO

1

DC

_VD

D_

IO2

V_

PW

R_M

ON

DC

_V

DD

_IO

2

VD

D_

IO1

DC

_V

DD

_IO

1

V_

PW

R_M

ON

CP

U_

VC

C_

CO

RE

VD

DC

DS

P_

LDO

_O

UT

V_

PW

R_M

ON

V_

PW

R_M

ON

V1

.3

US

B_L

DO

_O

UT

US

B_

VD

D_

IN

V_

PW

R_

MO

N

TP

S65

023

_VC

C_1

V8

I2C

_S

DA

_P

WR

13

,15

I2C

_S

CL

_P

WR

13,1

5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

112

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

CP

U D

EC

OU

PL

ING

CA

PS

I

I

I

I

NO-POP

NO-POP

U3

INA

21

9ID

CN

VIN+1

VIN-2

GND 3

VS 4

SCL 5

SDA 6

A0 7A1 8

R1

1 1

%

C1

18

0.1

uF

R1

02

NO

-PO

P

JP8

NO

-PO

P1

2

C1

66

0.1

uF

C12

2

1u

F

C1

11

0.0

1u

F

C1

29

0.1

uF

C1

10

0.1

uF

C1

57

0.1

uF

C1

48

1uF

C46

10

uF

C1

44

0.0

1u

F

C14

1

0.1

uF

C1

65

0.1

uF

C10

6

0.1

uF

R2

24

1 1

%

C12

4

0.1

uF

JP3

71

2

C2

2

10u

FC

133

0.0

1u

F

C8

30

.1u

F

C1

60

0.1

uF

U7

INA

21

9ID

CN

VIN+1

VIN-2

GND 3

VS 4

SCL 5

SDA 6

A0 7A1 8

JP3

8

12

C1

27

0.0

1uF

JP1

7NO

-PO

P

12

C1

16

1u

F

R5

91

1%

U2

1IN

A2

19

IDC

N

VIN+1

VIN-2

GND 3

VS 4

SCL 5

SDA 6

A0 7A1 8

JP1

5N

O-P

OP

A 1B2

C3

C1

05

0.1

uF

C1

32

1u

F

C1

53

0.1

uF

R2

19

NO

-PO

P

C1

09

0.1

uF

C1

13

0.1

uF

C1

19

0.1

uF

R1

08

0

TP

1

GN

D

C1

40

0.1

uF

U2

0IN

A2

19

IDC

N

VIN+1

VIN-2

GND 3

VS 4

SCL 5

SDA 6

A0 7A1 8

R1

461

1%

R2

27 0

C1

020

.1uF

C1

25

0.0

1u

F

C1

59

0.1

uF

JP1

NO

-PO

P

A 1B2

C3

C1

20

1uF


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

1V

8_S

YS

_R

ES

ET

z

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

VD

D_

IO2

VD

D_

IO1

EM

BE

D_E

MU

_XR

Sp

nRE

SE

T2

,19

,20

PW

R_

RS

Tn

14

PB

_RE

SE

T14

1V

8_S

YS

_R

ES

ET

z9

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

122

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

RE

SE

T

Q4

BS

S1

38G

D S

R1

8333

JP2

HE

AD

ER

3

1 2 3

C7

9.1

uF

C8

0.1

uF

TP

2n

RE

SE

T

R1

09

100

K

R1

98

10K

R2

0310

K

C7

5

100

nF

R1

00

100K

U2

9

SN

74

AV

C1T

45

VC

CA

1

GN

D2

A3

B4

DIR

5V

CC

B6



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

V5

VIN

_E

VM

V_P

WR

_M

ON

V_

PW

R_

MO

N

Ba

tte

ry_M

ea

sure

men

t18

INT

02

I2C

_S

DA

_P

WR

11

,15

I2C

_S

CL

_P

WR

11,

15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

132

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

PO

WE

R I

N

POP

Max

Input: 5VDC, 4 A.

Use only recommended power supplies.

R2

55

1M

1%

JP3

9H

EA

DE

R 31

23

R2

39

1 1

%

R2

56

1M 1

%R

92

47

5K 1

%

J18

Ba

tte

ry H

old

er

+1

GN

D2

SW

5A

1201

M2S

3AQ

E2

12

3

TP

23

VP

WR

_IN

R2

54 0

C5

90

.1u

F

TP

32

B+

+C6

7

22

0uF

F1

FU

SE

_3

A

12

C18

4

2.2

uF

R2

61

18

0K 1

%

U2

4IN

A2

19

IDC

N

VIN+1

VIN-2

GND 3

VS 4

SCL 5SDA 6

A0 7

A1 8

+C7

3

22

0uF

D8

LEDRED

JP22

12

L9

6.8

uH

20

%

SW

5B

1201

M2S

3AQ

E2

45

6

U26

TP

S61

030-

AD

J

EN

9

LBI

7

FB

12

SW

22

SW

11

SY

NC

8

GN

D11

PG

ND

55

PG

ND

44

PG

ND

33

LBO

10

VO

UT

1515

VO

UT

1414

VO

UT

1313

NC

16

VB

AT

6

PWR_PAD 17

J16

Pow

er

Jack

D7 SMCJ06A

TP

33

B-

C72

10u

F

TP

28

VB

AT

OU

T

R9

5

470

C1

90

0.1

uF

R9

3

18

2K 1

%

TP

31

R8

8

0

R9

10

TP

30


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VIN

_EV

M

VIN

_EV

M

VIN

_E

VM

VIN

_E

VM

TP

S6

502

3_V

CC

_1V

8

TP

S6

5023

_VC

C_

3V3

TP

S6

502

3_V

CC

_CO

RE

VR

TC

VR

TC

TP

S65

023_

LDO

_1V

3

VIN

_E

VM

TP

S65

023_

LD

O_V

LDO

2V

IN_

EV

M

VIN

_EV

M

VIN

_EV

MV

IN_E

VM

VR

TC

VIN

_E

VM

PB

_R

ES

ET

12

PW

R_R

ST

n12

I2C

_S

DA

2,5

,15

,17,

18

,19

I2C

_S

CL

2,5

,15

,17

,18

,19

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

142

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

PO

WE

R M

AN

AG

EM

EN

T

. DEFLDO2 DEFLDO1 VLDO1 VLDO2

0 0 1.3 V 3.3 V

0 1 2.8 V 3.3 V

1 0 1.3 V 1.8 V

1 1 1.8 V 3.3 V

V_CORE_SEL

OFF = 1.05V

ON = 1.30V default VOUT = VDEFDCDC * (( R85 + R257eq)/R257eq )

VDEFDCDC = 0.6

VDD_IO1_SEL

OFF = 1.8V

ON = 3.3V default

R8

3N

O-P

OP

R8

510

0K

1%

+C

64

22

uF

R8

410

0K

R7

8N

O-P

OP

+C

181

22

uF

R6

94

.7K

+C

65

10

uF

+C

183

2.2

uF

R2

500

R8

00

+C

66

10

uF

R7

6N

O-P

OP

R2

57

130

K 1

%

C60

0.0

01u

F

+C

69

10

uF

R2

451K

R3

33

R82

10K

R7

04.

7K

R7

9N

O-P

OP

C6

3N

O-P

OP

TP

26T

P-6

0

R7

210

K+

C1

88

22

uF

L82

.2u

H

R8

1N

O-P

OP

R7

51

0K

+C

18

22.

2u

F

R7

42K

R2

511

0K

R2

582

2.1

K

TP21

TP-6

0

R7

7N

O-P

OP

C6

10

.1u

F

TP

27T

P-6

0

L72.

2u

H

+C

18

92

2u

F

R7

11

0KU

25

TP

S65

023

DE

FD

CD

C3

1

VD

CD

C3

2

PG

ND

33

L34

VIN

CD

DC

35

VIN

DC

DC

16

L17

PG

ND

18

VD

CD

C1

9

DE

FC

DC

D1

10

HOT_RESETn 11

DEFLDO1 12

DEFLDO2 13

VSYSIN 14

VBACKUP 15

VRTC 16

AGND2 17

VLDO2 18

VINLDO 19

VLDO1 20

LOW

BA

Tn

21LD

O_E

N22

DC

DC

3_E

N23

DC

DC

2_E

N24

DC

DC

1_E

N25

TR

ES

PW

RO

N26

RE

SP

WR

ON

n27

INT

n28

SD

AT

29

SC

LK30

PWRFAILn31DEFDCDC232

VDCDC233PGND234

L235VINDCDC236

VCC37PWRFAIL_SNS38LOWBAT_SNS39

AGND140

PWR_PAD41

R2

52N

O-P

OP

C6

20

.1u

F

C18

50

.1u

F

R7

347

K

SW

1

RE

SE

T

143

2

TP

25T

P-6

0

1 2

ON

SW

4

DIP

_S

WIT

CH

_2

1 234

TP

20T

P-6

01

R2

59

24

3K

1%

R2

47

0L6

2.2

uH

+C

68

10

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

I2C

_S

DA

_P

WR

I2C

_S

CL

_P

WR

I2C

_S

DA

_P

WR

I2C

_S

CL

_P

WR

I2C

_SC

L_

PW

R

I2C

_S

DA

_P

WR

V3.

3

TP

S65

023

_VC

C_1

V8

TP

S65

023

_VC

C_3

V3

V1

.8

VD

D_

IO2

CP

U_

VC

C_

CO

RE

TP

S6

502

3_L

DO

_VLD

O2

TP

S65

023_

VC

C_

CO

RE

VD

D_

IO1

V1

.3

TP

S65

023

_LD

O_1

V3

V_

PW

R_M

ON

V_

PW

R_M

ON

V_

PW

R_M

ON

V_P

WR

_M

ON

V_

PW

R_M

ON

TP

S6

502

3_V

CC

_3V

3V

_P

WR

_M

ON

V_

PW

R_

MO

N

I2C

_S

DA

2,5

,14

,17

,18

,19

I2C

_S

CL

2,5,

14

,17,

18

,19

I2C

_S

DA

_P

WR

11,

13

I2C

_S

CL

_P

WR

11

,13

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

152

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

PO

WE

R R

OU

TE

R

VDD_IO1 Power Supply

VDD_IO2 Power Supply

NO-POP

NO-POP

NO-POP

Pow

er M

onito

r I2

C P

robe

Poi

nt H

eade

rs

NO-POP

C1

91

0.1

uF

JP20

12

U2

7IN

A2

19

IDC

N

VIN+1

VIN-2

GND 3

VS 4

SCL 5SDA 6

A0 7

A1 8

R2

640

R2

35

1 1

%

R2

38

0

+C

17

83

3u

F

C1

79

0.1

uF

JP2

4N

O-P

OP

POP

12

JP2

51

2

R1

33

0

R2

41

0

JP2

3

12

JP21

NO

-PO

P1

2

TP12

GN

D

R1

37

2.2

K

U2

3IN

A2

19

IDC

N

VIN+1

VIN-2

GND 3

VS 4

SCL 5SDA 6

A0 7

A1 8JP

26

12

R6

8

0

J3

HE

AD

ER

3

1 2 3

R23

70

TP

18T

est

Po

int_

1

R1

45

2.2

K

TP

17T

est

Poi

nt_

1

R2

65

1 1

%

R1

47

0


A-17

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

MM

C0_

CM

D2M

MC

0_D

AT

A2

2M

MC

0_D

AT

A3

2

MM

C0_

DA

TA

02

MM

C0_

DA

TA

12

MM

C0

_CLK

2

MM

C0.

INS

2

MM

C0

.WP

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

162

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

MM

C/S

D S

OC

KE

TS

J15 M

MC

/SD

_C

AR

D

DA

T3

1

CM

D2

VS

S1

3

VD

D4

CLK

5

VS

S2

6

DA

T0

7

DA

T1

8

DA

T2

9W

PW

P

CO

MC

O

CA

RD

_DE

TE

CT

CD

R26610K

R248NO-POP

TP

19M

MC

0.W

P

R2

90

10K

R26310K

R2

91

10K

R24210K

R26210K

R24010K

C1

86

0.1

uF

R2

93

1K

TP

22M

MC

0.I

NS

+C

18

7

10

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

RX

D

TXD

CT

S

RT

S

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

UA

RT

_RT

S2

,5

UA

RT

_RX

2,5

UA

RT

_CT

S2

,5

UA

RT

_TX

2,5

SP

I_C

LK

2,1

8

SP

I_D

X2

,18S

PI_

CS

02

,18

SP

I_R

X2

,18

I2C

_S

DA

2,5

,14

,15

,18

,19

I2C

_S

CL

2,5

,14,

15

,18,

19

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

172

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

RS

23

2(U

AR

T)/

EE

PR

OM

GND SHIELD

I2S3_CLK

I2S3_FS

I2S3_RX

I2S3_DX

256K-Bit I2C EEPROM

256K-Bit SPI EEPROM

UART_EN

R1

150

C9

5

0.1

uF

R1

25

10K

C9

2

0.1

uF

C3

0.1

uF

R1

2910

K

R1

140

R1

2810

K

R1

3010

K

R12

1

10K

R2

10K

C1

00

0.1

uF

C9

1

0.1

uF

C4

0.1

uF

JP3

POP

12

TP

24

GN

D

R5

10K

U5

MA

X32

22

T1I

N13

R2I

N9

R1I

N16

C2-

6

EN

_L1

C2+

5

NC

-114

T2O

UT

8T

1OU

T17

V-

7

NC

-211

SH

UT

DO

WN

20

V+

3

GN

D18

C1-

4C

1+2

R2O

UT

10R

1OU

T15

VC

C19

T2I

N12

U9 C

AT

25C

256K

CS

1

SO

2

WP

3

GN

D4

VC

C8

HO

LD7

SC

LK6

SIN

5C

115

0.1

uF

J1

CO

NN

EC

TO

R D

B95

94837261

1011

U6 2

4WC

256

A0

1V

CC

8

VS

S4

NC

3S

CL

6

SD

A5

A1

2W

P7


A-19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GP

AIN

AD

S_

GP

IO1

0

GP

IO1

1G

PA

IN0

GP

AIN

3G

PA

IN2

GP

AIN

1A

DS

_G

PIO

4

AD

S_

GP

IO1

AD

S_

GP

IO0

GP

IO6

GP

IO7

GP

IO9

GP

IO8

AD

S_

GP

IO3

AD

S_

GP

IO2

AD

S_

GP

IO5

VD

D_

SA

R

V1.

8V

3.3

V5

AD

S_

GP

IO0

2

SP

I_C

LK2,

17

SP

I_D

X2,

17

SP

I_C

S0

2,1

7

SP

I_R

X2,

17A

DS

_G

PIO

42

I2S

1_C

LK2

I2S

1_

FS

2

I2S

1_R

X2

INT

12

I2C

_S

DA

2,5

,14

,15,

17

,19

I2S

1_D

X2

I2C

_S

CL

2,5

,14,

15

,17

,19

XF

2

AD

S_

GP

IO1

2A

DS

_G

PIO

10

2

GP

IO1

12

AD

S_

GP

IO3

2A

DS

_G

PIO

22

AD

S_

GP

IO5

2

GP

AIN

02

GP

AIN

12

GP

AIN

22

GP

AIN

32

GP

AIN

02

Ba

tte

ry_

Me

asu

rem

ent

13

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

182

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

SA

R R

ES

IST

OR

NE

TW

OR

K

Remove R105 for

Internal Voltage

Measurement

GPAIN Battery

Measurement

LAYOUT NOTE:

These 3 connectors need to be placed

in specific coordinates to allow for Interfacing

to the ADS Codec Daughter Card

R2

46N

O-P

OP

R2

49N

O-P

OP

R2

70

4.7

5K

1%

R2

80

5.3

6K

1%

J14

HE

AD

ER

10X

2

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

SW

14D

NS

W7

UP

C1

96

0.1

uF

C19

7

NO

-PO

P

R2

72

24

.9K

1%

R2

53

0

R2

68

17

.4K

1%

SW

10R

WD

R8

9

0

SW

11P

LAY

R2

73

20

k

SW

13S

TO

PS

W8

MO

DE

R9

8

6.3

4K

1%

R99

5.4

9K

1%

TP

14

GP

IO5

R2

67

22

.6K

1%

SW

12F

WD

SW

6M

EN

U

R27

1

6.4

9K

1%

R2

60N

O-P

OP

R2

43N

O-P

OP

SW

15R

EC

SW

9S

hift

TP

29

GN

D

J13

HE

AD

ER

11

x2

2 4 6 8 10 12

1 3 5 7 9 1114

13 1516

1718 20

19 2122

R2

69

60

.4K

1%

J10

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AIC

_LI

NE

3L

AIC

_L

INE

3R

AIC

_LI

NE

2L

HE

AD

PH

ON

E_

RO

UT

AIC

_L

INE

2R

AIC

_M

BIA

S

HE

AD

PH

ON

E_L

OU

T

AIC

32

54_

RO

UTAIC

_M

IC1

LA

IC_

MIC

1R

MIC

1_

IN

MIC

2_

IN

CO

NN

_H

P_

LO

UT

AIC

_II

SC

LK

AIC

_II

SF

SA

IC_

IIS

D0

AIC

_II

SD

1 AIC

_M

ISO

AIC

_M

OS

IA

IC_

SP

I_S

EL

MIC

_DE

T

AIC

_S

CL

K

MIC

_D

ET

AIC

_R

ST

CO

NN

_H

P_

RO

UT

AIC

325

4_L

OU

T

GN

D-A

GN

D-A

GN

D-A

GN

D-A

GN

D-A

GN

D-A

GN

D-A

GN

D-A

GN

D-A

V3.

3A

V3

.3

GN

D-A

V3

.3A

VD

D_

IO1

GN

D-A

GN

D-A

VD

D_

IO1

GN

D-A

V3

.3A

VD

D_I

O1

GN

D-A

V1

.8

AU

DIO

_M

CLK

3

I2S

2_

CL

K2

I2S

2_F

S2

AIC

_RS

T2

nRE

SE

T2

,12

,20

I2S

2_D

X2

I2S

2_R

X2

I2C

_S

DA

2,5

,14,

15

,17

,18

I2C

_SC

L2

,5,1

4,1

5,1

7,1

8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01

, 2

01

019

20

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

CO

DE

C

Tie

Ana

log

Po

we

r to

Dig

ital P

ower

thro

ugh

sin

gle

po

int

con

nec

tion

or

Fer

rite

Bea

d.

STEREO IN 1

STEREO OUT

HEADPHONES OUT

Route all mic lines away from digital signals!

STEREO IN 2

Remove if not

using with I2C

LEFT MIC

RIGHT MIC

0 = LDO_OFF

1 = LDO_ON

+

C5

22

0uF

J7

SJ1

-35

15-S

MT

, 5P

JAC

K S

TE

RE

O2 3 14 5

8

9

+M

21 2

FB

11 BL

M21

AG

151

SN

1D

12

R1

701

00

R1

86

2.2

KC

108

0.1

uF

C12

1.0

47

uF

C1

56.0

47u

F

R1

690

JP4

0 PW

RJPNO

-PO

P1

2

C4

4

10

uF

C1

451

uF

R1

610

JP7 P

WR

JPNO

-PO

P1

2

C1

640

.47

uF

J4

SJ1

-35

15-S

MT

, 5P

JAC

K S

TE

RE

O2 3 14 5

8

9

R29

20

C1

7

22

uF

C3

70

.1u

F

R1

971

00

J12

SJ1

-35

15-S

MT

, 5P

JAC

K S

TE

RE

O2 3 14 5

8

9

R18

7

2.2

K

FB

12 B

LM

21A

G15

1S

N1D

12

R2

09

NO

-PO

P

C3

80

.1u

F

R1

35

4.7

K

R1

41N

O-P

OP

C1

680

.47

uF

R14

04

.7K

C1

760

.47

uF

R1

770

JP14

PW

RJP

NO

-PO

P1

2

U1

2

TL

V3

20A

IC3

204I

RH

BT

BC

LK2

WC

LK3

DIN

4

IOVSS 7

IN1_

L13

IN1_

R14

IN2_

L15

IN2_

R16

IN3_

L20

MIC

BIA

S19

IN3_

R21

HPVDD26

HP

L25

DVSS 28

LOR

23

AVDD24

RE

SE

T31

MC

LK1

DO

UT

5

IOVDD6

SC

L/S

SZ

9

SD

A/M

OS

I10

AVSS 17

LOL

22H

PR

27

DVDD29 SC

LK/M

IC_D

ET

8M

ISO

11S

PI_

SE

L12

RE

F18

LDO

_SE

L30

GP

IO32

PPAD 33

J9

SJ1

-35

15-S

MT

, 5P

JAC

K S

TE

RE

O2 3 14 5

8

9

C1

07

0.1

uF

R1

44N

O-P

OP

JP1

2

MIC

_B

IAS

123

R1

730

C3

0

10

uF

C3

2

10

uF

FB

4

BL

M21

AG

151

SN

1D1

2

TP5 AIC_GPIO

C1

8

22

uF

R1

920

J5

HD

R4

1234

C1

141

uF

R18

8

0

+

C1

22

0uF

C2

5

22

uF

R1

36N

O-P

OP

R1

800

C1

17

0.1

uF

C1

28

0.1

uF

C1

26

0.1

uF

R1

650

FB

1

BL

M21

AG

151

SN

1D1

2

TP

15

GN

D

R1

39

0

+M

11 2

C1

800

.47

uF


A-21

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LC

D_

DA

TA

2L

CD

_D

AT

A3

LC

D_

DA

TA

0L

CD

_D

AT

A1

LC

D_

DA

TA

4L

CD

_D

AT

A5

LC

D_

DA

TA

6L

CD

_D

AT

A7

VD

D_

IO1

VD

D_

IO1

VD

D_

IO1

V13

V1

3V

3.3

nR

ES

ET

2,1

2,1

9

LC

D_

RE

2

LCD

_B

IAS

_OE

2L

CD

_A

LE

2

LC

D_

nW

E2

GP

IO1

1_L

CD

_PW

R2

LC

D_

DA

TA

72

LC

D_

DA

TA

62

LC

D_

DA

TA

52

LC

D_

DA

TA

42

LC

D_

DA

TA

32

LC

D_

DA

TA

22

LC

D_

DA

TA

12

LC

D_

DA

TA

02

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5127

02-0

001

Mo

nd

ay,

Fe

bru

ary

01,

20

10

202

0

B

TM

S3

20C

551

5 E

VA

LU

AT

ION

MO

DU

LE

CO

LO

R L

CD

IN

TE

RF

AC

E

This board uses a mirrored footprint for J19

LCD POWER 13V

0SD-2828GDEDF11

J19

OE

L D

isp

lay

Mo

du

le

NC

-1(

GN

D )

1

VC

C2

VC

OM

H3

VD

DIO

4

VS

L5

NC

-66

D6

8D

77

D5

9

D4

10

D3

11

D2

12

D1

13

D0

14

E/R

Dn

15

R/W

n16

BS

017

BS

118

CS

n19

D/C

n20

RE

SE

Tn

21

IRE

F22

GP

IO1

23

GP

IO0

24

NC

-25

25

VD

D26

VC

I27

VS

S28

NC

-29

29

NC

-30(

GN

D )

30

Z4

1

C2

05

4.7

uF

R2

77

0

C2

02

4.7

uF

,16

V

R2

74

NO

-PO

P

L10

2.2

uH

C2

01

10

uF

R9

4

10K

Z3

1

C1

92

10

pF

D6

MB

R05

20

R2

780

Z2

1

C1

93

1u

F

R9

7

180K

C2

00

10u

F

R2

7550

C1

941

0u

F,1

6V

U2

8

TP

S61

041

SW

1

GN

D2

FB

3E

N4

Vin

5

Z1

1

R2

810

C1

98

NO

-PO

P

C7

4

10

uF

,16

V

C1

951

0u

F

R2

79N

O-P

OP

R2

76

560

K 1

%

D15

MM

BD

4148

13

2

C7

1

10u

F

C2

03

1u

F

R9

6

1.6

M 1

%

C1

99

NO

-PO

P

D1

4M

MB

D41

48

13

2

C2

04

NO

-PO

P



B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about theTMS320C5515 EVM produced by Spectrum Digital.


B-2 TMS320C5515 EVM Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE

Printed in U.S.A., February 2010512705-0001 Rev. A