Topic 2_Logic Gates

8/12/2019 Topic 2_Logic Gates

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FLB 23043DIGITAL SYSTEMS Introduction to Logic Gates 1

Topic 2:

Logic Gates


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Logic Gates The Inverter

The AND Gate

The OR Gate

The NAND Gate The NOR Gate

The XOR Gate

The XNOR Gate

Drawing Logic Circuit

Analysing Logic Circuit

Propagation Delay


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Universal Gates: NAND and NOR

NAND Gate

NOR Gate

Implementation using NAND Gates

Implementation using NOR Gates

Implementation of SOP Expressions

Implementation of POS Expressions

Positive and Negative Logic

Integrated Circuit Logic Families


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Logic Gates

Gate Symbols

EXCLUSIVE OR

a

ba.b

a

b a+b

a a'

a

b(a+b)'

a

b(a.b)'

a

ba b

a

ba.b&

a

b a+b1

AND

a a'1

a

b(a.b)'&

a

b(a+b)'1

a

ba b=1

OR

NOT

NAND

NOR

Symbol set 1 Symbol set 2

(ANSI/IEEE Standard 91-1984)


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Logic Gates: The Inverter

The InverterA A'

0 1

1 0

A A' A A'

Application of the inverter: complement.

1

0

0

1

0

1

0

1

1

0

0

1

1

0

1

0

Binary number

1s Complement


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Logic Gates: The AND Gate

The AND Gate

A B A . B

0 0 0

0 1 0

1 0 01 1 1

A

BA.B

&A

BA.B


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Logic Gates: The AND Gate

Application of the AND Gate

1 sec

A

1 sec

Enable

A

EnableCounter

Reset to zero

betweenEnable pulses

Register,

decode

andfrequency

display


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Logic Gates: The OR Gate

The OR Gate

1AB

A+BA

BA+B

A B A + B

0 0 0

0 1 1

1 0 11 1 1


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Logic Gates: The NAND Gate

The NAND Gate

&A

B(A.B)'

A

B(A.B)'

A

B(A.B)'

NAND Negative-OR

A B (A.B)'

0 0 1

0 1 1

1 0 11 1 0


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Logic Gates: The NOR Gate

The NOR Gate

NOR Negative-AND

1A

B(A+B)'

A

B(A+B)'

A

B(A+B)'

A B (A+B)'

0 0 1

0 1 0

1 0 01 1 0


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Logic Gates: The XOR Gate

The XOR Gate

=1A

BA B

A

BA B

A B A B

0 0 0

0 1 1

1 0 11 1 0


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Logic Gates: The XNOR Gate

The XNOR Gate

A

B(A B)'

=1A

B(A B)'

A B (A B)'

0 0 1

0 1 0

1 0 01 1 1


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When a Boolean expression is provided, we can easily draw

the logic circuit.

Examples:

(i) F1 = xyz' (note the use of a 3-input AND gate)

xy

z

F1

z'


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(ii) F2 = x + y'z (can assume that variables and their

complements are available)

(iii) F3 = xy' + x'z

x

y'z

F2

y'z

x'z

F3

x'z

xy'x

y'


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Analysing Logic Circuit

When a logic circuit is provided, we can analyse the circuit to

obtain the logic expression.

Example: What is the Boolean expression of F4?

A'B'

A'B'+C (A'B'+C)'

A'

B'

CF4

F4 = (A'B'+C)' = (A+B).C'


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Propagation Delay

Every logic gate experiences some delay (though very small)in propagating signals forward.

This delay is called Gate (Propagation) Delay.

Formally, it is the average transition time taken for the output

signal of the gate to change in response to changes in theinput signals.

Three different propagation delay times associated with a

logic gate:

tPHL

: output changing from the High level to Low level

tPLH: output changing from the Low level to High level

tPD=(tPLH + tPHL)/2 (average propagation delay)


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Propagation Delay

Input Output

Output

Input

H

L

L

H

tPHL tPLH


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Propagation Delay

A B C

Ideally, no

delay:

1

0

1

0

0

1

time

Signal for C

Signal for B

Signal for A

In reality, output signals

normally lag behind input

signals:1

0

1

0

0

1

time

Signal for C

Signal for B

Signal for A


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Calculation of Circuit Delays

Amount of propagation delay per gate depends on: (i) gate type (AND, OR, NOT, etc)

(ii) transistor technology used (TTL,ECL,CMOS etc),

(iii) miniaturisation (SSI, MSI, LSI, VLSI)

To simplify matters, one can assume (i) an average delay time per gate, or

(ii) an average delay time per gate-type.

Propagation delay of logic circuit

= longest time it takes for the input signal(s) to propagate to the

output(s).

= earliest time for output signal(s) to stabilise, given that input

signals are stable at time 0.


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In general, given a logic gate with delay, t.

If inputs are stable at times t1,t2,..,tn, respectively; then the

earliest time in which the output will be stable is:

max(t1, t2, .., tn) + t

Logic

Gate

t1t2

tn

: :

max (t1, t2, ..., tn ) + t

To calculate the delays of all outputs of a combinational

circuit, repeat above rule for all gates.


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As a simple example, consider the full adder circuit where allinputs are available at time 0. (Assume each gate has delay t.)

where outputs S and C, experience delays

of 2t and 3t, respectively.

X

Y S

C

Z

max(0,0)+t = t

t

0

0

0

max(t,0)+t = 2t

max(t,2t)+t = 3t2t


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Universal Gates: NAND and NOR

AND/OR/NOT gates are sufficient for building any Booleanfunctions.

We call the set {AND, OR, NOT} a complete set of logic.

However, other gates are also used because:

(i) usefulness(ii) economical on transistors

(iii) self-sufficient

NAND/NOR: economical, self-sufficient

XOR: useful (e.g. parity bit generation)


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NAND Gate

NAND gate is self-sufficient (can build any logic circuit withit).

Therefore, {NAND} is also a complete set of logic.

Can be used to implement AND/OR/NOT.

Implementing an inverter using NAND gate:

(x.x)' = x' (T1: idempotency)

x x'


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NAND Gate

((xy)'(xy)')' = ((xy)')' idempotency

= (xy) involution

((xx)'(yy)')' = (x'y')' idempotency

= x''+y'' DeMorgan= x+y involution

Implementing AND using NAND gates:

Implementing OR using NAND gates:

xx.y

y

(x.y)'

x

x+y

y

x'

y'


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NOR Gate

NOR gate is also self-sufficient.

Therefore, {NOR} is also a complete set of logic

Can be used to implement AND/OR/NOT.

Implementing an inverter using NOR gate:

(x+x)' = x' (T1: idempotency)

x x'


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FLB 20203

DIGITAL SYSTEMS Introduction to Logic Gates 26

NOR Gate

((x+x)'+(y+y)')'=(x'+y')' idempotency= x''.y'' DeMorgan

= x.y involution

((x+y)'+(x+y)')' = ((x+y)')' idempotency

= (x+y) involution

Implementing AND using NOR gates:

Implementing OR using NOR gates:

x x+yy

(x+y)'

x

x.y

y

x'

y'


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Implementation using NAND gates

Possible to implement any Boolean expression using NAND

gates.

Procedure:

(i) Obtain sum-of-products Boolean expression:

e.g. F3 = xy'+x'z

(ii) Use DeMorgan theorem to obtain expression

using 2-level NAND gates

e.g. F3 = xy'+x'z

= (xy'+x'z)' ' involution= ((xy')' . (x'z)')' DeMorgan


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Implementation using NAND gates

F3 = ((xy')'.(x'z)') ' = xy' + x'z

x'

z

F3

(x'z)'

(xy')'x

y'


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Implementation using NOR gates

Possible to implement any Boolean expression using NOR

gates.

Procedure:

(i) Obtain product-of-sums Boolean expression:

e.g. F6 = (x+y').(x'+z)

(ii) Use DeMorgan theorem to obtain expression

using 2-level NOR gates.

e.g. F6 = (x+y').(x'+z)

= ((x+y').(x'+z))' ' involution= ((x+y')'+(x'+z)')' DeMorgan


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Implementation using NOR gates

F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)

x'

z

F6

(x'+z)'

(x+y')'x

y'


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Sum-of-Products expressions can be implemented using:

2-level AND-OR logic circuits

2-level NAND logic circuits

AND-OR logic circuit

F = AB + CD + E

F

A

B

D

C

E Two or more product terms are

summed by boolean addition


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NAND-NAND circuit (by circuittransformation)

a) add double bubbles

b) change OR-with-

inverted-inputs to NAND& bubbles at inputs to

their complements

F

A

B

D

C

E

A

B

D

C

E'

F


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Product-of-Sums expressions can be implemented using:

2-level OR-AND logic circuits

2-level NOR logic circuits

OR-AND logic circuit

G = (A+B).(C+D).E

G

A

B

DC

E


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NOR-NOR circuit (by circuit

transformation):

a) add double bubbles

b) changed AND-with-

inverted-inputs to NOR& bubbles at inputs to

their complements

G

A

B

D

C

E

A

B

DC

E'

G


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Positive & Negative Logic

In logic gates, usually:

H (high voltage, 5V) = 1

L (low voltage, 0V) = 0

This convention positive logic.

However, the reverse convention, negative logic possible:

H (high voltage) = 0

L (low voltage) = 1

Depending on convention, same gate may denote different

Boolean function.


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A signal that is set to logic 1 is said to be asserted, or active,

ortrue.

A signal that is set to logic 0 is said to be deasserted, or

negated, or false.

Active-high signal names are usually written in

uncomplemented form.

Active-low signal names are usually written in complemented

form.


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Positive logic:

Negative logic:

Enable

Active High:

0: Disabled

1: Enabled

Enable

Active Low:

0: Enabled1: Disabled


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Some digital integrated circuit families: TTL, CMOS, ECL.

TTL: Transistor-Transistor Logic.

Uses bipolar junction transistors

Consists of a series of logic circuits: standard TTL, low-powerTTL, Schottky TTL, low-power Schottky TTL, advanced

Schottky TTL, etc.


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CMOS: Complementary Metal-Oxide Semiconductor.

Uses field-effect transistors

ECL: Emitter Coupled Logic.

Uses bipolar circuit technology.

Has fastest switching speed but high power consumption.


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Performance characteristics

Propagation delay time.

Power dissipation.

Fan-out: Fan-out of a gate is the maximum number of inputsthat the gate can drive.

Speed-power product (SPP): product of the propagation

delay time and the power dissipation.


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SummaryLogic Gates

AND,

OR,

NOT

NAND

NOR

Drawing Logic

Circuit

Analysing

Logic Circuit

Given a Boolean

expression, draw the

circuit.

Given a circuit, find

the function.

Implementation of a

Boolean expression

using these

Universal gates.

Implementation

of SOP and POS

Expressions

Positive and

Negative Logic

Concept of Minterm

and Maxterm

End of file

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Topic 2_Logic Gates