Upload
brett-wildermoth
View
229
Download
0
Embed Size (px)
Citation preview
7/29/2019 Topic06 Introduction to Memory
1/78
Memory: Types and how to use them... 6
1Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
2/78
MemoryThe Black Box
All memory devices are attached to the data,address and control buses of themicroprocessor.
MemoryDevice
Address
2Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
3/78
MemoryThe Black Box : The Control Bus
The control bus defines how the memory device should communicate with theuP.
The Control Bus handles things like:
The direction of the Data Bus; are we reading from the memory device or
writing to it. The speed of communication; an external clock is part of the control bus.
Interrupt handling; any interrupt sources from the device are part of this bus.
MemoryDevice
Address
3Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
4/78
MemoryThe Black Box : The Address Bus
The address bus provides the address of the memory location that the uP wantsto access. The bus is unidirectional.
The width of the address bus defines the total amount of addressable memory.
If a uP has 16 address pins then it is capable of addressing 65536 unique memory
locations. If a memory device has only 3 address pins then it must contain 8 addressable
memory words.
MemoryDevice
Address
4Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
5/78
MemoryThe Black Box : The Data Bus
The Data Bus is responsible for moving the data between the uP and the memorydevice.
The Data Bus is bidirectional; when writing data to the memory device the dataflows from the uP to the memory device. When reading data from the device it
flows towards the uP. The width of the uPs data bus defines the word length of the uP. The
MC9S12XDP512 has a 16 bit internal data bus, therefore it is a 16 bit processor.
MemoryDevice
Address
5Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
6/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
6Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
7/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
7Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
8/78
MemoryThe Black Box : How it all works
MemoryDevice
AddressLDAA $2000
7Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
9/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
7Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
10/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
8Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
11/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
8Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
12/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
8Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
13/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
8Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
14/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
9Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
15/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
9Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
16/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
9Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
17/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
9Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
18/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
10Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
19/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
10Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
20/78
MemoryThe Black Box : How it all works
Address
Memory
Decoder
MemoryElements
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
21/78
MemoryThe Black Box : How it all works
Address$2000Memory
Decoder
MemoryElements
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
22/78
MemoryThe Black Box : How it all works
Address
Memory
Decoder
MemoryElements
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
23/78
MemoryThe Black Box : How it all works
Address
Memory
Decoder
MemoryElements
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
24/78
MemoryThe Black Box : How it all works
Address
Memory
Decoder
MemoryElements
Position8192 ($2000)
$45
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
25/78
MemoryThe Black Box : How it all works
Address
Memory
Decoder
MemoryElements
$45
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
26/78
MemoryThe Black Box : How it all works
Address
Read
Memory
Decoder
MemoryElements
$45
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
27/78
MemoryThe Black Box : How it all works
Address
Read
Memory
Decoder
MemoryElements
$45
11Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
28/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
Read
12Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
29/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
Read
$45
12Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
30/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
Read
$45
12Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
31/78
MemoryThe Black Box : How it all works
MemoryDevice
Address
Read
$45
12Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
32/78
MemoryThe Black Box : Summary
The address of the location is placed on the address bus, the control linethen defines either a read or write cycle. During a write cycle the data isalso made available on the data bus at this time.
When the device receives the R/W signal it latches the address internally.
This address is then used to drive an internal memory decoder whichactivates a particular row of memory elements. The row of memoryelements is then connected to the data bus.
During a read cycle, the data in the row of elements is driven on to thedata bus and read by the uP. During a write cycle, the data bus is driven on
to the memory elements. The memory transaction is then complete.
13Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
33/78
MemoryTypes
All memory is categorized into two maintypes: ROM
RAM
14Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
34/78
ROMRead-Only Memory
Commonly referred to as Read-Only Memory, orNon-Volatile RAM (NVRAM).
This type of memory can only be read.
Generally programs and constants are stored in
ROM, once they are written they very rarelychange, and they never change while programsare running.
ROMMemoryDevice
Address
Read Enable
ClockNo R/W line just
a RE line instead.
15Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
35/78
ROMRead-Only Memory
There exists two major reason why ROM memory is used insteadof RAM:
Values stored in ROM always remain stored under all possiblepower conditions. The ROM chip can be removed from thesystem and stored elsewhere and the contents will remain intact.Like Hard Drives, ROM is considered to be non volatile memory.
The second reason is security, since the ROM can only be readfrom, the contents of the ROM can not be altered through
malicious or accidental use.
16Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
36/78
ROMRead-Only Memory: How it Works
Inside a basic 1k ROM.
17Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
37/78
Memory Elements
Memory Elements are configured as a 2D structure. The number of columns equals the width of the data
bus and the number of rows equals 2width of address bus.
Memory
Decoder
A0
A1
D7 D0
18Wednesday, 8 July 2009
ROM
7/29/2019 Topic06 Introduction to Memory
38/78
ROMHistorically
Originally ROM referred tomemory that could only bewritten to once.
It was constructed fromhardwired logic, encoded into thesilicon itself.
Bit values were manually wiredinto the memory elements via ametallization layer.
This type of memory was highlyinflexible and extremelyexpensive.
Memory Element of a ROM
19Wednesday, 8 July 2009
ROMS
7/29/2019 Topic06 Introduction to Memory
39/78
ROMSThe Pros
Nonvolatile: if power is lost the contentsremain unchanged. When a device is powered ON it needs a
program to run...
20Wednesday, 8 July 2009
ROMS
7/29/2019 Topic06 Introduction to Memory
40/78
ROMSThe Cons
Extremely inflexible If a mistake is made then the 1000+ devices
built are landfill...
21Wednesday, 8 July 2009
ROM
7/29/2019 Topic06 Introduction to Memory
41/78
ROMThe Good News
Not all ROMs are made equal. There are variantsthat provide some level of flexibility.
These variants include: PROM EPROM EEPROM Flash EPROM
22Wednesday, 8 July 2009
PROM
7/29/2019 Topic06 Introduction to Memory
42/78
PROMProgrammable Read-Only Memory
This type of memory has the
ability to be programmed onlyonce.
Programming of these devicesis achieved using PROM
Programmer.
The Pocket Programmer
PROM/EPROM Programmer.
23Wednesday, 8 July 2009
PROM
7/29/2019 Topic06 Introduction to Memory
43/78
PROMProgrammable Read-Only Memory
PROM is suitable for ROM applications where a
small number of inflexible ROM are required. In situations were programs are upgraded the
PROM would simply be replaced with onecontaining a newer version of the code.
Expensive and required a technician to do it.
24Wednesday, 8 July 2009
PROM
7/29/2019 Topic06 Introduction to Memory
44/78
PROMMemory Element
The PROM programmer applies enough current to blow the fuses for allmemory elements that should contain a logical 1 value.
25Wednesday, 8 July 2009
EPROM
7/29/2019 Topic06 Introduction to Memory
45/78
EPROMErasable Programmable Read Only Memory
EPROM allows slightly more flexibility thanPROM.
EPROM is a ROM device that can beprogrammed using a PROM programmer.
It however can be erased using ultraviolet light.
A little quartz window is installed on the top ofthe ROM package, through which you canactually see the silicon chip that contains thedata.
26Wednesday, 8 July 2009
EPROM
7/29/2019 Topic06 Introduction to Memory
46/78
EPROMErasable Programmable Read Only Memory
27Wednesday, 8 July 2009
EPROM
7/29/2019 Topic06 Introduction to Memory
47/78
EPROMErasable Programmable Read Only Memory
The window on the top of the chip is made of quartz as ultraviolet light will notpass through glass.
The ultraviolet light discharges all of the memory elements on the chip, allowingthem to be reprogrammed.
In a UV eraser it usually takes around 30 minutes to erase an EPROM.
If the chip is left unprotected outside in the sun, it would take 3 weeks ofsunshine to erase the chip, if left unprotected under florescent lights it would takea year to be erased.
28Wednesday, 8 July 2009
EPROM
7/29/2019 Topic06 Introduction to Memory
48/78
Memory Elements
The EPROM Transistor plays a significant role inthe EPROM memory element. When the floatinggate is uncharged the transistor functions
normally.29Wednesday, 8 July 2009
EPROM
7/29/2019 Topic06 Introduction to Memory
49/78
EPROMMemory Elements
The EPROM Memory
Element30Wednesday, 8 July 2009
EEPROM (E2PROM)
7/29/2019 Topic06 Introduction to Memory
50/78
EEPROM (E2PROM)Electrically Erasable Programmable Read Only Memory
The next level of flexibility is EEPROM.
EEPROM is considered to be the most flexible type of ROM, thecontents of the ROM can be erased and reprogrammed on the fly,while situated inside the final product.
The EEPRROM can in fact be used as if it were RAM, however theaccess time for a write cycle is extremely slow.
An EEPROM device has a limited number of times it can be written
to, which is generally in the order of thousands.
31Wednesday, 8 July 2009
EEPROM
7/29/2019 Topic06 Introduction to Memory
51/78
EEPROMMemory Elements
The EEPROM Cell contains a EEPROM Transistor, thistransistor also has a floating gate. Once charged thistransistor will always show a logical 1 until
discharged.32Wednesday, 8 July 2009
FLASH
7/29/2019 Topic06 Introduction to Memory
52/78
FLASH
Flash memories have grown to be very popularand many microcontrollers contain Flash memory
on-chip. The MC9S12XDP512 includes 512k of Flash
memory.
Flash has a number of built-in write protection
mechanisms. Flash programming voltage
Programming Algorithm
33Wednesday, 8 July 2009
FLASH
7/29/2019 Topic06 Introduction to Memory
53/78
FLASHMemory Elements
The FLASH memoryElement.
34Wednesday, 8 July 2009
RAM
7/29/2019 Topic06 Introduction to Memory
54/78
RAMRandom Access Memory
RAM is primarily used for the storage of programdata.
RAM is extremely volatile.
Any fluctuation in power will result in all memoryelements being corrupted or erased.
Data can be easily written and read from RAM,
quickly and efficiently due to the nature in whichit stores information.
35Wednesday, 8 July 2009
RAM
7/29/2019 Topic06 Introduction to Memory
55/78
RAM Like all other memory devices, the RAM chip connects to the data,
address and control buses.
Externally, the RAM chip differs from the ROM chip as it contains anadditional control line to allow data to be written to the RAM chip.This additional line is the write line.
However internally there are many differences between RAM andROM.
RAMMemoryDevice
Address
Read/Write
Clock
RE
WE
36Wednesday, 8 July 2009
RAM
7/29/2019 Topic06 Introduction to Memory
56/78
RAMRandom Access Memory
Inside a basic 1k RAM.
37Wednesday, 8 July 2009
RAM
7/29/2019 Topic06 Introduction to Memory
57/78
RAMRandom Access Memory
There are currently two major types of RAM,these are: SRAM, And DRAM.
38Wednesday, 8 July 2009
SRAM
7/29/2019 Topic06 Introduction to Memory
58/78
SRAM
SRAM has extremely low latency. It is the fastest memory technology that is
currently available. The Cache of CPUs consist of
SRAM memory. The basic SRAM memory element is made up of
6 transistors. An SRAM memory element occupies a lot of
space on the silicon wafer. SRAM is expensive and is generally only available
in small quantities.
39Wednesday, 8 July 2009
SRAM
7/29/2019 Topic06 Introduction to Memory
59/78
SRAMMemory Element
An SRAM Memory Element.
40Wednesday, 8 July 2009
DRAM
7/29/2019 Topic06 Introduction to Memory
60/78
DRAMDynamic Random Access Memory
DRAM is a type of RAM capable of holding dataas long as each memory element is continuallywritten to.
A special logic circuit referred to as the refreshcircuit, reads each column of the 2D memorystructure and writes the values back.
The refresh circuit performs this task over ahundred times a second.
If the memory elements are not refreshed atregular intervals then the data contained insidethe DRAM memory element will be lost.
41Wednesday, 8 July 2009
DRAM
7/29/2019 Topic06 Introduction to Memory
61/78
DRAMDynamic Random Access Memory
Due to the overhead of refreshing each element, DRAM isgenerally a lot slower than SRAM.
However, DRAM has the advantage of occupying of the spaceon an IC than SRAM and is therefore cheaper.
The overhead of the refresh circuit is tolerated in order to allowthe use of larger capacity and yet less expensive memory.
42Wednesday, 8 July 2009
DRAM
7/29/2019 Topic06 Introduction to Memory
62/78
DRAMDynamic Random Access Memory
A DRAM memory element consists of only onetransistor and a capacitor.
When the capacitor is charged it holds the bitvalue is 1 and if it is discharged it holds the bitvalue is 0.
The transistor is used to read the value held bythe capacitor.
The problem with capacitors is that they holdtheir charge for only a limited time and thenfades. These capacitors are very small so theircharges fade particularly quickly.
43Wednesday, 8 July 2009
DRAM
7/29/2019 Topic06 Introduction to Memory
63/78
Memory Element
A DRAM Memory Element.
44Wednesday, 8 July 2009
DRAM Versus SRAM
7/29/2019 Topic06 Introduction to Memory
64/78
The Pros and Cons
The use of SRAM has two major advantages over DRAM:
SRAM does not require an external refresh making it easier toimplement than DRAM.
Access times for SRAM are much lower than DRAM. SRAM cangive access times as low as 10 nanoseconds, as opposed to theaverage 60 nanoseconds of DRAM. The cycle time of SRAM ismuch shorter as the memory does not need to be refreshedbetween memory reads and writes.
The use of SRAM has two major disadvantages over DRAM:
SRAM is much more expensive than DRAM
SRAM occupies more area on a silicon wafer than DRAM.
45Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
65/78
Interfacing to Memory
Interfacing a uP to memory can be either adifficult or a simple task, depending on whetheryou do your homework first or not.
In a uP based system, the uP is the master. TheuP defines when the memory device is accessedand when data is made available to, or read fromthe data bus.
So the memory device you choose must tomeet the timing requirements of the uP.
46Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
66/78
When connecting a memory device to a uP youneed to do the following: Connect the external clock from the uP to
the memory devices clock pin.
Connect the R/W pin of the uP to thememory device's R/W or RE pin.
MemoryDevice
CLKRE
EClkR/W
47Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
67/78
Interfacing to Memory
Connect the Data Bus of the uP to the Data Bus ofthe memory device ensuring the bits align properly.
If the data buses differ in size then align the smaller
bus to the least significant bits of the larger bus.
MemoryDevice
D7D6
D5D4D3D2D1D0
D7D6
D5D4D3D2D1D0
48Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
68/78
Interfacing to Memory
Connect the address bus of the memorydevice to the least significant end of theuPs address bus.
MemoryDevice
A2A1A0
A5A4A3
A2A1A0
49Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
69/78
Interfacing to Memory
If this uP with a 6 bit address bus is connectedto the memory device that only has a 3 bitaddress input.
What does it do to the memor s ace?
Memory
DeviceA2A1A0
A5
A4A3A2A1A0
50Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
70/78
Interfacing to Memory
Since only the bottom 3 bits of the address bus areused and the top 3 are ignored, that means the eightmemory location on the device are:
XXX000 - XXX111
Therefore the address 000001 refers to samelocation as 111001.
MemoryDevice
A2A1A0
A5A4A3A2A1A0
51Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
71/78
Interfacing to Memory
So the memory space would look somethinglike this.
$00
$3F
MD
MDMD
MD
MD
MDMD
MD
The memory Devicerepeats every 8 bytes.
MemoryMap
52Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
72/78
Interfacing to Memory
So how could we stop the device from repeating?
How could we ensure it only occupied 8 bytes in ourmemory space?
What role could the 3 most significant bits of theaddress bus play?
MemoryDevice
A2A1A0
A5A4A3A2A1A0
CE
53Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
73/78
g y
So how could we stop the device from repeating?
How could we ensure it only occupied 8 bytes in ourmemory space?
What role could the 3 most significant bits of theaddress bus play?
MemoryDevice
A2A1A0
A5A4A3A2A1A0
& CE
53Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
74/78
g y
Now when the 3 most significant bits of the addressbus are all high the memory device is enabled.
The CE pin of the memory device is a chip enable
pin, its kind of like an ON/OFF switch.
MemoryDevice
A2A1A0
A5A4A3A2A1A0
& CE
54Wednesday, 8 July 2009
Interfacing to Memory
7/29/2019 Topic06 Introduction to Memory
75/78
g y
The Memory Device is now only available in therange 111000 to 111111.
$00
$3FMD
MemoryMap
$38
55Wednesday, 8 July 2009
7/29/2019 Topic06 Introduction to Memory
76/78
MC9S12XDP512Memory Map
7/29/2019 Topic06 Introduction to Memory
77/78
57Wednesday, 8 July 2009
Need FurtherAssistance?
7/29/2019 Topic06 Introduction to Memory
78/78
Assistance?
Ask your Demonstrator,
Post a question on the Forum, Email the Convener, or
Make an appointment.
58Wednesday, 8 July 2009