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Toshit RalhanEMail: [email protected]
09868619819
Experience Summary
About 1.4 years of experience in FPGA. Implementation of
algorithms using
HDL. Simulation, Synthesis and bitstream generation of VHDL
code
Hands on experience on implementation of various Encryption
& Decryption
Algorithms using VHDL/VERILOG
Knowledge of Entire FPGA design flow. Implementation of Design
on FPGA. Device Driver code forSLIC, UART , Flash Memory using VHDL
platform.
Testing of Board VHDL code for design Simulation and
Synthesis.
Bit stream Generation. Projects on Telecommunication Interested
in Digital Signal Processing
Knowledge of RS-232, SPI protocol
PRESENT STATUS:-
Presently working at Paramahansa Systems And Softwares, New
Delhi as a Design
Engineer in R. & D. department from May 2008.
Project Experience Skills
Tools/ Software Libero 7.2 , 8.3 from Actel , MODEL SIMMultisim
, Tina-Pro and Electronic Workbench, ORCAD, ISE
Webpack7.1 (Xilinx).Operating Systems : WindowsHDL : VHDL,
VERILOG
Educational Qualification
1> Advanced postgraduate diploma in VLSI technology from
SCL(Semiconductor
Laboratory ) Chandigarh under deptt of SPACE govt of India.
This include ckt design using verilog ,VHDL,Xilinx, ,STA,
Digital design both at
frontend & backend level,CMOS ckt design
Percentage: 81%
2 > Bachelor of Technology in Electronics and
Telecommunication (U.P TechUniversity).
Percentage: 68%
College: College Of Engineering Roorkee(U.P Tech University)Year
of passing:2007
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Toshit RalhanEMail: [email protected]
09868619819
Project Details
Encryption and Decryption in Telemobile system
Brief description:
Telemobile is interfaced to our board . The modem and mux are
externally connected to
the board .The board receives the data perform the encryption or
decryption as demandedby the user .The encryption or decryption is
done by the 521 bit key and using an
complex algorithm .This board has live on power up feature by
use of flash memory for
storing the 521bit key and various states of the system on
flashSoftware Platform / ToolsVHDL & Libero 7.2 , 8.3 from
Actel
Role & Contribution Development of drivers for flash memory
in VHDL.
Interfacing of the flash memory with SRAM on ACTEL FPGA
This whole module is interfaced with the parent code and
successfully checked forvarious flaws
Simulation, Synthesis and bitstream generation of VHDL code is
done..
Encryption and Decryption in Telephone system
Brief description:
Telephone is interfaced to our board by a SLIC (Subscriber Line
Interface Circuit) .SLIC willsimulate as an Exchange for the
Telephone.While; Modem is connected to telephone line comingfrom
Exchange.
Before encryption, data is compressed by vocoder (AMBE-2000).
Then, compressed data isencrypted in FPGA. The Encrypted data is
converted to desired level by modem & then it is sentto
telephone line. Then, on the other side, Modem will receive the
data and then, Decryption willbe done by FPGA and then, decompress
by the vocoder and then, send to telephone via SLIC(Si3210)(The
SLIC also comprises of a Codec, so, it will decode the digital to
Analogue voice).
Software Platform / ToolsVHDL & Libero 8.3 from Actel
Role & Contribution Code debugging for SLIC , UART , Modem
and adding new functionality to these source
codes
Simple Encryption and Decryption of Data.
Simulation, Synthesis and bitstream generation of VHDL code is
done..
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Toshit RalhanEMail: [email protected]
09868619819
Capture data and speech from line and transmit it to line
Brief description:Objective of project is to capture voice and
data from telephone .It has various digital signalprocessing chips
like voice codec, vocoder etc. It has Actel FPGA used for signal
processing.The drivers were coded using VHDL and successfully
implemented on FPGA.It is used fordiagnosis purpose. It is used to
diagnose the speech and data from line.
Software Platform / Tools
Language : VHDL.Tools : Libero 7.1 from Actel, Multisim and
EWB.
Role & Contribution Successfully coded and tested the Device
Drivercode fordata transfer using RS-232.
The platform used was VHDL. Successfully coded and tested the
Device Driver code for Voice Codec using VHDLplatform.
PROJECT OF Post Graduation:
Implement an Two stage compensated operational Amplifier
Brief description:
Mainly the design is concentrated on the design ofHigh Gain RC
Compensated opampright from sizing of the transisters to
development of proper layout in cadence virtuoroso
tool
Software Platform / ToolsCadence Virtuoso Tool
Role & Contribution
Team size 2
Designing, sizing of Transistors & Testing
PROJECT OF Post Graduation:
Implement an 8-bit RISC Processor using XILINX FPGA
Brief description:
This project comprised of simulating RISC Processor on FPGA.
First we design the systembased on the reference of RISC processor.
Our next step is to implement the design. It has all theblocks of
processor like Control Unit, Arithmetic and Logical unit, Program
Counter. Coding isdone in VHDL using tool ISE 9.1 of Xilinx. Our
next task is to download that code on hardware,which we done with
the help of project guide successfully.
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Toshit RalhanEMail: [email protected]
09868619819
Software Platform / ToolsXilinx 9.1,VHDL
Role & Contribution
Individual Person
Designing, Coding & Testing
Design algorithm and data flow diagram during execution of
variousInstruction. Coding of ALU and Control Unit.
END OF 8th SEM.:
Intelligent Control Of Traffic Lights Using Infra Red As a
Source
Brief description:
PDP: - Programming 8051 to resolve traffic problem on an four
way crossing by
increasing the on period of green light by 5sec by checking
after every 6th second by use
of infra red sensors
Software Platform / ToolsAssembly Language
Role & Contribution
Team member, Team size 4
Coding to generate OPCODE for microprocessor using Assembly
language.
Training Details
1. Done four weeks of industrial training in MTNL on
E10B,AXE-10,EWSD exchangeso as to understand the working of its
various components
2. Completed four weeks of industrial training in reliance
infocomm. on projectCDMA
Technology and submitted a report on usage ,applications and its
possibleimplications in the company
Personal DetailsFathers Name Shri Lalit Kumar RalhanDate of
Birth 28th Sep 1984Sex Male
Nationality Indian
Date: 2nd August 2009
Place: Delhi TOSHIT RALHAN
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