1. May 1, 2013On-the-fly design explorationframework for
simulationMay 1, 2013Lior Altman, HUJIAvi Green, IntelItai Yarom,
Synopsys
2. May 1, 2013Its worth to find bugs early2
3. May 1, 2013Re-spins
4. May 1, 2013The meaning of re-spin4
5. May 1, 2013Verification is Becoming the main Task How can we
improve the verification flow? Can we make it easier to fix
bugs?
6. May 1, 2013The Bug Fix Flow Detect simulation ends with
unexpected result Debug what caused the wrong behavior? Fix &
Verify provide a fix and verify it. Can take several simulation
iterations The time consuming element is the time it takes to
verify the fix This influence directly from how many times we rerun
the simulation
7. May 1, 2013Our Solution We focus on the fix & verify
steps We want to: provide a way to instantly check the fix
effectValidate the specific fix without the need to recompile
andresimulate all the design. compare two alternative fixes
Minimize the number of comp+elab+sim Time = #iteration X (compile,
elaboration and simulation time)
8. May 1, 2013assign o = a & b;always @(x,y,z) beginx = y;z
= x;endassign o = a & b | c;always @(x,y,z) beginz = x;x =
y;end+ | cChanging expressionsorderHow does it works
9. May 1, 2013How does it works
10. May 1, 2013The Analyze Engine The analyze engine builds
theexpression tree(s) that we wantto present on the waveform. Step
1: Find the statements thatwere changed. Step 2: Analyze the code
and determine all thestatements that will be affected. Step 3:
Analyze the context of statements Assign , Flip-Flop, Mux etc
11. May 1, 2013Updating the waveformWe are using a simulator
agnosticapproach that uses the simulatorexpressions:For each
statement (fromanalyzer) generate expression (virtualsignals). Show
them on the Waveform.No needing to resimulate!!
12. May 1, 2013Updating the waveformWe are using a simulator
agnosticapproach that uses the simulatorexpressions:For each
statement (fromanalyzer) generate expression (virtualsignals). Show
them on the Waveform.No needing to resimulate!!
13. May 1, 2013Performance The expression will be calculated on
the fly The expression can use signals and/or other expressions
values. This is very fast, since all the values are available. It
enable us to validate the specific fix without the need to
recompileand resimulate all the design. The performance is related
to: Expressions complexity Amount of expressions The viewable time
window This flow can support multiple waveform for different fixes.
Enable us to compare them and choose which fix to take
14. May 1, 2013Prove of Concept The goal of the project was to
show that it canbe done and enable designers to use it On-the-fly
calculation is available today forassertions and constraints (in
some simulators) We enable to run our framework on simplelogic
changes No support for complex SystemVerilog constructs We consider
to release the framework as anopen source for the verification
community
15. May 1, 2013Future Work Provide support for more complex
logic Improve the ability to compare between fixes Improve the
UI/UX
16. May 1, 2013Summary Chip re-spins occurmore often. The
effort of a bug fix isthe time it takes toverify it We introduced
aframework to reducethis time significantly
17. May 1, 2013On-the-fly design explorationframework for
simulationMay 1, 2013Q & AAvi Green Itai Yarom
