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Transistor Circuit DC BiasPart 1
ENGI 242
February 2003 ENGI 242 2
DC Biasing Circuits
• Fixed-Bias Circuit• Emitter-Stabilized Bias Circuit• Collector-Emitter Loop• Voltage Divider Bias Circuit• DC Bias with Voltage Feedback• Miscellaneous Bias Circuits
February 2003 ENGI 242 3
Maximum Power Curve
February 2003 ENGI 242 4
Fixed-Bias Circuit
February 2003 ENGI 242 5
DC Equivalent circuit
February 2003 ENGI 242 6
Base-Emitter (Input) Loop
Using Kirchoff’s voltage law: – VCC + IBRB + VBE = 0
Solving for IB: CC BE
B B
V - VI =
R
February 2003 ENGI 242 7
Collector-Emitter (Output) Loop
Since: IC = IB
Using Kirchoff’s voltage law: VCE – VCC – IC RC
Because: VCE = VC - VE
Since VE = 0V, then: VC = VCE
Also: VBE = VB - VE
with VE = 0V, then: VB = VBE
February 2003 ENGI 242 8
BJT Saturation RegionsWhen the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that:
CC CE Csat
C
CEwhere
V - VI =
RV = 0 .2 V
February 2003 ENGI 242 9
Determining Icsat
February 2003 ENGI 242 10
Determining Icsat for the fixed-bias configuration
February 2003 ENGI 242 11
Load Line Analysis
February 2003 ENGI 242 12
Load Line Analysis
The end points of the line are : ICsat and VCEcutoffFor load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff
ICsat:
VCEcutoff:
Where IB intersects with the load line we have the Q pointQ-point is the particular operating point: • Value of RB
• Sets the value of IB
• Where IB and Load Line intersect• Sets the values of VCE and IC.
CE
C
CC Csat V 0V
C
CE CC I 0mA
VI =
R
V = V
|
|
February 2003 ENGI 242 13
Circuit values effect Q-point
February 2003 ENGI 242 14
Circuit values effect Q-point (continued)
February 2003 ENGI 242 15
Circuit values effect Q-point (continued)
February 2003 ENGI 242 16
DC Fixed Bias Circuit Example
February 2003 ENGI 242 17
Load-line analysis
February 2003 ENGI 242 18
Fixed-bias load line
February 2003 ENGI 242 19
Movement of Q-point with increasing levels of IB
February 2003 ENGI 242 20
Effect of RC on the load line and Q-point
February 2003 ENGI 242 21
Effect of VCC on the load line and Q-point
February 2003 ENGI 242 22
Example
Emitter Stabilized Bias
February 2003 ENGI 242 24
Emitter-Stabilized Bias Circuit
Adding a resistor to the emitter circuit (between the emitter lead and ground) stabilizes the bias circuit
February 2003 ENGI 242 25
Improved Bias Stability
The addition of RE to the Emitter improves the stability of a transistorStability refers to a bias circuit in which the currents and voltages will remain fairly constant for a wide range of temperatures and transistor forward current gain ()The temperature surrounding the transistor circuit is not always constantTherefore, the transistor is not a constant value
February 2003 ENGI 242 26
Base-Emitter Loop
February 2003 ENGI 242 27
Equivalent Network
February 2003 ENGI 242 28
Reflected Input impedance of RE
February 2003 ENGI 242 29
Base-Emitter Loop
Applying Kirchoffs voltage law: - VCC + IB RB + VBE +IE RE = 0
Since: IE = ( + 1) IB
We can write: - VCC + IB RB + VBE + ( + 1) IB RE = 0
Grouping terms and solving for IB:
Or we could solve for IE with:
CC BEB
B E
V - VI =
R + (β+1)R
BCC E BE E E
R- V + I + V + I R = 0
( + 1)
February 2003 ENGI 242 30
Collector-Emitter Loop
February 2003 ENGI 242 31
Collector-Emitter Loop
Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0
Assuming that IE IC and solving for VCE: IC = VCC – VCE – (RE + RC)
Solve for VE: VE = IE RE
Solve for VC: VC = VCC - IC RC
or
VC = VCE + IE RE
Solve for VB: VB = VCC - IB RB or
VB = VBE + IE RE
February 2003 ENGI 242 32
Transistor Saturation
CC CE CSAT
C E
V - VI =
R + R
At saturation, VCE is at a minimum
We will find the value VCEsat = 0.2V
For load line analysis, we use VCE = 0
To solve for ICSAT, use the output KVL equation:
February 2003 ENGI 242 33
Load Line Analysis
The load line end points can be calculated:
At cutoff:
At saturation:
C CE CC I = 0 mAV V |
CE
CCC V = 0V
C E
VI =
R + R|
February 2003 ENGI 242 34
Emitter Stabilized Bias Circuit Example
February 2003 ENGI 242 35
Load Line For The Emitter-bias Configuration.