Triple Output AMOLED Bias · 2019-07-20 · Triple Output AMOLED Bias General Description The RT4731 is a highly integrated Boost, two LDOs (one channel for AVDD and the other channel

RT4731

Copyright © 2019 Richtek Technology Corporation. All right reserved. is a registered trademark of Richtek Technology Corporation.

DS4731-02 June 2019 www.richtek.com

1

Triple Output AMOLED Bias

General Description

The RT4731 is a highly integrated Boost, two LDOs

(one channel for AVDD and the other channel for VOP)

and inverting charge pump to generate positive and

negative output voltage. The negative output voltages

can be adjusted from 0.6V to 2.4V with 100mV per

step by SWIRE interface protocol. The part maintains

the highest efficiency by utilizing a 0.33x/0.5x mode

fractional charge pump with automatic mode transition.

With its input voltage range of 2.9V to 4.8V, the RT4731

is optimized for products powered by single-cell battery

and the output current up to 30mA. The RT4731 is

available in UBGA-21B 1.82x3.23 package to achieve

optimized solution for PCB space.

Ordering Information RT4731

Package Type

QSU : UBGA-21B 1.82x3.23

Lead Plating System

G : Green (Halogen Free and Pb Free)

Note :

Richtek products are :

RoHS compliant and compatible with the current

requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.

Features 2.9V to 4.8V Supply Voltage Range

Single Wire Protocol

Fixed 4.6V Positive Voltage Output

Positive Output Voltage AVDD 2.8V

Negative Voltage Output from 0.6V to 2.4V per

0.1V by SWIRE Pin

Auto-Mode Transition of 0.33x/0.5x Charge

Pump

Built-in Soft-Start

30mA Maximum Output Current

Programmable Output Fast Discharge Function

High Impedance Output when IC Shutdown

UVLO, OCP, SCP, OTP Protection

Shutdown Current < 1A

Available in 21-Ball UBGA Package

Applications AMOLED Bias in Portable Device

Marking Information 00 : Product Code

W : Date Code00W

Simplified Application Circuit

BST

L1

VINLXP

SWIRE

VOP

VON

C1P

RT4731

GND

CIN

VIN

CBST

VOP

COP

VON

CON

C1N

CF1

C2P

C2N

CF2

AVDD AVDD

CAVDD

AVDD_EN

VOUT

RT4731

Copyright © 2019 Richtek Technology Corporation. All rights eserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS4731-02 June 2019

2

Pin Configuration

(TOP VIEW)

C2NGND VON

SWIRE GND C2P

AVDD_ENVIN

LXP GND

C1N

C1P

GND BST VOP

AVDD_EN NC NC

GND VOUT

(SNS)AVDD

AVDD

A3A1 A2

B3B1 B2

C1 C2

D1 D2

C3

D3

E3E1 E2

F3F1 F2

G3G1 G2

UBGA-21B 1.82x3.23

Functional Pin Description Pin No. Pin Name Pin Function

A1, B2, D2, E1, G1 GND Ground.

A2 VON Negative terminal output.

A3 C2N Flying capacitor 2 negative connection.

B1 SWIRE Enable and VON voltage setting.

B3 C2P Flying capacitor 2 positive connection.

C1 VIN Power input.

C2, F1 AVDD_EN Enable for AVDD with internal connected.

C3 C1N Flying capacitor 1 negative connection.

D1 LXP Switching node of boost converter.

D3 C1P Flying capacitor 1 positive connection.

E2 BST Output voltage of boost converter.

E3 VOP Positive terminal output.

F2, F3 NC No internal connection.

G2 VOUT

(SNS)AVDD Output voltage sense

G3 AVDD AVDD LDO output.

RT4731



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Functional Block Diagram

N1

P1

SCP1

RP2

RP1

VOP

C1N

VIN

GND

LXP

PWM

Logic

UVLO

OCP1

RN2

RN1

SCP2

VON

DAC+

-

Oscillator

Pulse

Counter

VREF

Bandgap

Reference

-0.33x/-0.5x

Charge Pump

C1P

Soft-Start

LDO

+

-GM

VREF

DAC

SWIRE

VREF

Fast

Discharge

VOPVON

BST

C2P

C2N

LDO

AVDD_EN AVDD VOUT(SNS AVDD)

VIN

Operation The RT4731 is a highly integrated Boost, two LDOs

(one channel for AVDD and the other channel for VOP)

and inverting charge pump to generate positive and

negative output voltage. It can support input voltage

range from 2.9V to 4.8V and the output current up to

30mA. The VOP positive output voltage is set at a

typical value of 4.6V. The VON negative output voltage

is set at a typical value of 2.4V and can be

programmed through single wire protocol (SWIRE pin).

The available voltage range is from 0.6V to 2.4V with

100mV per step. The AVDD positive output voltage is

set at a typical value of 2.8V. The RT4731 provides

Over- Temperature Protection (OTP) and Short Circuit

Protection (SCP) mechanisms to prevent the device

from damage with abnormal operations. When the

SWIRE and AVDD_EN voltages are logic low, the IC will

be shut down with low input supply current less than

1A.

RT4731



4

Absolute Maximum Ratings (Note 1)

Supply Input Voltage VIN Pin ----------------------------------------------------------------------------------------- 0.3V to 6V

Output Voltage VOP Pin ----------------------------------------------------------------------------------------------- 0.3V to 6V

Output Voltage AVDD Pin --------------------------------------------------------------------------------------------- 0.3V to 6V

Output Voltage VON Pin ----------------------------------------------------------------------------------------------- 6V to 0.3V

VIN to VON --------------------------------------------------------------------------------------------------------------- 0.3V to 7.5V

C2N to GND -------------------------------------------------------------------------------------------------------------- 6V to 0.3V

Others Pin to GND ------------------------------------------------------------------------------------------------------ 0.3V to 6V

Power Dissipation, PD @ TA = 25°C

UBGA-21B 1.82x3.23 ------------------------------------------------------------------------------------------------- 0.88W

Package Thermal Resistance (Note 2)

UBGA-21B 1.82x3.23, JA ------------------------------------------------------------------------------------------- 112.2C/W

Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260C

Junction Temperature ------------------------------------------------------------------------------------------------- 150C

Storage Temperature Range ---------------------------------------------------------------------------------------- 65C to 150C

ESD Susceptibility (Note 3)

HBM (Human Body Model) ------------------------------------------------------------------------------------------ 2kV

Recommended Operating Conditions (Note 4)

Supply Input Voltage Range ----------------------------------------------------------------------------------------- 2.9V to 4.8V

Positive Output Voltage ----------------------------------------------------------------------------------------------- 4.6V

Negative Output Voltage Range ------------------------------------------------------------------------------------ 2.4V to 0.6V

AVDD Output Voltage ------------------------------------------------------------------------------------------------- 2.8V

Ambient Temperature Range --------------------------------------------------------------------------------------- 40C to 85C

Junction Temperature Range --------------------------------------------------------------------------------------- 40C to 125C

Electrical Characteristics (VIN = 3.7V, VOP = 4.6V, VON = 2.4V, AVDD = 2.8V, CIN = 4.7F, CBST = 20F, COP = 10F, CAVDD = 1F, CON = 30F, CF1 =

1F, L1 = 2.2H, TA = 25°C, unless otherwise specified.)

Parameter Symbol Test Conditions Min Typ Max Unit

Power Supply

Input Voltage Range VIN 2.9 -- 4.8 V

Under Voltage Lockout

Threshold Voltage

VUVLO_H VIN rising -- 2.2 2.5 V

VUVLO_HYS VIN hysteresis -- 100 -- mV

Over-temperature Protection TOTP (Note 5) -- 140 -- C

Over-temperature Protection

Hysteresis TOTP_HYST (Note 5) -- 15 -- C

Shutdown Current ISHDN SWIRE = 0V -- -- 1 A

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VOP

Positive Output Voltage Range VOP -- 4.6 -- V

Positive Output Voltage

Accuracy VOP_ACC 1 -- 1 %

Positive Output Current

Capability

IOP_MAX -- -- 30 mA

IOP_HBM VOP = 4.6V, VON |2.2|V -- -- 55

Positive Output Voltage Ripple VOP_RIPPLE IOP = 20mA (Note 5) -- 10 -- mV

Line Regulation VOP_LINE VIN = 2.9V to 4.8V, IOP = 20mA

(Note 5) -- 5 -- mV

Load Regulation VOP_LOAD IOP = 0mA to 30mA (Note 5) -- 5 -- mV

Fast Discharge Resistance RDISP -- 105 --

Short Circuit Protection VSCP1 -- < 80%

VOP -- V

AVDD

Positive Output Voltage Range AVDD VIN = 2.9V to 4.8V -- 2.8 -- V

Positive Output Voltage

Accuracy AVDD_ACC IAVDD=1mA 2 -- 2.5 %

Positive Output Current

Capability IAVDD_MAX -- -- 300 mA

AVDDEN Input Current IAVDD_EN VAVDD_EN = 3.3V -- -- 1 uA

Line Regulation AVDD_LINE VIN = 2.9V to 4.8V, IAVDD = 1mA -- 0.13 0.35 %

Load Regulation AVDD_LOAD IAVDD = 1mA to 300mA -- 0.5 1 %

Output Current Limit IAVDD_LIM VAVDD = 90%VAVDD 350 600 -- mA

Logic Input (AVDD_EN)

AVDD Enable

Input Voltage

Logic-High VIH 0.9 -- -- V

Logic-Low VIL -- -- 0.4 V

Charge Pump Output

Negative Output Voltage

Range VON 2.4 -- 0.6 V


Setting Range VON_SET Per step -- 100 -- mV


Accuracy VON_ACC 1 -- 1 %

Negative Output Current

Capability

ION_MAX (Note 5) -- -- 30

mA ION_HBM

VOP = 4.6V, VON |2.2|V

(Note 5) -- -- 55

Negative Charge Pump

Switching Frequency fOSC_N 0.8 1 1.2 MHz


Ripple VON_RIPPLE ION = 20mA (Note 5) -- 20 -- mV

RT4731



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Line Regulation VON_LINE VIN = 2.9V to 4.8V, ION = 20mA

(Note 5) -- 10 -- mV

Load Regulation VON_LOAD ION = 0mA to 30mA (Note 5) -- 30 -- mV

Fast Discharge Resistance RDISN -- 60 --

Short Circuit Protection VSCP2 -- > 80%

VON -- V

Logic Input (SWIRE)

SWIRE Turn-off Detection

Time toff_dly 350 -- -- s

SWIRE Signal Stop Indicate

Time tstop 350 -- -- s

Twait after Data twait_int 10 -- -- ms

Rising Input High Threshold

Voltage Level VIH 1.2 -- VIN V

Falling Input Low Threshold

Voltage Level VIL 0 -- 0.4 V

SWIRE Pull Low Resistor RSWIRE -- 300 -- k

Wake up Delay twkp -- -- 1 s

SWIRE Rising Time tR -- -- 200 ns

SWIRE Falling Time tF -- -- 200 ns

Clocked SWIRE High tON 2 10 40 s

Clocked SWIRE Low tOFF 2 10 40 s

SWIRE to VOP On Time tVOP_ON -- 1.6 -- ms

Input Clocked SWIRE

Frequency fSWIRE 25 -- 250 kHz

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These

are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect

device reliability.

Note 2. JA is measured under natural convection (still air) at TA = 25C with the component mounted on a high effective-thermal-

conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Spec. is guaranteed by design.

RT4731



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Typical Application Circuit

BST

L1

4.7µF

VINLXP

SWIRE

VOP

VON

C1P

-0.6V to -2.4V

RT4731

GND

E3

A2

D3

A1, B2, D2, E1, G1

B1

B3

C1

E2

CIN

VIN

2.9V to 4.8V

2.2µH

D110µFCBST1

VOP

COP10µF

4.6V

VON

CON110µF

C1NC3

CF11µF

C2P

C2NA3

CF2

1µF

CON210µF

AVDDG3 VAVDD

CAVDD1µFAVDD_EN

C2, F12.8V

VOUTG2

10µFCBST2

CON310µF

Table 1. Component List of Evaluation Board

Reference Qty. Part Number Description Package Supplier

CIN 1 GRM188R61C475KAAJ 4.7F/16V/X5R 0603 Murata

CBST1, CBST2, COP,

CON1, CON2, CON3 6 GRM188R61A106KE69 10F/10V/X5R 0603 Murata

CAVDD 1 GRM155R61C105KE01 1F/16V/X5R 0402 Murata

CF1, CF2 2 GRM155R61C105KE01 1F/16V/X5R 0402 Murata

L1 1

1269AS-H-2R2M=P2 2.2H 2.5mmx2.0mmx1.0mm Murata

GLCLK2R201A 2.2H 2.5mm x 2.0mm x 1.0mm ALPS

ZTFL-201610TB-2R2M 2.2H 2.0mm x 1.6mm x 1.0mm ZenithTek

Time Diagram

SWIRE Interface

90%

10%

tON tOFF

tRtF

twkp

RT4731



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Power Sequence

AVDD_EN

AVDD

0

0

2.8V

0

SWIRE

VOP

VON

tss1 ≤ 3ms

0

0

0

4.6V

-2.4V

1 2

tstop > 350μstss2 ≤ 2ms

-1.4V

twait_int > 10ms

toff_dly > 350μs

1.5ms ≤ Tdly ≤ 2.5ms 10 11

…

tVOP_ON

Hi-Z

Hi-Z

0VIN

Table 2. VON Output Voltage with SWIRE Pulse

Pulse VON(V)

0 2.4 (default)

1 2.4

2 2.3

3 2.2

4 2.1

5 2.0

6 1.9

7 1.8

8 1.7

9 1.6

10 1.5

11 1.4

12 1.3

13 1.2

14 1.1

15 1.0

16 0.9

17 0.8

18 0.7

19 0.6

20 0

RT4731



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Table 3. VOP/VON Shutdown Discharge Selection with SWIRE Pulse

Pulse Discharge

21 Enable

Once pulse 21 received on SWIRE pin, the RT4731 will enable the discharge function to discharge the VOP/VON

outputs for 20ms and then enter high impedance state when fault or power-off condition. The discharge function

is default disabled and outputs keep high impedance state when fault or power-off condition .

RT4731



10

Typical Operating Characteristics

VOP, VON Efficiency vs. Output Current

60

65

70

75

80

85

90

0 5 10 15 20 25 30

Output Current (mA)

Effic

ien

cy (

%)

VOP = 4.6V, VON = 2.4V, AVDD = 0V

4.5V

3.7V

2.9V

VOP vs. Output Current

4.590

4.591

4.592

4.593

4.594

4.595

4.596

4.597

4.598

4.599

4.600

0 5 10 15 20 25 30

Output Current (mA)

VO

P (

V)

VOP = 4.6V, VON = 2.4V

4.5V

3.7V

2.9V

VON vs. Output Current

-2.405

-2.403

-2.401

-2.399

-2.397

-2.395

0 5 10 15 20 25 30

Output Current (mA)

VO

N (

V)

VOP = 4.6V, VON = 2.4V

2.9V

3.7V

4.5V

AVDD vs. Output Current

2.800

2.801

2.802

2.803

2.804

2.805

2.806

2.807

2.808

2.809

2.810

0 5 10 15 20 25 30

Output Current (mA)

AV

DD

(V)

AVDD = 2.8V

4.5V

3.7V

2.9V

VOP vs. Input Voltage

4.594

4.595

4.596

4.597

4.598

4.599

4.600

2.8 3.05 3.3 3.55 3.8 4.05 4.3 4.55 4.8

Input Voltage (V)

VO

P (

V)

VOP = 4.6V, VON = 2.4V

IOPON = 10mA

IOPON = 20mA

VON vs. Input Voltage

-2.3980

-2.3975

-2.3970

-2.3965

-2.3960

-2.3955

-2.3950

2.8 3.05 3.3 3.55 3.8 4.05 4.3 4.55 4.8

Input Voltage (V)

VO

N (

V)

VOP = 4.6V, VON = 2.4V

IOPON = 20mA

IOPON = 10mA

RT4731



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AVDD vs. Input Voltage

2.8050

2.8055

2.8060

2.8065

2.8070

2.8075

2.8080

2.8085

2.8090

2.8095

2.8100

2.8 3.05 3.3 3.55 3.8 4.05 4.3 4.55 4.8

Input Voltage (V)

AV

DD

(V

)

AVDD = 2.8V

IAVDD = 20mA

IAVDD = 10mA

VIN = 3.7V, VOP = 4.6V, VON = 2.4V

SWIRE

(5V/Div)

VOP

(2V/Div)

VON

(2V/Div)

VBST

(5V/Div)

Time (1ms/Div)

Power On (VOP, VON)

AVDD_EN

(5V/Div)

AVDD

(1V/Div)

Time (1ms/Div)

Power On (AVDD)

VIN = 3.7V, AVDD = 2.8V

SWIRE

(5V/Div)

VOP

(2V/Div)

VON

(2V/Div)

VBST

(5V/Div)

Time (20ms/Div)

Power Off without Discharge (VOP, VON)

VIN = 3.7V, VOP = 4.6V, VON = 2.4V

SWIRE

(5V/Div)

VOP

(2V/Div)

VON

(2V/Div)

VBST

(5V/Div)

Time (20ms/Div)

Power Off with Discharge (VOP, VON)

VIN = 3.7V, VOP = 4.6V, VON = 2.4V

AVDD_EN

(5V/Div)

AVDD

(1V/Div)

Time (1ms/Div)

Power Off (AVDD)

VIN = 3.7V, AVDD = 2.8V

RT4731



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Application Information The RT4731 is a highly integrated Boost, LDO and

inverting charge pump to generate positive and

negative output voltages for AMLOED bias. It can

support input voltage range from 2.9V to 4.8V and the

output current up to 30mA. The VOP positive output

voltage is generated from the LDO supplied from a

synchronous Boost converter, and VOP is set at a typical

value of 4.6V. The Boost converter output also drives

an inverting charge pump controller to generate VON

negative output voltage which is set at a typical value of

2.4V. The negative output voltage can be programmed

through the dedicated pin which implements single wire

protocol and the available voltage range is from 0.6V

to 2.4V with 100mV per step. The AVDD positive

voltage is generated from a LDO supplied from VIN. It

is set at a typical value of 2.8V.

Input Capacitor Selection

Input ceramic capacitor with 4.7F capacitance is

suggested for applications. For better voltage filtering,

select ceramic capacitors with low ESR, X5R and X7R

types are suitable because of their wider voltage and

temperature ranges.

Boost Inductor Selection

The inductance depends on the maximum input current.

As a general rule, the inductor ripple current range is

20% to 40% of the maximum input current. If 40% is

selected as an example, the inductor ripple current can

be calculated according to the following equations :

OUT OUT(MAX)IN(MAX)

IN

L IN(MAX)

V II =

V

I = 0.4 I

where η is the efficiency of the VOP Boost converter,

IIN(MAX) is the maximum input current, and IL is the

inductor ripple current. The input peak current can then

be obtained by adding the maximum input current with

half of the inductor ripple current as shown in the

following equation :

IPEAK = 1.2 x IIN(MAX)

Note that the saturated current of the inductor must be

greater than IPEAK.

The inductance can eventually be determined

according to the following equation :

2

2

IN OUT IN

OUT OUT(MAX) OSC

η V V VL

0.4 V I f

where fOSC is the switching frequency. For better

system performance, a shielded inductor is preferred to

avoid EMI problems.

Boost Output Capacitor Selection

The output ripple voltage is an important index for

estimating IC performance. This portion consists of two

parts. One is the product of ripple current with the ESR

of the output capacitor, while the other part is formed by

the charging and discharging process of the output

capacitor. As shown in Figure 1, VOUT1 can be

evaluated based on the ideal energy equalization.

According to the definition of Q, the VOUT1 value can

be calculated as the following equation :

OUT OUT OUT1SOC

OUTOUT1

SOC OUT

1Q = I D = C V

f

I DV =

f C

where fOSC is the switching frequency and D is the duty

cycle.

Finally, taking ESR into consideration, the overall output

ripple voltage can be determined by the following

equation :

OUTOUT ESR OUT1 ESR

OSC OUT

I DV = V + V = V +

f C

where VESR = ICrms x RCESR

The output capacitor, COUT, should be selected

accordingly.

RT4731



13

Input Current Inductor Current

Output Current

Time

Time

Output Ripple (ac)DTs

IL

VOUT1

Figure 1. Output Ripple Voltage Without Contribution

of ESR

Under Voltage Lockout

To prevent abnormal operation of the IC in low voltage

condition, an under voltage lockout is included which

shuts down VOP, VON operation when input voltage is

lower than the specified threshold voltage.

Soft-Start

The RT4731 employs an internal soft-start feature to

avoid high inrush current during start-up. The soft-start

function is achieved by clamping the output voltage of

the internal error amplifier with another voltage source

that is increased slowly from zero to near VIN during the

soft-start period.

Negative Output Voltage Setting

The Negative output voltage can be programmed by a

MCU through the dedicated pin according to Table 2

“VON Output Voltage with SWIRE Pulse”.

Shutdown Delay and Discharge

When the SWIRE signal is logic low for more than

350s. The output VOP/VON can be actively discharged

to GND with discharge function enabled referring to

Table 3 “VOP/VON Shutdown Discharge Selection with

SWIRE Pulse”. The AVDD voltage can be shut down if

AVDD_EN is logic low. In shutdown mode, the input

supply current for the IC is less than 1A.

Over Current Protection

The RT4731 includes a cycle-by-cycle current limit

function which monitors the inductor current during each

ON period. The power switch will be forced off to avoid

large current damage once the current is over the limit

level. The AVDD LDO contains an independent current

limiter which limits the output current to 0.6A (typ.). The

current limiting level is reduced to around 0.3A named

fold-back current limit when the output voltage is further

decreased.

Short Circuit Protection

The RT4731 has an advanced output short-circuit

protection mechanism which prevents the IC from

damage by unexpected applications. When VOP/VON

becomes shorted to ground, and the output voltage is

under the limit level with 1ms (typ.) duration, the bias

function enters shutdown mode and can only re-start

normal operation after triggering the SWIRE pin.

Over Temperature Protection

The RT4731 equips an over temperature protection

circuitry to prevent overheating due to excessive power

dissipation. The OTP will shut down VOP/VON operation

when temperature exceeds 140C (typ.). The AVDD

operation will be shut down when temperature exceeds

140C (typ.), and the output current exceeds 80mA.

Once the ambient temperature cools down by

approximately 15C, IC will automatically resume

normal operation. To maintain continuous operation,

the maximum junction temperature should be prevented

from rising above 125C.

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

PD(MAX) = (TJ(MAX) TA) / JA

where TJ(MAX) is the maximum junction temperature, TA

RT4731



14

is the ambient temperature, and JA is the junction-to-

ambient thermal resistance.

For continuous operation, the maximum operating

junction temperature indicated under Recommended

Operating Conditions is 125C. The junction-to-ambient

thermal resistance, JA, is highly package dependent.

For a UBGA-21B 1.82x3.23 package, the thermal

resistance, JA, is 112.2C/W on a standard JEDEC 51-

7 high effective-thermal-conductivity four-layer test

board. The maximum power dissipation at TA = 25C

can be calculated as below :

PD(MAX) = (125C 25C) / (112.2C/W) = 0.88W for a

UBGA-21B 1.82x3.23 package

The maximum power dissipation depends on the

operating ambient temperature for the fixed TJ(MAX) and

the thermal resistance, JA. The derating curve in Figure

2 allows the designer to see the effect of rising ambient

temperature on the maximum power dissipation.

Figure 2. Derating Curve of Maximum Power

Dissipation

Layout Considerations

For the best performance of the RT4731, the following

PCB layout guidelines should be strictly followed.

For good regulation, place the power components as

close to the IC as possible. The traces should be wide

and short especially for the high current output loop.

The input and output bypass capacitor should be

placed as close to the IC as possible and connected

to the ground plane of the PCB.

The flying capacitor should be placed as close to the

C1P/C1N/C2P/C2N pin as possible to avoid noise

injection.

Minimize the size of the LXP node and keep the

traces wide and short. Care should be taken to avoid

running traces that carry and noise-sensitive signals

near LXP or high-current traces.

Separate power ground (PGND) and analog ground

(GND). Connect the GND and the PGND islands at a

single end. Make sure that there are no other

connections between these separate ground planes.

.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 25 50 75 100 125

Ambient Temperature (°C)

Ma

xim

um

Po

we

r D

issip

atio

n (

W) 1 Four-Layer PCB

RT4731



15

Outline Dimension

Symbol Dimensions In Millimeters Dimensions In Inches

Min. Max. Min. Max.

A 0.430 0.630 0.017 0.025

A1 0.100 0.200 0.004 0.008

b 0.190 0.290 0.007 0.011

D 3.180 3.280 0.125 0.129

D1 2.700 0.106

E 1.770 1.870 0.070 0.074

E1 1.300 0.051

e 0.450 0.018

e1 0.650 0.026

21B UBGA 1.82x3.23 Package

Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Documents

Triple Output AMOLED Bias · 2019-07-20 · Triple Output AMOLED Bias General Description The RT4731 is a highly integrated Boost, two LDOs (one channel for AVDD and the other channel