Trusted and Assured Microelectronics Hardware Assurance … · 2018-03-09 · Trusted and Assured Microelectronics Hardware Assurance Evaluation and Test Capabilities. Matthew Casto

Trusted and Assured Microelectronics Hardware Assurance Evaluation and Test

CapabilitiesMatthew Casto on behalf of Jeremy Muldavin

Office of the Deputy Assistant Secretary of Defense for Systems Engineering

2018 ITEA Cybersecurity Workshop Fort Walton Beach, FL | March 7, 2018

ITEA Cyber Workshop March 7, 2018 | Page-1 Distribution Statement A – Approved for public release by DOPSR. Distribution is unlimited.

ITEA Cyber WorkshopMarch 7, 2018 Page-2

Future Warfighting SystemsAdvanced Microelectronics Needs

Human and Robot Collaboration

Miniature and Swarming

System of Systems

Cyber and Social

Autonomous and Collaborative

Diverse Protected Links

Human and RobotSystems

Big Data and AI Systems

DecentralizedSystems

Global Tech and Infrastructure

Artificial Intelligence (AI)and Graph Processors

Open and Distributed Architecture & Processing

Vision, Semantic andNavigation Processing

Frequency and Antenna Diversity Signal Proc.

Leverage & Assure Accessto the best Technology

• Local processing raw data• Rapid tech. insertion &

upgrades using SotA

• 100B-1T node graphs• Need 1000x performance

and efficiency for real-time

• High performance imagers & local processing circuits

• Robust Navigation & local semantic processing

• Multi-antenna & frequencies• Adaptive processing (Trillion

Ops/sec/watt) for robust comm. & radar systems

• Use best global tech where it exists

• Assure domestic sources for state-of-art

Distribution Statement A – Approved for public release by DOPSR. Distribution is unlimited.


Electronics as a Strategic Issue

Current TacticalIssue

DoD Trusted Electronics Issue• While the number of trusted suppliers is

increasing there remains access challenges at leading edge nodes

Larger Strategic

Issue

COTS Electronics Trust (DoD & Beyond†)• Most COTS electronics used in DoD systems are

fabricated overseas; significant risk from tamper• Risks similar for the broader national security

community, banking, critical infrastructure, etc.

Access to Electronics / Electronics based economic growth

• Shift in electronics fabrication creates potential for overseas control

• End of Moore’s Law potential carries economic impacts

† Including the broader national security community, banking, critical infrastructure, commercial industry, etc.

Significant electronics challenges represent a strategic level national issue

FY03-CurrentTrusted Foundry Program

PB 17:Trusted & Assured Micro-electronics

POM 18 and beyondDoD Micro-electronics Innovation for National Security (MINSEC)



NDAA FY 2017 S231Strategy Request Summary

1. Define the various levels of trust required by DoD systems2. Identify means of classifying DoD systems based on the required level of trust

for microelectronics within the system3. Identify means by which trust in microelectronics can be assured4. Identify a means to increase the supplier base for assured microelectronics to

ensure multiple supply pathways5. Provide an assessment of the microelectronics needs of the DoD in future

years, including the need for trusted, radiation-hardened microelectronics6. Provide an assessment of the microelectronics needs of the DoD that may not

be fulfilled by entities outside the DoD7. Identify the resources required to assure access to trusted microelectronics,

including infrastructure workforce, and investments in science and technology8. Develop a research and development strategy to ensure the DoD can, to the

maximum extent practicable, use state of the art commercial microelectronics capabilities or their equivalent, while satisfying the needs for trust

9. Develop recommendations for changes in authorities, regulations, and practices, including acquisition policies, financial management, public-private partnership policies, or in any other relevant areas, that would support the achievement of goals of the strategy


ITEA Cyber WorkshopMarch 7, 2018 | Page-5 Distribution Statement A – Approved for public release by DOPSR. Distribution is unlimited.

Trusted Foundry and Trusted & Assured Microelectronics (T&AM) Purpose

Program goals:• Protect microelectronic designs and intellectual property (IP) from espionage and

manipulation• Advance DoD hardware analysis capability, e.g., physical, functional, and design verification

and validation, and commercial design standards and practices • Develop, mature, demonstrate, and transition new microelectronics assurance model that

leverages commercial state-of-the-art (SOTA) capabilities and ensures future accessTechnical challenges:

• Develop alternate assured photomask capability to preserve long-term trusted access and protection of IP (Trusted Foundry only)

• Scale/enhance the government’s ability to detect security flaws in integrated circuits• Leverage academic and industry research for assuring microelectronics from any supplier

Program partners: • DoD science & technology (S&T), acquisition communities, academia, industry

OSD Program: • Program Elements activities are being coordinated by the Office of the Assistant Secretary of

Defense for Research and Engineering (ASD(R&E)) since the effort encompasses a broad range of performers from other DoD Components, activities, and agencies as well as Intelligence Community S&T organizations and laboratories


Microelectronics (ME) Assurance Process Flow

Analyses

Criticality

Threats

Vulnerabilities

Risk AssessmentCONOPS

Capabilities

Needs

Systems of

SystemsSystemsBoards

Components

Assurance Required

Assurance Process

Flow

Mitigations Manufacture1234

Designer Supplier

Con

sequ

ence

Likelihood

ASICs, 8

Display Logic, 2.7Interface, 30.3

Logic ASSPs, 2.8

Data Converters, 29.4

DSP, 6

Microprocessors, 0.261 Microcontrollers,

23.2Analog ASSPs, 76.8

SRAM, 3.4

DRAM, 85.8

Flash, 33.2

Amplifiers and Comparators, 33.8

Power, 167

General Purpose Logic, 81.8

FPGAs, 11.1

Quantities (M), Total 596M

ASICs

Display Logic

Interface

Logic ASSPs

Data Converters

DSP

Microprocessors

Microcontrollers

Analog ASSPs

SRAM

DRAM

Flash

Amplifiers and Comparators

Power

General Purpose Logic

FPGAs

IDA Data: Based on dataBeans 2017, quantities in millions


What We are Doing

Policy

• DoD Instruction (DoDI) 5000.02

• Program Protection Plan (PPP)

• NDAA FY2017, Sec 231 Strategy for Assured MicroE

• National Security Strategy

Joint Federated Assurance Center

• Software assurance knowledge & tools

• Hardware assurance knowledge & tools

• Advanced verification & validation capabilities

Trusted & Assured

Microelectronics• Access to state-of-

the-art foundries• Trust and

assurance methods and demonstration

• Industrial best practices for assurance

DoD MINSEC

• Capture and secure R&D

• New capability development

• COTS Co-Dev• Radiation

hardened microE• RF and OE

MINSEC – Microelectronics Innovation for National Security and Economic Competitiveness


JFAC

• JFAC is a federation of DoD SwA and HwA capabilities and capacities– To support programs in addressing current and emerging threats and

vulnerabilities– To facilitate collaboration across the Department and throughout the lifecycle of

acquisition programs– To maximize use of available resources– To assess and recommend capability and capacity gaps to resource

• Innovation of software and hardware inspection, detection, analysis, risk assessment, and remediation tools and techniques to mitigate risk of malicious insertion– R&D is key component of JFAC operations– Focus on improving tools, techniques, and procedures for SwA and HwA to

support programs

• Federated Organizations– Army, Navy, AF, NSA, DMEA DISA, NRO, and MDA laboratories and engineering

support organizations; Intelligence Community and Department of Energy

The mission of JFAC is to support programs with SwA and HwA needsDistribution Statement A – Approved for public release by DOPSR. Distribution is unlimited.


Long-Term Strategy Time Line

2015 2016 2017 2018 2019 2020 2021 2020 2023 2024

Alternate Source for Trusted PhotomasksPreparation activities

Improve capabilities and capacity, and provide support to program needs, for analysis of microelectronics trust

Identify and develop standards, practices, and partnerships to improve availability of trust from commercial providers

Preparation activities

Verification and Validation (V&V) Capabilities and Standards for Trust

Advanced Technology and Alternative Techniques for Microelectronics Hardware Trust

Preparation activities

Trusted and Assured Microelectronics Program:

Transition

DoD Trusted Foundry Program Consolidation - Defense Microelectronics Activity (DMEA)

Newly Established Trusted Foundry Contract

Sustained Network of Trusted Certified Suppliers

Deploy new capabilitiesCapability development and demonstration

Capability Development Deploy new capability



Systems Engineering Approach(Managing ME supply-chain & life-cycle risk)

… …

PPP AssuredDesign

SystemSecurity Architecture

Op. Sec. & Anti TamperSwAHwA

QualityEscape

MaliciousInsertion

PPP/CPI

Programdevelopment andcapabilities

Design Verify Mask Fabrication Pack.andtest

Verify andvalidate

Config./prog.SW

Integrateand test

Operationand maint..

Counterfeit& Excess

MaliciousInsertion

QualityEscape

Info.Loss

Info.Loss

Rev. Eng.

Rev. Eng.

QualityEscape

Mitigation

ImpactEfficacy DoD& Industry

Integrity

ThreatTrustedMask

Innovators &Developers

System architectsR&D engineers

Acquisition expertsManufacturing

experts

Threats

Mitigations

Adopters & Improvers

System integratorsTest and validation

Operators and maintainers



New Trust and Assurance Approaches

Implement and demonstrate assurance capability with transition partners

QualityEscape

MaliciousInsertion

PPP/CPI

ProgramDevelopment andCapabilities


Verify andvalidate

Config./prog. SW

Integrateand test

Operation and maint.

Counterfeit& Excess

MaliciousInsertion

QualityEscape

Info.Loss

Info.Loss

Rev. Eng.

Rev. Eng.

QualityEscape

Design for trust

• Designing techniques to limit full use/functionality to trusted operation

IP protection

• Preventing exploitation, including control of use, concealment, reconfiguring, partitioning, or employment

Low-volume/high-mix

production• Innovative

methods to permit cost-effective, Trusted and assured low volume manufacturing of state-of-the-art ICs

Electronic component

markers• Tagging/marking

ICs and subassemblies to authenticate and track supply chain movements

Imaging technologies and

forensics • Advanced

capabilities to efficiently evaluate dense, state-of-the-art commercial components



Additional Source for Trusted Photomasks

• Develop second leading-edge Trusted photomask shop− Trusted flow in data preparation and manufacturing designs needed to manage risk of IP

theft and malicious alteration− A second leading-edge (<130nm) source will ensure tape-in/mask release, mask

manufacturing, and authentication process

• MIT-LL• Cypress 90nm• On-Semi• Future DMEA• Northrop Grumman• BAE, M/A-Com,

Triquint, etc.

• Facility• Hardware• Software• People

Secure Mask Fab Secure Masks

Metrics

1) Hardware & Facility Acquired2) Demonstrated IOC3) Monitor

# Photomasks# Acquisition Programs#Node sizes

GDS Sources



Microelectronics Trust Verification Technologies

• Verification needed when Trusted Foundry not available– DoD formed JFAC to provide this service– Long-term challenge to analyze leading-edge ICs and scale up capacity

Design Verification

• Verification/assurance of designs, IP, netlists, bit-streams, firmware, etc.

Physical Verification

• Destructive analysis of ICs and Printed Circuit Boards

Functional Verification

• Non-destructive screening and verification of select ICs

DoD, Intelligence Community, and DoE enhancing capability to meet future demand



Radiation Hardened Summary

• These tasks will help develop innovative, trusted approaches for strategic radiation-hardened electronics

• Stakeholders:– Performers: NSWC Crane, SPAWAR (SSC-PAC), Naval Research

Lab, MIT-LL, and Draper Laboratories – Coordinating with: Air Force, MDA, Sandia, NASA, and space

radiation effects community • Top-level activities – Each task is focused on providing

an alternative source(s) for strategic RH electronics– Strategic RH Electronics Council– RHBD design (high-voltage analog; verification of Sandia PSOC)– MIT-LL 90-nm FDSOI MPW run– Radiation testing of analog test chips, 90-nm FDSOI, FPGAs, and

non-volatile memories– Strategic RH module demonstration (using alternative sources)– Qualification of strategic RH parts– NRL hardening efforts at trusted foundries


Navy Strategic Rad-Hard • NSWC Crane performed initial prompt radiation dose tests on 14 & 16 nm FinFET ASICs

from GF, Intel, Samsung, and TSMC– Inherent dose rate radiation tolerance is high and in nearly all cases upset threshold exceeds old ITAR

levels– SPAWAR (SCC-Pac) & NSWC Crane are surveying foundries for rad-hard (RH) analog IC capability– Strategic Radiation Hardened Electronics Council (SRHEC) charter created

FY18 Technical Highlight


Use Second Order Circuit Emanations to Characterize and Validate Circuitry


Output Signature Changes with Added Circuitry


Building Reference Signatures to Assess of Probability of Detection


Validation & Verification Enablement

• Advancements in the ability to quickly and efficiently image and analyze dense state-of-the-art microelectronics circuits and systems

• Multi-modal and non-destructive techniques for imaging planar, 2.5D, and 3D microsystems and circuits

• Computational and algorithmic methods to determine connectivity, function, activity, and aberrations in complex circuits through imaging techniques

QualityEscape

MaliciousInsertion

PPP/CPI



Verify andvalidate

Config./prog. SW

Integrateand test


Counterfeit& Excess

MaliciousInsertion

QualityEscape

Info.Loss

Info.Loss

Rev. Eng.

Rev. Eng.

QualityEscape

Imaging technologies and

forensics • Advanced

capabilities to efficiently evaluate dense, state-of-the-art commercial components



Operational Confidentiality & Integrity

• Methods an technologies to establish provenance of all IP and physical components of a microsystem through the supply chain

• Authentication and access control techniques to ensure that the devices are used as intended

• Methods and systems for electronically tracking and analyzing supply chain movements and the security of those systems

QualityEscape

MaliciousInsertion

PPP/CPI



Verify andvalidate

Config./prog. SW

Integrateand test


Counterfeit& Excess

MaliciousInsertion

QualityEscape

Info.Loss

Info.Loss

Rev. Eng.

Rev. Eng.

QualityEscape

Electronic component

markers• Tagging/marking

ICs and subassemblies to authenticate and track supply chain movements



A Potential New Approach for Achieving MicroE Assurance

Current Approach Cyber-Physical Approach

New cyber-physical standards and gov’t leadership necessary for assurance

ITEA Cyber WorkshopMarch 7, 2018 Page-22 Distribution Statement A – Approved for public release by DOPSR. Distribution is unlimited.

The Threat of Loss ofMicroelectronics Leadership

Current 14-nm foundries

1

2

4

2 , 5

6

7

Current 14-nm foundriesNew advanced foundries

4

R&Descape

Current Global Microelectronics Leadership

Possible Future Global Microelectronics Leadership

Supply Risk

DomesticSources

Asia• Significant increase in # of fabless firms

– 3,000 new in 2017• Multiple Joint Ventures and acquisitions• Investments of $150B+ in advanced microelectronics and $60B+ in STEM and universities• TSMC offers $200M a year in free silicon to universities

U.S. Ecosystem• Strong domestic fabless

semiconductor industry–Apple, Qualcomm,

others dominate profits–Hardware startups

falling behind foreigners• Integrated Device

Manufacturers at risk • R&D from top universities

migrates to Europe & Asia

Asia• Leading world-class

microelectronics design and production capability

–7 new (≤14nm) foundries

• Trade policies:–Increase domestic

market share–Acquisitions and

startups funded by government

U.S. Ecosystem• Strong global fabless

semiconductor industry–U.S. companies invest in

Asian production• Integrated Device

Manufacturers diversify• Overproduction globally

forces domestic fabrication closure

• Best R&D from Asia

R&Descape

Supply Risk

Supply Risk


Past and Current Analogous Situations

Japan• Trade and industrial

actions in ‘70s & ’80s to increase semiconductor market share

–Largely successful, U.S. lost significant market share and fab capacity.

Technology slow down due to scaling physical limitations could result in leadership transition

1970 1980 1990 2000 2010 2020

China• In 2015, stated plan to reach “advanced

world-level in all major semiconductor industry segments by 2030.”

–Subsidies: ($150B over 10 years), direct funding by state-owned companies, & foreign company and IP purchase

–Zero-sum trade policies• Current status:

–Foundries now 2-3 generations behind–Seven (7) state-of-the-art fabrication

starts planned–No domestically owned memory, but

major memory investments –Significant increase in # of fabless firms

Taiwan• Created ITRI in ‘70s, a

government funded R&D Institute. Spun off multiple companies, including TSMC

• Today, 4th in global market share

• TSMC is world’s largest pure-play foundry

U.S. Government Response

• VHISC ($918M) was DoD program to develop two new generations of IC tech

• MIMIC ($570M) was DoD program to accelerate GaAs technology

US Gov. & Industry Response

• SEMATECH ($870M + industry match) partnership of 14 U.S. companies

–Transitioned from government to private funding only and international partners joined

?


Microelectronics Strategy Challenges & Investments

Commercial Access

Commercial & Assured Gov. Line

Government dual use

R&D facilities

Access & Assurance

Enabling Manufacturing

State-of-the-Art

Disruptive R&D

Legacy&

Boutique

State-of-the Practice

Science &Technology

Preserving US Government Partnerships in SOTP

Preserve & Enhance Government Unique Capabilities Enhance and Bridge Disruptive

R&D to Domestic Production

Access to Assured SOTA in US



Strategic National Security Applications

Strategic National Economic Competitiveness Applications

Secure IoT Autonomous Systems + AI

Robust + AgileCommunicators

Commercial SpaceFinancial & Data Analytics

Biomedical

Disruptive Research & Development

Access & Assurance

Enhanced Manufacturing

Incentives &Market Growth

Materials, Devices, Circuits Design Tools for ComplexityArchitectures

Experts, Infrastructure, Venture Capital Innovation, Science & Technology, R&D

• Secure Design • IP, EDA, experts• Foundry assured

Access• Prototype

Demonstrations

• SOTP Back-end parity with SOTA

• SOTA on 200mm tools at SOTP

• High-mix low vol. fabrication

• Acquisition reform and incentives

• Tax, policy, regulation reform

• R&D and domestic fab incentives

Rebuilding U.S. Microelectronics Leadership and Dominance

ProactiveAwareness &Security• Supply Chain track• Proactive

Authorities• Intelligence & CI• Standards

Strategic Alliances• Cooperative R&D• Trade and Foreign

Military Sales (FMS)• Americas• Europe• Asia partners



Create Microelectronics Innovation Throughout the United States

Fabrication Center

Design Center

ProactiveAwareness &

Security

Awareness & Security R&D

Capture

Fabrication Center

InnovationHub

Design Center

Access & Assurance


StrategicAlliances

StrategicAlliances

Strategic Alliances

R&D Capture

Incentives &Market Growth

Incentives and Mkt Growth



Proactive Awareness

Access & Assurance


Results

Proposed MINSEC

New Capability Development & Insertion(JFAC/Services/SCO/FFRDC)

COTS ProgrammableCo-Development (JFAC/MIBP)

Capture & Secure R&D and Production in US Ecosystem(JFAC/MIBP/FFRDC/USD(I))

Workforce Dev.(JFAC/DAU/FFRDC)

Develop the Next Generation Technology(DARPA/IARPA/DOE)

Rad Hard(JFAC/NNSA/FFRDC/MDA)

RF & Optical(JFAC/Services/FFRDC)

3.1% 77.3% 19.6%

Cap

ture

&

Sec

ure

R&

DM

oder

niza

tion

& S

ecur

ity

Deliver business, IC, publication, and patent awareness to inform critical technologies

Dis

rupt

ive

R&

DSp

ecia

ltyN

eeds

32.9%

14.5%

27.0%

9.5%

9.8%

Properly informedAuthorities and IP protection

Intelligence and CIAwareness for criticalmanufacturers

Supply chain awareness & threats, proper authorities

Access to SOTA & SOTP fabrication & R&D fabrication facilities for development

Secure design IP, EDA tools; experts to capture & secure IP

Secure design,IP, EDA tools, experts fab access, prototypingSecure design,IP, EDA tools, experts for virtual V&V

Cooperative Development with industry for new products

Secure design,IP, EDA tools, fab for RBHD test articles

Enhanced SOTPGov. & merchant facilities for RHBP

Capture R&D in SOTP enhanced, secure Gov. & merchant fabs

Obsolescence &Replacement (JFAC/DLA)

US and DoD creates the next generation technology for future systems

R&D capture, nurtured, and secured in domestic ecosystem, with assurance built in

RHBP and RHBD for strategic and space applications

3 demos of 10-1000x performance gain for program insertion

Assured SOTA COTS available for DoD systems & applications

Secure design,IP, EDA tools; experts to capture & secure IP

2.6%

Supply chain awareness & threats

Secure design,IP, EDA tools, fab access for demos

Enhanced SOTPGov. & merchant facilities for RF & optical devices

Pilot RF and optical US capabilities for DoD

3.6%


Domestic Ecosystem

New Capability Development Operational View

Materials

Devices

ArchitecturesDesign Tools

Innovation Ecosystem

High-Mix Fabs Package & Test

State-of-Practice

State-of-Art

GovernmentExpert

Designers

Industry & Academic Designers

End-userExperts V&V

Analysts

Super-computer Emulators

Administrators, Business Managers & Architects

Software & Test

EDA ToolsIP Library

SW Assurance & Validation Tools

Secure Enclaves

Modernized SystemsResearch & Development

Innovators & Developers

Academia

RFPGovernment

Industry

Design Tools

Materials Devices

ArchitecturesFabricate & Package

Integrate & Demonstrate



Systems Engineering:Critical to Defense Acquisition

Defense Innovation Marketplacehttp://www.defenseinnovationmarketplace.mil

DASD, Systems Engineeringhttp://www.acq.osd.mil/se



For Additional Information

Dr. Jeremy MuldavinODASD, Systems Engineering

571-372-6690 [email protected]


Documents

Trusted and Assured Microelectronics Hardware Assurance … · 2018-03-09 · Trusted and Assured Microelectronics Hardware Assurance Evaluation and Test Capabilities. Matthew Casto