TURBO CODES IN UMTS/ WIMAX/ LTE SYSTEMS : SOLUTIONS FOR AN EFFICIENT FPGA I MPLEMENTATION · 2016-09-11 · LTE SYSTEMS: SOLUTIONS FOR AN EFFICIENT FPGA I MPLEMENTATION Ph. D. Cristian

TURBO CODES IN UMTS/ WIMAX/

LTE SYSTEMS: SOLUTIONS FOR AN

EFFICIENT FPGA IMPLEMENTATION

Ph. D. Cristian ANGHEL

INTRODUCTION

IARIA - The Eleventh Advanced International Conference on Telecommunications AICT 2015

Physical Layer - PHY

Radio Link Control - RLC

Media Access Control - MAC

Radio Resource Control - RRC

Non-Access Stratum - NAS

Telecom Protocol Stack

INTRODUCTION

� Forward Error Coding – FEC

� Source coding

� Channel coding

� Block codes (Hamming, Hadamard, cyclic)

� Convolutional codes

� Non-systematic convolutional codes NSC

� Recursive systematic covolutional codes RSC

� Turbo codes

� Systematic codes used in a pseudo-random manner

� All codes are good, except the ones we can think of

(Jacob Wolfowitz)


TURBO CODES

� Turbo coding principle

� Coding rate

� [1] C. Berrou, A. Glavieux, and P. Thitimajshima, Near Shannon limit error-correcting coding and decoding: Turbo Codes, IEEE Proceedings of the Int. Conf. on Communications, Geneva, Switzerland, May 1993, pp. 1064-1070.

� [2] C. Berrou and A. Glavieux, Near optimum error correcting coding and decoding: Turbo-Codes, IEEE Trans. Communications, vol. 44, no. 10, pp. 1261-1271, Oct. 1996.

� [3] C. Berrou and M. Jézéquel, Non binary convolutional codes for turbo coding, Electronics Letters, vol. 35, no. 1, pp. 9-40, Jan. 1999.


1

3c

R =

TURBO CODES

� UMTS/ WiMAX/ LTE RSC turbo encoder


TURBO CODES

� UMTS/ WiMAX/ LTE RSC trellis


0

1

2

3

4

5

6

7

k k+1 k+2

00/00

11/00

10/11

01/11

10/11

01/11

00/00

11/00

00/10

11/10

10/01

01/01

10/01

01/01

00/10

11/10

01/00

10/00

11/11

00/11

11/11

00/11

01/00

10/00

01/10

10/10

11/01

00/01

11/01

00/01

01/10

10/10

00/00

11/00

10/11

01/11

10/11

01/11

00/00

11/00

00/10

11/10

10/01

01/01

10/01

01/01

00/10

11/10

01/00

10/00

11/11

00/11

11/11

00/11

01/00

10/00

01/10

10/10

11/01

00/01

11/01

00/01

01/10

10/10

TURBO DECODER

� UMTS/ LTE RSC turbo decoder


( )'2

o

kXΛ ( )2

o

kXΛ

( )1

o

kXΛ

( )i

kXΛ

( )i

kZΛ

( )'i

kZΛ

TURBO DECODER

� WiMAX RSC turbo decoder


( )01,

i

k kA BΛ

( )10,

i

k kA BΛ

( )11,

i

k kA BΛ

( ),1kWΛ

( ),1kYΛ

( ),2kYΛ

( ),2kWΛ

( )01,

o

k kA BΛ

( )10,

o

k kA BΛ

( )11,

o

k kA BΛ

( )' '

11,

o

k kA BΛ

( )' '

10,

o

k kA BΛ

( )' '

01,

o

k kA BΛ ( )kAΛ

( )kBΛ

TURBO DECODER

� Decoding algorithm


max*( , ) ln(e e )

max( , ) ln(1 e ) max( , ).

x y

y x

x y

x y x y− −

= + =

+ + ≈

TURBO DECODER

� Max-Log MAP – WiMAX


( )( )( )

,, log

,0, 0

P A a B bk k

A Ba b k k

P A Bk k

= =

Λ =

= =

( ) ( ) ( ) ( )1 ,,

i j i

k k k a b k k k kS S A B w W y Yγ+

→ = Λ + Λ + Λ

( ) ( ) ( ){ }1

'

1 1 1 1max

jik k

j i i j

k k k k k k kS S

S S S Sα α γ+

+ + + +

→

= + →

( ) ( ) ( )' ' 0

1 1 1 1 1 1

j j

k k k k k kS S Sα α α+ + + + + +

= −

( ) ( ) ( ){ }1

'

1 1 1 1max

jik k

i j i j

k k k k k k kS S

S S S Sββ γ+

+ + + +

→

= + →

( ) ( ) ( ) ( )1 1 1 1 1

i j i i j j

k k k k k k k k k kZ S S S S S Sα γ β+ + + + +

→ = + → +

( )( )

{ }1: ,

, maxji

k k

k kS S a b

t a b Z+→

=

( ) ( ) ( ),

, , 0,0o

a b k k k kA B t a b tΛ = −

( ) ( ) ( ){ }

( ) ( ){ }

1,0 1,1

0,0 0,1

max , , ,

max , , ,

o o

k k k k k

o o

k k k k

A A B A B

A B A B

Λ = Λ Λ −

Λ Λ

( ) ( ) ( ){ }

( ) ( ){ }

0,1 1,1

0,0 1,0

max , , ,

max , , ,

o o

k k k k k

o o

k k k k

B A B A B

A B A B

Λ = Λ Λ −

Λ Λ

TURBO DECODER



( )

( ) ( )

( ) ( )

( ) ( )

0 0

1

0 3 0

1 11

0 4 0

1 10

0 7 0

1 01

0

,

, ( ) ( )

, ( ) ( )

k k k

k k k k k

k k k k k k k

k k k k k k k

S S

S S A B

S S A B Y W

S S A B Y W

γ

γ

γ

γ

+

+

+

+

→ =

→ = Λ

→ = Λ + Λ + Λ

→ = Λ + Λ + Λ

( ) ( )

( ) ( )

( )

( ) ( )

1 0 0

1 10

1 3 0

1 01

1 4

1

1 7 0

1 11

, ( ) ( )

, ( ) ( )

0

,

k k k k k k k

k k k k k k k

k k k

k k k k k

S S A B Y W

S S A B Y W

S S

S S A B

γ

γ

γ

γ

+

+

+

+

→ = Λ + Λ + Λ

→ = Λ + Λ + Λ

→ =

→ = Λ

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

' 0 0 0 0

1 1 1 1

' 0 3 0 3

1 1 1 1

' 0 4 0 4

1 1 1 1

' 0 7 0 7

1 1 1 1

a

k k k k k k k

b

k k k k k k k

c

k k k k k k k

d

k k k k k k k

S S S S

S S S S

S S S S

S S S S

β

β

β

β

β γ

β γ

β γ

β γ

+ + + +

+ + + +

+ + + +

+ + + +

= + →

= + →

= + →

= + →

( ) ( ) ( ) ( ) ( ){ }' 0 ' 0 ' 0 ' 0 ' 0max , , ,

a b c d

k k k k k k k k k kS S S S Sβ β β β β=

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

' 0 0 0 0

1 1 1

' 0 1 1 0

1 1 1

' 0 6 6 0

1 1 1

' 0 7 7 0

1 1 1

a

k k k k k k k

b

k k k k k k k

c

k k k k k k k

d

k k k k k k k

S S S S

S S S S

S S S S

S S S S

α α γ

α α γ

α α γ

α α γ

+ + +

+ + +

+ + +

+ + +

= + →

= + →

= + →

= + →

( ) ( ) ( ) ( ) ( ){ }' 0 ' 0 ' 0 ' 0 ' 0

1 1 1 1 1 1 1 1 1 1max , , ,

a b c d

k k k k k k k k k kS S S S Sα α α α α

+ + + + + + + + + +=

TURBO DECODER



( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

( ) ( ) ( )

0 0 0 0 0 0

1 1 1 1 1

1 4 1 1 4 4

1 1 1 1 1

2 1 2 2 1 1

1 1 1 1 1

3 5 3 3 5 5

1 1 1 1 1

4 6 4 4 6

1 1 1

k

k

k

k

k

a

k k k k k k k k k

b

k k k k k k k k k

c

k k k k k k k k k

d

k k k k k k k k k

e

k k k k k k k

Z S S S S S S

Z S S S S S S

Z S S S S S S

Z S S S S S S

Z S S S S S

α γ β

α γ β

α γ β

α γ β

α γ

+ + + + +

+ + + + +

+ + + + +

+ + + + +

+ + +

→ = + → +

→ = + → +

→ = + → +

→ = + → +

→ = + → ( )

( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

6

1 1

5 2 5 5 2 2

1 1 1 1 1

6 7 6 6 7 7

1 1 1 1 1

7 3 7 7 3 3

1 1 1 1 1

k

k

k

k k

f

k k k k k k k k k

g

k k k k k k k k k

h

k k k k k k k k k

S

Z S S S S S S

Z S S S S S S

Z S S S S S S

β

α γ β

α γ β

α γ β

+ +

+ + + + +

+ + + + +

+ + + + +

+

→ = + → +

→ = + → +

→ = + → +

( )( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

0 0 1 4 2 1 3 5

1 1 1 1

4 6 5 2 6 7 7 3

1 1 1 1

, , , ,0,0 max

, , ,

k k k k

k k k k

a b c d

k k k k k k k k

ke f g h

k k k k k k k k

Z S S Z S S Z S S Z S S

t

Z S S Z S S Z S S Z S S

+ + + +

+ + + +

→ → → → =

→ → → →

TURBO DECODER

� Max-Log MAP – LTE


( ) ( ) ( ) ( )V , , ,i

ij k kX X i j Z Z i jγ = +Λ

( )( ) ( ) ( )

( ) ( ) ( ){ }

( )( )

( )

1

'

2 1

'

V W ,forSISO1V

V IL W ,forSISO2

, forSISO1

, forSISO2

i

k k k

k o

k k k

i

ki

k i

k

X X X

XX X X

Z

ZZ

= Λ +=

= Λ −

ΛΛ =

Λ

( )

( )

( ) ( )

0

1

2

3

0

V

V

k

i

k

i

k k

X

Z

X Z

γ

γ

γ

γ

=

=

= Λ

= + Λ

00 0 04 3

10 3 14 0

21 1 25 2

31 2 35 1

42 2 46 1

52 1 56 2

63 3 67 0

73 0 77 3

;

;

;

;

;

;

;

;

γ γ γ γ

γ γ γ γ

γ γ γ γ

γ γ γ γ

γ γ γ γ

γ γ γ γ

γ γ γ γ

γ γ γ γ

= =

= =

= =

= =

= =

= =

= =

= =

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( )

0 00 4 04

0 10 4 14

1 21 5 25

1 31 5 3

0 1 1

1 1 1

2 1 1

3 1 1

4 1

5

2 42 6 46

2

1

5 1 152 6

ˆ max ( ), ( )

ˆ max ( ), ( )

ˆ max ( ), ( )

ˆ max ( ), ( )

ˆ max ( ), ( )

ˆ max ( ), (

k k k

k k k

k k k

k k k

k k k

k k k

S S S

S S S

S S S

S S S

S S S

S S S

β β γ β γ

β β γ β γ

β β γ β γ

β β γ β γ

β β γ β γ

β β γ β

+ +

+ +

+ +

+ +

+ +

+ +

= + +

= + +

= + +

= + +

= + +

= + +{ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

56

3 63 7 676 1

3 73 7

1

7 1 771

)

ˆ max ( ), ( )

ˆ max ( ), ( )

k k k

k k k

S S S

S S S

γ

β β γ β γ

β β γ β γ

+ +

+ +

= + +

= + +

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

( ) ( ) ( )

0 00 1 10

2 21 3 31

4 42 5 52

6 63 7 7

0 1 1

1 1 1

2 1 1

3 1 1

4 1

3

0 04 1 14

2

1

5 1 125 3

ˆ max ( ),( )

ˆ max ( ), ( )

ˆ max ( ), ( )

ˆ max ( ),( )

ˆ max ( ), ( )

ˆ max ( ), (

k k k

k k k

k k k

k k k

k k k

k k k

S S S

S S S

S S S

S S S

S S S

S S S

α α γ α γ

α α γ α γ

α α γ α γ

α α γ α γ

α α γ α γ

α α γ α

− −

− −

− −

− −

− −

− −

= + +

= + +

= + +

= + +

= + +

= + +{ }

( ) ( ) ( ){ }

( ) ( ) ( ){ }

35

4 46 5 566 1

6 67 7

1

7 1 771

)

ˆ max ( ), ( )

ˆ max ( ), ( )

k k k

k k k

S S S

S S S

γ

α α γ α γ

α α γ α γ

− −

− −

= + +

= + +

TURBO DECODER

� Max-Log MAP – LTE


( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

0 00 0

1 14 4

2 25 5

3 31 1

4 42 2

5 56 6

6 67

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7

7 73 3

0,0

1,4

2,5

3,1

4,2

5,6

6,7

7,3

k

k

k

k

k

k

k

k

k k

k k

k k

k k

k k

k k

k k

k k

S S

S S

S S

S S

S S

S S

S S

S S

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

−

−

−

−

−

−

−

−

+

+

+

+

+

= +

= +

= +

= +

= +

=

= +

+ +

+

=

+

+

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

0 04 4

1 10 0

2 21 1

3 35 5

4 46 6

5 52 2

6 63

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

3

7 77 7

0,4

1,0

2,1

3,5

4,6

5,2

6,3

7,7

k

k

k

k

k

k

k

k

k k

k k

k k

k k

k k

k k

k k

k k

S S

S S

S S

S S

S S

S S

S S

S S

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

λ α γ β

−

−

−

−

−

−

−

−

+

+

+

+

+

= +

= +

= +

= +

= +

=

= +

+ +

+

=

+

+

( ) ( ) ( )1 0

( ): 1 ( ): 0max { , } max { , },

i j i i j i

o

k k kS S X S S X

X i j i jλ λ→ = → =

Λ = −

TURBO DECODER

� LTE - Quadratic Permutation Polynomial (QPP)

interleaver


Kififi mod)()( 2

21⋅+⋅=π

( )0 1 1 2

0 0 2

1 1 2

2 2 1 0 2

2

sum (0) ,sum (0) 0,sum (0) 0

0 0

1: 1

sum ( ) sum ( 1)

sum ( ) sum ( 1)

sum ( ) sum ( 1) sum ( 1) sum ( 1)

( ) sum ( ) mod

f

for i K

i i f

i i f

i i i i f

i i K

end

π

π

= = =

=

= −

= − +

= − +

= − + − + − +

=

TURBO DECODER


interleaver


0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

SISO

MEM

39, 38, 37,�, 5,4,3,2,1,0

TURBO DECODER


interleaver


0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

SISO

MEM

7,34,1,28,...,12,19,6,13,0

TURBO DECODER


interleaver


0

1

2

3

4

SISO0

MEM0

4,3,2,1,0

5

6

7

8

9

SISO1

MEM1

9,8,7,6,5

10

11

12

13

14

SISO2

MEM2

14,13,12,11,10

15

16

17

18

19

SISO3

MEM3

19,18,17,16,15

20

21

22

23

24

SISO4

MEM4

24,23,22,21,20

25

26

27

28

29

SISO5

MEM5

29,28,27,26,25

30

31

32

33

34

SISO6

MEM6

34,33,32,31,30

35

36

37

38

39

SISO7

MEM7

39,38,37,36,35

TURBO DECODER


interleaver


0

1

2

3

4

SISO0

MEM0

12,19,6,13,0

5

6

7

8

9

SISO1

MEM1

37,24,31,18,25

10

11

12

13

14

SISO2

MEM2

2,9,36,3,30

15

16

17

18

19

SISO3

MEM3

7,14,21,8,15

20

21

22

23

24

SISO4

MEM4

32,39,26,33,20

25

26

27

28

29

SISO5

MEM5

17,4,11,38,5

30

31

32

33

34

SISO6

MEM6

22,29,16,23,10

35

36

37

38

39

SISO7

MEM7

7,34,1,28,35

0

1

2

3

4

SISO0

MEM0

12,19,6,13,0

5

6

7

8

9

SISO1

MEM1

37,24,31,18,25

10

11

12

13

14

SISO2

MEM2

2,9,36,3,30

15

16

17

18

19

SISO3

MEM3

7,14,21,8,15

20

21

22

23

24

SISO4

MEM4

32,39,26,33,20

25

26

27

28

29

SISO5

MEM5

17,4,11,38,5

30

31

32

33

34

SISO6

MEM6

22,29,16,23,10

35

36

37

38

39

SISO7

MEM7

7,34,1,28,35

0

1

2

3

4

SISO0

MEM0

12,19,6,13,0

5

6

7

8

9

SISO1

MEM1

37,24,31,18,25

10

11

12

13

14

SISO2

MEM2

2,9,36,3,30

15

16

17

18

19

SISO3

MEM3

7,14,21,8,15

20

21

22

23

24

SISO4

MEM4

32,39,26,33,20

25

26

27

28

29

SISO5

MEM5

17,4,11,38,5

30

31

32

33

34

SISO6

MEM6

22,29,16,23,10

35

36

37

38

39

SISO7

MEM7

7,34,1,28,35

TURBO DECODER


interleaver


K/N

locations

N positions per

location

Index i = 0 : K-1

WA = mod(i, K/N)

WP = floor(i, K/N)

RA = WA + 1

PC=IL(i)

WA = write address

RA = read address

WP = write position

PC = position content

IL = interleaver

...

TURBO DECODER

� LTE – reordering unit: even-odd merge sorting


TURBO DECODER

� LTE – split with overlap


TURBO DECODER

� WiMAX – proposed architecture


AG

MEM

IN

MEM

AUX

MEM

IN2

MEM

W

MEM

PARIL

M

U

X

1

D

M

U

X

1

M

U

X

2D

M

U

X

2

+

+

+

DLY+

+

+

+ + +

+

+

+

- - -

--

-

+ + +

SISO

CONTROL

1Tclk 1Tclk

6Tclk

LLR

2

BYTE

Read addressWrite addressWrite enable

Start trellisData ValidDelay value

SISO1/2Switch in.buff

Mux1 SelMux2 Sel

( )10 ,

i

k kA BΛ

( )01 ,

i

k kA BΛ

( )11 ,

i

k kA BΛ

( ),k jYΛ

( ),k jWΛ

TURBO DECODER

� LTE – proposed architecture


( )i

kXΛ

( )i

kZΛ

( )'i

kZΛ

( )1

o

kXΛ

( )'2

o

kXΛ

( )2

o

kXΛ ˆ

kX

2

o

Λ

2

o

Λ

TURBO DECODER

� LTE – SISO proposed architecture


( )

( )1

'

2

V /

V

k

k

X

X

( )

( )'/

i

k

i

k

Z

Z

Λ

Λ

( )

( )1

'

2

/o

k

o

k

X

X

Λ

Λ

TURBO DECODER

� LTE – timing diagram: serial vs. parallel


Λi(Xk)

memory

Λi(Zk)

memory

Λi(Z’k)

memory

W(Xk)

memory

V2(Xk)

memory

GAMMA

ALPHA

BETA

MEM_BETA

L

SISO

MO

DU

LE

S f

rom

AR

CH

ITE

CT

UR

E

SISO1 SISO2

R(K-1:0) R(0:K-1)

R(K-1:0) R(0:K-1)

COMPUTE COMPUTE

COMPUTE

COMPUTE

COMPUTE

COMPUTE COMPUTE

COMPUTE

COMPUTE

COMPUTE

W(0:K-1)

RESET/W(K-1:0) RESET/R(0:K-1)

W(K-1:0) R(0:K-1)

R{IL(K-1:0)} R{IL(0:K-1)}

W(K-1:0) R(0:K-1)

Λ2

o(X’k)

memory

R(K-1:0) R(0:K-1)

W{IL(0:K-1)}

TIME

(clock periods)

0 2K+Delay 3K+Delay 4K+2*DelayK

R(K-1:0)

R(K-1:0)

IL

memoryR(K-1:0) R(0:K-1)

TURBO DECODER


Λi(Xk)

memory

Λi(Zk)

memory

Λi(Z’k)

memory

W(Xk)

memory

V2(Xk)

memory

GAMMA

ALPHA

BETA

MEM_BETA

L

SISO

a

MO

DU

LE

S fro

m A

RC

HIT

EC

TU

RE

SISO1SISO2

R(K/2-1:0) R(0:K/2-1)

R(K/2-1:0) R(0:K/2-1)

COMPUTE COMPUTE

COMPUTE

COMPUTE

COMPUTE

COMPUTE COMPUTE

COMPUTE

COMPUTE

COMPUTE

W(0:K/2-1)

RESET/W(K/2-1:0) RESET/R(0:K/2-1)

W(K/2-1:0) R(0:K/2-1)

R{IL(K/2-1:0)} R{IL(0:K/2-1)}

W(K/2-1:0) R(0:K/2-1)

Λ2

o(X’k)

memory

R(K/2-1:0) R(0:K/2-1)

W{IL(0:K/2-1)}

GAMMA

ALPHA

BETA

MEM_BETA

L

SISO

b

TIME

(clock periods)

0 K+Delay 3K/2+Delay 2K+2*DelayK/2

COMPUTE COMPUTE

COMPUTE

COMPUTE

COMPUTE

COMPUTE COMPUTE

COMPUTE

COMPUTE

COMPUTE

W(K/2-1:0) R(0:K/2-1) W(K/2-1:0) R(0:K/2-1)

R(K/2-1:0)

R(K/2-1:0)

IL

memoryR(K/2-1:0) R(0:K/2-1)

OBTAINED RESULTS

� WiMAX


Number of Iterations Block Size

L=48, QPSK 1/2 K=1, QPSK 1/2

1 1.5 2 2.5 3 3.5 4 4.5 510

-6

10-5

10-4

10-3

10-2

10-1

100

RSZ[dB]

REB

K= 1

K= 2

K= 3

K= 4

BER

SNR[dB]

1 1.5 2 2.5 3 3.5 4 4.5 510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

RSZ[dB]

REB

L= 24

L= 48

L= 240

BER

SNR[dB]

OBTAINED RESULTS

� WiMAX


Number of Retransmisions

L=24, QPSK ½, K=4

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 310

-5

10-4

10-3

10-2

10-1

100

RSZ[dB]

REP

transmisie

1 retransmisie

2 retransmisii

3 retransmisii

4 retransmisii

PER

SNR[dB]

transmission

1 retransmission

2 retransmission

3 retransmission

4 retransmission

OBTAINED RESULTS

� LTE

Number of Iterations Block Size

L=512, QPSK 1/2 K=3, QPSK 1/2


-6 -5 -4 -3 -2 -1 0 1 210

-6

10-5

10-4

10-3

10-2

10-1

100

SNR [dB]

BER

K=40

K=512

K=6144

-6 -5 -4 -3 -2 -1 0 1 2 310

-5

10-4

10-3

10-2

10-1

100

SNR [dB]

BER

iter=1

iter=2

iter=3

iter=4

iter=5

OBTAINED RESULTS

� LTE

Parallel N=2 Parallel N=4

L=512, QPSK 1/2, K=3 L=1024, QPSK 1/2, K=3


-3 -2 -1 0 1 2 310

-5

10-4

10-3

10-2

10-1

100

QPSK, 3 iter, 512 bits, N = 2

SNR[dB]

BER

serial

parallel with overlap

parallel without overlap

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.510

-5

10-4

10-3

10-2

10-1

100

QPSK, 1024, 3 iter, N = 4

SNR[dB]

BER

parallel with overlap

parallel without overlap

serial

CONCLUSIONS

� Efficient Max-Log MAP implementation

� Only one SISO

� All latency-reduction procedures can be applied

over the proposed decoding scheme

� Turbo decoding serial architecture adapted for

parallel decoding

� Only one interleaver used in the proposed parallel

decoding architecture

� Efficient implementation for the interleaver

� Almost identical decoding performances for serial

vs. parallel decoding when small overlap accepted



THANK YOU

[email protected]

Documents

TURBO CODES IN UMTS/ WIMAX/ LTE SYSTEMS : SOLUTIONS FOR AN EFFICIENT FPGA I MPLEMENTATION · 2016-09-11 · LTE SYSTEMS: SOLUTIONS FOR AN EFFICIENT FPGA I MPLEMENTATION Ph. D. Cristian