TUSB9260 Implementation Guide (Rev. C)

Application ReportSLLA301C–August 2010–Revised February 2011

TUSB9260 Implementation GuideLee Myers .......................................................................................... Computer Connectivity Solutions

ABSTRACT

This document is provided to assist platform designers in implementing the TUSB9260 USB 3.0 to SerialATA Bridge Controller. Detailed information can be found in the TUSB9260 Data Manual (SLLS962). Thisdocument provides board design recommendations for the various device features when designing in theTUSB9260.

This document is intended for developers familiar with high-speed PCB design and layout. Knowledge ofthe USB 3.0 and SATA specifications and protocol is required as well. The following layoutrecommendations should not be considered the sole method of implementation, but rather as a guide. Thepreferences of the individual developer, requirements of the design, number of components in the circuit,as well as many other factors will influence each individual layout.

xxx

xxx

xxx

Contents1 TUSB9260 Typical System Implementation ............................................................................. 32 Power Considerations ...................................................................................................... 4

2.1 1.1-V and 3.3-V Digital Supplies ................................................................................. 42.2 1.1-V, 1.8-V and 3.3-V Analog Supplies ........................................................................ 42.3 Ground Terminals .................................................................................................. 42.4 Capacitor Selection Recommendations ......................................................................... 42.5 Power-Up/Down Sequencing ..................................................................................... 42.6 External Voltage Regulator Recommendation ................................................................. 52.7 TUSB9260 Power Consumption ................................................................................. 52.8 USB VBUS .......................................................................................................... 5

3 USB Connection ............................................................................................................ 53.1 High-Speed Differential Routing ................................................................................. 53.2 SuperSpeed Differential Routing ................................................................................. 6

4 SATA Connection ........................................................................................................... 64.1 SATA Differential Routing ......................................................................................... 6

5 ESD Protection .............................................................................................................. 76 GPIO Terminals ............................................................................................................. 7

6.1 GPIO[7:0] ........................................................................................................... 76.2 GPIO[8/UART_RX:9/UART_TX] ................................................................................. 76.3 GPIO[10/SPI_CS2:11/SPI_CS1] ................................................................................. 7

7 PWM Terminals ............................................................................................................. 78 JTAG Interface .............................................................................................................. 79 External Reference Clock .................................................................................................. 7

9.1 Crystal Selection ................................................................................................... 89.2 External Clock/Oscillator Selection .............................................................................. 9

10 Serial Peripheral Interface (SPI) ......................................................................................... 1011 Precision Reference Return Resistor ................................................................................... 1112 External PLL Loop Capacitors ........................................................................................... 1113 Example Schematics ...................................................................................................... 11

1SLLA301C–August 2010–Revised February 2011 TUSB9260 Implementation GuideSubmit Documentation Feedback

© 2010–2011, Texas Instruments Incorporated

http://www.ti.com/lit/pdf/SLLS962

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum= SLLA301C

www.ti.com

List of Figures

1 Typical System Implementation ........................................................................................... 3

2 Example Crystal Implementation.......................................................................................... 8

3 Example Reference Clock Layout ........................................................................................ 9

4 Example Oscillator Implementation ..................................................................................... 10

5 SPI Connection ............................................................................................................ 10

List of Tables

1 TUSB9260 Nominal Power Consumption by Voltage Rail (Approximate)........................................... 5

2 Internal JTAG Resistor Termination ...................................................................................... 7

3 External Reference Clock Selection ...................................................................................... 8

4 Flash Devices Tested on the TUSB9260............................................................................... 11

2 TUSB9260 Implementation Guide SLLA301C–August 2010–Revised February 2011Submit Documentation Feedback



USB 3.0

SuperSpeed

PC with

USB 3.0

Support

USB 2.0

High-speed

SATA

Gen 1/2Serial ATA Device

SPI JTAG

GPIO/PWMCLOCK

SPI

FLASH

Crystal or

Oscillator

HDDActivity

LED

Optional

JTAGHeader

TUSB9260

www.ti.com TUSB9260 Typical System Implementation

1 TUSB9260 Typical System Implementation

Figure 1 represents a typical implementation of the TUSB9260 USB 3.0 to Serial ATA Bridge. The deviceserves as a bridge between a downstream USB 3.0 host port and a SATA device such as a hard diskdrive. A crystal or oscillator supplies the required clock source. A SPI Flash device contains the firmwarethat is loaded into the TUSB9260 after the de-assertion of RESET. Push buttons or any other desired logiccan be connected to the TUSB9260 GPIO terminals. The TUSB9260 can also output a pulse widthmodulated signal that can be used to drive an activity LED.

Figure 1. Typical System Implementation




Power Considerations www.ti.com

2 Power Considerations

2.1 1.1-V and 3.3-V Digital Supplies

The TUSB9260 requires 1.1-V and 3.3-V digital power source.

The 1.1-V terminals are named VDD11. These terminals supply power to the digital core. The 1.1- V coreallows for a significant reduction in both power consumption and logic switching noise.

The 3.3-V terminals are named VDD33 and supply power to most of the input and output cells.

Both VDD11 and VDD33 supplies must have 0.1-µF bypass capacitors to VSS (ground) to ensure properoperation. One capacitor per power terminal is sufficient and should be placed as close to the terminal aspossible to minimize trace length. Smaller value capacitors like 0.01-µF are also recommended on thedigital supply terminals.

When placing and connecting all bypass capacitors, high-speed board design rules must be followed.

2.2 1.1-V, 1.8-V and 3.3-V Analog Supplies

A Pi filter is recommended on all analog power terminals to minimize circuit noise. These filters can becombined on a per-rail basis for a total of three (VDDA11/VDDA11_USB2) + (VDDA18/VDDR18) +(VDDA33).

Analog power terminals must have a 1-µF and a 10-µF bypass capacitor connected to VSSA (ground) toensure proper operation. Place the capacitor as close as possible to the associated terminal to minimizetrace length. Smaller value capacitors such as 0.1-µF and 0.01-µF are also recommended on the analogsupply terminals.

2.3 Ground Terminals

VSS, VSSA, VSS18, and VSS33 can be connected together to form one ground plane. This techniqueallows for creating a large image plane for the signal layer directly adjacent to the ground plane.

2.4 Capacitor Selection Recommendations

When selecting bypass capacitors for the TUSB9260 device, X7R-type capacitors are recommended. Thefrequency versus impedance curves, quality, stability, and low-cost of these capacitors make them alogical choice for most computer systems.

The selection of bulk capacitors with low-ESR specifications is recommended to minimize low-frequencypower supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolyticcapacitors. These capacitors typically have ESR specifications that are less than 0.01 Ω at 100 kHz. Also,several manufacturers sell “D” size surface mount specialty polymer solid aluminum electrolytic capacitorswith ESR specifications slightly higher than 0.01 Ω at 100 kHz. Both of these bulk capacitor optionssignificantly reduce low-frequency power supply noise and ripple.

2.5 Power-Up/Down Sequencing

All TUSB9260 analog and digital power terminals must be controlled during the power-up and power-downsequence to ensure that absolute power terminal ratings are not exceeded as doing so can result indamage to the device.

No particular power-up or power-down sequencing of the power rails is required.

For additional power requirements, please refer to the TUSB9260 Data Manual (SLLS962).



http://www.ti.com/lit/pdf/SLLS962


www.ti.com USB Connection

2.6 External Voltage Regulator Recommendation

Since the TUSB9260 requires three voltage supplies (1.1-V, 1.8-V, and 3.3-V) a multi-channel voltageregulator is recommended. The TPS650061 or TPS65024x are good choices. The TPS650061 utilizes aDCDC converter and two LDO regulators in a single package. The DCDC converter can supply 1-Anominal current while the two LDO’s can supply 300-mA nominal current. Since the 1.1-V supply canconsume upwards of 340-mA of current the DCDC converter is ideal for supplying the 1.1-V current whilethe two LDO’s can be used to supply 1.8-V and 3.3- V current. Likewise the TPS65024x utilizes threeDCDC converters and three LDO’s. Both devices also have a built in supervisor circuit that can beconnected to GRST# on the TUSB9260.

2.7 TUSB9260 Power Consumption

Nominal power ratings for the TUSB9260 are shown in Table 1. Measurements were taken at nominalvoltage while transferring data via USB3 to a SSD drive.

Table 1. TUSB9260 Nominal Power Consumption by Voltage Rail (Approximate)

VOLTAGE RAIL CURRENT POWER

3.3 V 6 mA 19.8 mW

1.8 V 58 mA 104.4 mW

1.1 V 319 mA 350.9 mW

Total 383 mA 475.1 mW

2.8 USB VBUS

Power can be supplied via a USB cable on the terminal VBUS. VBUS is a 5-V source that is connected tothe USB_VBUS terminal on the TUSB9260 via a voltage divider. Connect a 90.9-kΩ, 1% resistor from thecable VBUS connector to the USB_VBUS terminal on the TUSB9260 and a 10-kΩ, 1% resistor fromUSB_VBUS to ground.

2.8.1 Limiting Inrush Current on VBUS

To prevent inrush current the TI TPS2560/61 is recommended. Inrush current can occur on VBUS when afunction is plugged into the network. For example the bulk capacitance used to supply power to the SATAdevice can be quite large, causing inrush current when the USB cable is connected. The TPS2560/61power-distribution switches are intended for applications where heavy capacitive loads are likely to beencountered. The TPS2560/61 has two controllable outputs that can be controlled via the TUSB9260GPIO terminals. In the example implementation the TUSB9260 is used to switch power on or off to theSATA device by controlling the EN2 terminal on the TPS2561.

3 USB Connection

There are three sets of differential pairs for connecting the USB port; one set for High-Speed and two setsfor SuperSpeed.

3.1 High-Speed Differential Routing

The high-speed differential pair (USB_DM and USB_DP) is connected to a USB type B connector. Thedifferential pair traces should be routed with 90-Ω, ±15% differential impedance. The high-speed signalpair should be trace length matched. Maximum trace length mismatch between High-Speed USB signalpairs should be no greater than 150 mils. Keep total trace length to a minimum. Route differential tracesfirst. Route the differential pairs on the top or bottom layers with the minimum amount of vias possible. Notermination or coupling caps are required. If a common mode choke is required then place the choke asclose as possible to the USB connector signal pins. Likewise ESD clamps should also be placed as closeas possible to the USB connector signal pins (closer than the choke).

In order to minimize cross-talk on the USB2/3 differential signal pairs, it is recommended that the spacingbetween the two interfaces be five times the width of the trace (5W rule). For instance, if the SS USBTX/RX differential pair trace widths are 5 mils, then there should be 25 mils of space (air gap) between theTX and RX differential pairs and the DP/DM differential pair.




SATA Connection www.ti.com

If this 5W rule cannot be implemented, then the space between the TX/RX differential pairs and DP/DMdifferential pairs should be maximized as much as possible and ground-fill should be placed between thetwo. In this case, it is better to route each differential pair on opposite sides of the board with a groundplane between them.

3.2 SuperSpeed Differential Routing

SuperSpeed consists of two differential routing pairs, a transmit pair (USB_SSTXM and USB_SSTXP) anda receive pair (USB_SSRXM and USB_SSRXP). Each differential pair’s traces should be routed with90-Ω, ±15% differential impedance. The high-speed signal pair should be trace length matched. Maximumtrace length mismatch between SuperSpeed USB signal pairs should be no greater than 2.5 mils. Thetransmit differential pair does not have to be the same length as the receive differential pair. Keep totaltrace length to a minimum. Route differential traces first. Route the differential pairs on the top or bottomlayers with the minimum amount of vias possible. The transmitter differential pair requires 0.1-µF couplingcaps for proper operation. The package/case size of these caps should be no bigger than 0402. C-packsare not allowed. The caps should be placed symmetrically as close as possible to the USB connectorsignal pins. If a common mode choke is required then place the choke as close as possible to the USBconnector signal pins (closer than the transmitter caps). Likewise ESD clamps should also be placed asclose as possible to the USB connector signal pins (closer than the choke and transmitter caps).

It is permissible to swap the plus and minus on either or both of the SuperSpeed differential pairs. Thismay be necessary to prevent the differential traces from crossing over one another. However it is notpermissible to swap the transmitter differential pair with receive differential pair.

In order to minimize cross-talk on the SS USB differential signal pairs, it is recommended that the spacingbetween the TX and RX signal pairs be five times the width of the trace (5W rule). For instance, if the SSUSB TX/RX differential pair trace widths are 5 mils, then there should be 25 mils of space (air gap)between the TX and RX differential pairs.

If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should bemaximized as much as possible and ground-fill should be placed between the two. In this case, it is betterto route each differential pair on opposite sides of the board with a ground plane between them.

4 SATA Connection

The TUSB9260 supports one 3G SATA port operating at 1.5 GHz or 3 GHz depending on the maximumspeed of the attached device.

4.1 SATA Differential Routing

The SATA traces (SATA_TXP and SATA_TXM) should be routed with 100-Ω, ±15% differentialimpedance. Maximum trace length mismatch between SATA signal pairs should be no greater than2.5 mils. Transmit differential pair does not have to be the same length as receive differential pair. Keeptotal trace length to a minimum. Route differential traces first. Route the differential pairs on the top orbottom layers with the minimum amount of vias possible. Each SATA trace requires a coupling capacitorbe placed inline. The package/case size of these caps should be no bigger than 0402. C-packs are notallowed. The caps should be placed symmetrically as close as possible to the SATA connector signalpins.

It is permissible to swap the plus and minus on the SATA differential pair. This may be necessary toprevent the differential traces from crossing over one another. However it is not permissible to swap thetransmitter diff pair with the receive diff pair.

In order to minimize cross-talk on the SATA differential signal pairs, it is recommended that the spacingbetween the TX and RX signal pairs for each interface be five times the width of the trace (5W rule). Forinstance, if the SATA TX/RX differential pair trace widths are 5 mils, then there should be 25 mils of space(air gap) between the TX and RX differential pairs.

If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should bemaximized as much as possible and ground-fill should be placed between the two. In this case, it is betterto route each differential pair on opposite sides of the board with a ground plane between them.




www.ti.com ESD Protection

5 ESD Protection

The TUSB9260 provides ESD protection on all signal and power pins up to 2000 V using the human bodymodel and 500 V using the charged device model. If more protection is required, the TI TPD2EUB30 canbe used as this device meets or exceeds IEC61000-4-2 (Level 4) requirements. This device can be usedon any of the differential pairs of the TUSB9260. Place the device as close as possible to the signal pinsof the connector. Refer to the datasheet for more information regarding this device.

6 GPIO Terminals

The TUSB9260 supports a minimum of 12 GPIOs. Some GPIO terminals have dual functionalitydepending on how they are configured.

6.1 GPIO[7:0]

GPIO terminals 7 through 0 can be used for general purpose use such as connecting activity LEDs, usedas push-button input, or connected to various signals from other devices. Each GPIO terminal has internalpull-down resistors. If a GPIO terminal is not used it should be left unconnected.

6.2 GPIO[8/UART_RX:9/UART_TX]

GPIO terminals 8 and 9 are dual function terminals. They can be used as general purpose input/outputterminals like GPIO[7:0] or they can be configured as an UART interface. Both terminals have internalpull-up resistors, so they can be left unconnected if not used.

6.3 GPIO[10/SPI_CS2:11/SPI_CS1]

GPIO terminals 10 and 11 are dual function terminals. They can be used as general purpose input/outputterminals like GPIO[7:0] or they can be configured as SPI chip select terminals for additional peripheralssuch as an LCD driver. Both terminals have internal pull-up resistors, so they should be left unconnected ifnot used.

7 PWM Terminals

The TUSB9260 has two pulse width modulated (PWM) terminals. These terminals are always outputs.They should be left unconnected if not used.

8 JTAG Interface

The TUSB9260 supports JTAG for board level test and debug support. Typically these terminals are leftunconnected or routed to a header to plug in an external JTAG controller. Table 2 shows the JTAGterminal names and internal resistor connection. The JTAG interface should be left unconnected if JTAGsupport is not required.

Table 2. Internal JTAG Resistor Termination

NAME PULL-UP OR PULL-DOWN DESCRIPTION

JTAG_TCK Pull-down JTAG test clock

JTAG_TDI Pull-up JTAG test data in

JTAG_TDO Pull-down JTAG test data out

JTAG_TMS Pull-up JTAG test mode select

JTAG_RSTZ Pull-down JTAG reset

9 External Reference Clock

The TUSB9260 requires an external reference clock. This clock can be derived from an existing clock,crystal, or oscillator. The TUSB9260 supports one clock frequency as shown in Table 3. FREQSEL[1:0]terminals can be connected directly to ground or tied to VDD33.




54

53

30

31

4

52

External Reference Clock www.ti.com

Table 3. External Reference Clock Selection

FREQSEL[1:0] INPUT FREQUENCY (MHz)

00b Reserved

01b Reserved

10b Reserved

11b 40

9.1 Crystal Selection

Select a fundamental mode crystal with load capacitance of 12 pF – 24 pF and PPM rating of ±100 PPMor better. Connect the crystal between the XI and XO terminals with a 1-MΏ shunt resistor as shown inFigure 2. Place the crystal near the XI and XO terminals. Try to keep the XI and XO traces to a minimumlength with few or no vias as shown in Figure 3.

Figure 2. Example Crystal Implementation




www.ti.com External Reference Clock

Figure 3. Example Reference Clock Layout

9.2 External Clock/Oscillator Selection

When using an external clock source such as an oscillator, the reference clock should have ±100 PPM (orbetter) frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak topeak jitter after applying the USB 3.0 jitter transfer function.

Connect the output of the clock source or oscillator to the XI terminal. Leave the XO terminal unconnectedas shown in Figure 4. Try to keep the clock trace to a minimum length with few or no vias.

Note that the TUSB9260 has a VSSOSC terminal. This terminal is the reference ground for the internaloscillator. This reference ground should be used for the crystal circuit, which is also shown in Figure 4.




54

53

30

31

4

52

17

1820

21

Pm25LV512A

SOIC_8S

Pm25LV512A

SOIC_8S

Serial Peripheral Interface (SPI) www.ti.com

Figure 4. Example Oscillator Implementation

10 Serial Peripheral Interface (SPI)

A SPI system consists of one master device and one or more slave devices. The TUSB9260 is a SPImaster providing the SPI clock, data-in, data-out and up to three chip select terminals.

The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a low active ChipSelect terminal (SPI_CS[2:0]#). Data is transmitted with a 3-terminal interface consisting of terminals forserial data input (SPI_DATA_IN), serial data output (SPI_DATA_OUT) and serial clock (SPI_SCLK). AllSPI terminals have integrated pull-up resistors. No external components are required to connect the SPIinterface to an external SPI flash device. See Figure 5 for an example implementation of the SPI interfaceusing one SPI slave device.

Figure 5. SPI Connection

The SPI interface can operate over a frequency range of 100 kHz to 50 MHz. The word size for the flashmust be 8 bits. A minimum flash size of 512 kbits (64 k x 8) is recommended. Table 4 shows SPI flashdevices that have been tested with the TUSB9260.




www.ti.com Precision Reference Return Resistor

Table 4. Flash Devices Tested on the TUSB9260

MAX CLOCK FREQUENCYDENSITY PAGE SIZEMANUFACTURER PART NUMBER READ COMMAND(kbit) (bytes) (MHz)

Numonyx/ST M25P05A 512 256 20 / 25

Numonyx/ST M25P10A 1024 256 20 / 25

Atmel AT25FS010 1024 256 50

Pflash Pm25LV512A 512 256 33

Pflash Pm25LV010A 1024 256 33

11 Precision Reference Return Resistor

The TUSB9260 requires an external precision reference return resistor. This resistor is part of the USB2.0PHY core used for internal calibration. A 10-kΩ, ±1% (1/20 W or greater) precision resistor should beplaced between terminals USB_R1 and USB_R1RTN. This resistor should be placed no further than500 mils from the two terminals.

12 External PLL Loop Capacitors

There are three terminals on the TUSB9260 that require external capacitors. These are the external loopcapacitors for each of the three PLL’s in the TUSB9260. CEXT0 terminal is used for the USB 2.0 PHYPLL, CEXT1 terminal is used for the SuperSpeed PHY PLL, and terminal CEXT2 is used for the SATAPLL.

All three CEXTx terminals require a 4.7-nF capacitor connected to ground. Each capacitor should beplaced within 500 mils of its associated terminal and provide adequate shielding from external noisesources.

13 Example Schematics

The following schematic is provided as a reference design. There is one user configurable jumper (J4) onthe board. A jumper must be placed across pins 1 and 2 or across pins 2 and 3 depending on the desiredpower option. When the jumper is placed across pins 1 and 2 a flash drive can be powered directly fromthe USB cable power eliminating the need for an external wall-wart. However it should be noted that SATAdevices that require 12 V will not operate in this mode. To support all SATA devices place the jumperacross pins 2 and 3 and connect a 12-V / 2-A wall-wart to DC jack J3 (positive tip).




5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1. MATCH TO WITHIN 2.5MILS2. 100-ohms DIFFERENTIALIMPEDANCE3. 50-ohms SINGLE-ENDEDIMPEDANCE

1. MATCH TO WITHIN 2.5MILS2. 100-ohms DIFFERENTIALIMPEDANCE3. 50-ohms SINGLE-ENDEDIMPEDANCE

NOTE: TO USE OSCILLATOR IN PLACE OF CRYSTALREMOVE 1M RESISTOR AND 18pF CAPS

ESD PROTECTION

MISC GPIO INDICATORS

SPI ENABLE

SILKSCREEN:GPIO0 (D1): SW_HBGPIO1 (D4): PWR_STATE_0GPIO2 (D2): HS_FS_SUSPEND#GPIO3 (SW1): PBUTTON#GPIO4: SELF_PWRGPIO5 (D7): PWR_STATE_1GPIO6 (D5): HS_FS_CONNECT#GPIO7 (D8): SS_CONNECT#GPIO8: UART_RXGPIO9: UART_TXGPIO10: SATA_ENGPIO11: FAULT#PWM0 (D3): HDD_ACT#PWM1 (D6): MISC_LED0#

40MHz crystal

The SATA TX differential pair were swapped tosimplify the EVM board layout. THe 9260firmware provided by TI takes this swap intoaccount.

* 11 = 40MHz

CAP_SATATXMCAP_SATATXP

CAP_SATARXMCAP_SATARXP

SATATXM

SATARXP

SSRXP

CAP_SSTXM

US_DM

CAP_SSTXPSSTXM

US_DP

SSTXP

SSRXM

VSSOSC

XI

FREQSEL0FREQSEL1

UART_RXUART_TX SPI_SCK

SPI_CE#

USB_R1

USB_R1RTN

VDD2VDD1VDD0

CN_VBUS

XO

FUSE_12V

SW_HBPWR_STATE_0HS_FS_SUSPEND#PBUTTON#

PWR_STATE_1HS_FS_CONNECT#SS_CONNECT#

HDD_ACT#MISC_LED0#

SELF_PWR

SW_HB

PWR_STATE_0

PWR_STATE_1

HS_FS_SUSPEND#

HS_FS_CONNECT#

SS_CONNECT#

HDD_ACT#

MISC_LED0#PBUTTON#

SELF_PWR

CAP_SSTXM

CAP_SSTXP

SSRXM

SSRXP

US_DM

US_DP

SATATXP

SATARXM

SPI_SO_J

SPI_SOSPI_SI

VDD_3P3V

BOARD_3P3V

BOARD_1P8V

BOARD_3P3V SATA_5V

BOARD_12V

VDD_1P1V VDDA_1P8V VDDA_3P3V

BOARD_3P3V BOARD_3P3V BOARD_3P3V BOARD_3P3V

VBUS

BOARD_12V

VDD_3P3V

VDD_1P1V USB2_1P1V

GRST#

SATA_ENFAULT#

Sheet of

SIZE

SCALE: NONE

DWG NO: TUSB9260

TUSB9260 EVM

Saturday, January 29, 2011

C

1 2Sheet of

SIZE

SCALE: NONE

DWG NO: TUSB9260

TUSB9260 EVM


C

1 2Sheet of

SIZE

SCALE: NONE

DWG NO: TUSB9260

TUSB9260 EVM


C

1 2

R4110R4110

R14

330

R14

330

J2

Conn USB3_B_AKAK4AA009K1MainSuper

J2

Conn USB3_B_AKAK4AA009K1MainSuper

VBUS1

DM2

DP3

GND4

SSTXN5

SSTXP6

GND7

SSRXN8

SSRXP9

SHIELD010

SHIELD111

D7

LED Green 0805

D7

LED Green 0805

R13 NOPOPR13 NOPOP

R5 NOPOPR5 NOPOP

C2 0.01uFC2 0.01uF

R410K 1%R410K 1%

R9

1M

0402

R9

1M

0402

R19

330

R19

330

U11

TPD2EUSB30

U11

TPD2EUSB30

D+1

D-2 GND

3

R4010R4010

R16

330

R16

330

C5

4.7nF

C5

4.7nF

TUSB9260PAP U5TUSB9260PAP U5

PWM02

PWM13

GRSTZ4

UART_RX_GPIO85

UART_TX_GPIO96

GPIO08

GPIO19

GPIO210

GPIO311

GPIO413

GPIO514

GPIO615

GPIO716

SPI_CS021

SPI_CS1_GPIO1022

SPI_CS2_GPIO1123

FREQSEL030

FREQSEL131

XI52

VSSOSC53 XO54

SATA_TXM56

SATA_TXP57

SATA_RXM59

SATA_RXP60

SPI_SCLK17

SPI_DATA_IN18

SPI_DATA_OUT20

JTAG_TCK25JTAG_TDI26JTAG_TDO27JTAG_TMS28JTAG_TRSTZ29

USB_VBUS33

USB_DM35

USB_DP36

VDD038

USB_R139

USB_R1RTN40

USB_SSTXM42

USB_SSTXP43

USB_SSRXM45

USB_SSRXP46

VDD149

VDD263

VD

D1

VD

DS

HV

7

VD

D1

2

VD

D1

9

VD

DS

HV

24

VD

D3

2

VD

DA

18

37

VD

DR

18

_1

48

VD

DS

HV

50

VD

D4

1

VD

D3

35

1

VD

DR

18

_2

62

VD

D4

4

VS

S6

5

VD

D4

7

VD

D5

5

VD

D5

8

VD

D6

1

VD

D6

4

VD

DA

33

34

+ C10220uF

+ C10220uF

R38

NOPOP

R38

NOPOP

R37 NOPOPR37 NOPOP

C19

18pF

C19

18pF

C16

.001uF

C16

.001uF

R8 NOPOPR8 NOPOP

R25

10K

R25

10K

C17

18pF

C17

18pF

D2

LED Green 0805

D2

LED Green 0805

R690.9K 1%R690.9K 1%

C6 0.01uFC6 0.01uF

R12 4.7kR12 4.7k

CN1

10031569-001LF

CN1

10031569-001LF

GNDS1

A+S2

A-S3

GNDS4

B-S5

B+S6

GNDS7

V33P1

V33P2

V33P3

GNDP4

GNDP5

GNDP6

V5P7

V5P8

V5P9

GNDP10

DAS/DSSP11

GNDP12

V12P13

V12P14

V12P15

R22

330

R22

330

F1

PTC FUSE

F1

PTC FUSE

C3

4.7nF

C3

4.7nF

J13

HDR2X1 M .1

J13

HDR2X1 M .1

1 2

D4

LED Green 0805

D4

LED Green 0805

R7

10K

1%

R7

10K

1%

R4210R4210

R20

330

R20

330

D5

LED Green 0805

D5

LED Green 0805

XY1

X OR Y

XY1

X OR Y

XO1

GND2

VCC4

XI3

D3

LED Green 0805

D3

LED Green 0805

N.O.

SW1PB_SWITCH

N.O.

SW1PB_SWITCH

12

43

C15

.1uF

C15

.1uF

D1

LED Green 0805

D1

LED Green 0805

R23 NOPOPR23 NOPOP

R29

0

R29

0

R1

0

R1

0

R21

330

R21

330

C8

22uF

C8

22uF

R11 NOPOPR11 NOPOP

C45

1uF

C45

1uF

C140.1uF C140.1uF

C7 0.01uFC7 0.01uF

D8

LED Green 0805

D8

LED Green 0805

D6

LED Green 0805

D6

LED Green 0805

U10

TPD2EUSB30

U10

TPD2EUSB30

D+1

D-2 GND

3

U12

TPD2EUSB30

U12

TPD2EUSB30

D+1

D-2 GND

3

+ C12220uF

+ C12220uF

R24

3.65K

R24

3.65K

C2018pFC2018pF

C4

4.7nF

C4

4.7nF

U2

Pm25LV512A

SOIC_8S

U2

Pm25LV512A

SOIC_8S

CE#1

SO2

WP#3

GND4

SI5SCK6HOLD#7VCC8

C18

0.1uF

C18

0.1uF

R28

0

R28

0

C11

0.1uF

C11

0.1uF

R10 4.7KR10 4.7K

C130.1uF C130.1uF

C1 0.01uFC1 0.01uF

R3

4.7K

R3

4.7K

R18

330

R18

330

R2

4.7K

R2

4.7K

J1

NOPOP

J1

NOPOP

123

R15

330

R15

330R17

4.7K

R17

4.7K

Example Schematics www.ti.com




5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NOTE: USE LOW ESR CAP

NOTE: USE LOW ESR CAP

5V REGULATOR

STAR GROUND AGND TO GND

3.3V, 1.8V AND 1.1V REGULATOR

POWER SWITCH

VBUS SELECT

TUSB9260 DECOUPLING

CABLE POWERED

SELF POWERED

BOOT PH

VSENSE

ILIM1

SW_1.1VFB_DCDC

MODE

TRSTMR#

BOARD_12VREG_5V

BOARD_1P8V

VDD_1P1V

VDD_1P1V

USB2_1P1V

VDDA_1P8V

VDD_3P3VBOARD_3P3V

VDDA_3P3V

SOURCE_5VREG_5V VBUS

SOURCE_5V

BOARD_3P3V

BOARD_3P3V

BOARD_5V SATA_5V

VDD_1P1V

BOARD_1P8V

BOARD_3P3V

BOARD_5V

AA

A

A

A

SATA_ENFAULT#

GRST#

Sheet of

SIZE

SCALE: NONE

DWG NO: POWER

TUSB9260 EVM

Wednesday, August 11, 2010

C

2 2Sheet of

SIZE

SCALE: NONE

DWG NO: POWER

TUSB9260 EVM


C

2 2Sheet of

SIZE

SCALE: NONE

DWG NO: POWER

TUSB9260 EVM


C

2 2

C3222uFC3222uF

C54

0.1uF

C54

0.1uF

R35

4.7K

R35

4.7K

C23

0.01uF

C23

0.01uF

C59

0.01uF

C59

0.01uF

C26

0.1uF

C26

0.1uF

C37

0.1uF

C37

0.1uF

R33

10K

0402

5%

R33

10K

0402

5%

C3322uFC3322uF

U4

TPS650061

U4

TPS650061

VINDCDC8

EN_DCDC10

MODE9

VINLDO115

EN_LDO13

VINLDO218

EN_LDO24

PGND6

AGND12

PG#5

SW7

FB_DCDC11

VLDO114

VLDO217

FB_LDO113

FB_LDO216

RSTSNS19

RST#20MR#

1TRST

2

PWR_PAD21

C67

0.1uF

C67

0.1uF

T

S

J3

2.1mm x 5.5mm

T

S

J3

2.1mm x 5.5mm

1

23

FB2

220 @ 100MHZ

FB2

220 @ 100MHZ

R27

3.16K

1%

R27

3.16K

1% + C30

1000uF

+ C30

1000uF

FB1

220 @ 100MHZ

FB1

220 @ 100MHZ

C38

0.01uF

C38

0.01uF

C61

1uF

C61

1uF

R30

400K

0402

1%

R30

400K

0402

1%

R34NOPOPR34NOPOP

J4

HDR

J4

HDR

123

C25

1uF

C25

1uF

C58

0.1uF

C58

0.1uF

C43

0.1uF

C43

0.1uF

C72

30pF

C72

30pF

C6222uFC6222uF

R26

10K

1%

R26

10K

1%

R39

4.7K0402

R39

4.7K0402

C36

0.1uF

C36

0.1uF

L2

2.2uH

L2

2.2uH

C22

0.01uF

C22

0.01uF

C42

0.01uF

C42

0.01uF

C6422uFC6422uF

C6322uFC6322uF

C28

0.1uF

C28

0.1uF

C31

0.1uF

C31

0.1uF

C4622uFC4622uF

D12

MBRS540T3

D12

MBRS540T3

C40

0.1uF

C40

0.1uF

C35

0.1uF

C35

0.1uF

C6022uFC6022uF

R31475K

04021%

R31475K

04021%

FB4

220 @ 100MHZ

FB4

220 @ 100MHZ

C2422uFC2422uF

C29

0.01uF

C29

0.01uF

C69

0.1uF

C69

0.1uF

C66

0.1uF

C66

0.1uF

C39

0.1uF

C39

0.1uF

FB5

220 @ 100MHZ

FB5

220 @ 100MHZ

C34

1uF

C34

1uF

C5722uFC5722uF

C68

0.1uF

C68

0.1uF

L1

15uH

L1

15uH

C27

0.1uF

C27

0.1uF

U7

TPS2560DRC

U7

TPS2560DRC

GND1

IN2

IN3

EN14

EN25

FAULT2Z6

ILIM7

OUT28

OUT19

FAULT1Z10

PAD11

+ C21220uF

+ C21220uF

R36

27.4K

0402

5%

R36

27.4K

0402

5%

C44

0.1uF

C44

0.1uF

N.O.

SW2PB_SWITCH

N.O.

SW2PB_SWITCH

12

43

U3

TPS5450

U3

TPS5450

BOOT1

NC2

NC_3

VSENSE4

ENA5GND6VIN7PH8

GN

D9

R32

4.7K04025%

R32

4.7K04025%

C41

0.1uF

C41

0.1uF

www.ti.com Example Schematics




IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and www.ti.com/automotiveAutomotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps

RF/IF and ZigBee® Solutions www.ti.com/lprf

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2011, Texas Instruments Incorporated

http://www.ti.com/audio

http://www.ti.com/communications

http://amplifier.ti.com

http://www.ti.com/computers

http://dataconverter.ti.com

http://www.ti.com/consumer-apps

http://www.dlp.com

http://www.ti.com/energy

http://dsp.ti.com

http://www.ti.com/industrial

http://www.ti.com/clocks

http://www.ti.com/medical

http://interface.ti.com

http://www.ti.com/security

http://logic.ti.com

http://www.ti.com/space-avionics-defense

http://power.ti.com

http://www.ti.com/automotive

http://microcontroller.ti.com

http://www.ti.com/video

http://www.ti-rfid.com

http://www.ti.com/wireless-apps

http://www.ti.com/lprf

http://e2e.ti.com

Documents

TUSB9260 Implementation Guide (Rev. C)